NCP81143MNTXG

NCP81143 Multiple-Phase Controller with SVID Interface for Desktop and Notebook CPU Applications The NCP81143 Multi−Phase buck solution is optimized for Intel VR12.5 compatible CPUs with user configurations of 3/2/1 phases this controllers combines true differential voltage sensing, differential inductor DCR current sensing, input voltage feed−forward, and adaptive voltage positioning to provide accurately regulated power for both Desktop and Notebook applications. The control system is based on Dual−Edge pulse−width modulation (PWM) combined with DCR current sensing providing the fastest initial response to dynamic load events at reduced system cost. They have the capability to shed to single phase during light load operation and can auto frequency scale in light load conditions while maintaining excellent transient performance. The NCP81143 offers two internal MOSFET drivers with a single external PWM signal. High performance operational error amplifiers are provided to simplify compensation of the system. Patented Dynamic Reference Injection further simplifies loop compensation by eliminating the need to compromise between closed−loop transient response and Dynamic VID performance. Patented Total Current Summing provides highly accurate digital current monitoring. Features http://onsemi.com MARKING DIAGRAM 1 1 NCP 81143 AWLYYWWG G 36 QFN36 CASE 485CC A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 33 of this data sheet. • NCP81143 and Meets Intel® VR12.5 specifications • Current Mode Dual Edge Modulation for Fastest Initial Response to • • • • • • • • • • • • Transient Loading High Performance Operational Error Amplifier Digital Soft Start Ramp Dynamic Reference Injection Accurate Total Summing Current Amplifier Dual High Impedance Differential Voltage and Total Current Sense Amplifiers Phase−to−Phase Dynamic Current Balancing “Lossless” DCR Current Sensing for Current Balancing True Differential Current Balancing Sense Amplifiers for Each Phase Adaptive Voltage Positioning (AVP) Switching Frequency Range of 200 kHz –1 MHz Vin range 4.5 V to 25 V Startup into Pre−Charged Loads While Avoiding False OVP © Semiconductor Components Industries, LLC, 2013 October, 2013 − Rev. 0 • • • • • • • Power Saving Phase Shedding Vin Feed Forward Ramp Slope Pin Programming for Internal SVID parameters Over Voltage Protection (OVP) & Under Voltage Protection (UVP) Over Current Protection (OCP) VR−RDY Output with Internal Delays These are Pb−Free Devices Applications • Desktop & Notebook Processors 1 Publication Order Number: NCP81143/D DVIDFF VSN VSP DAC GND CSCOMP CSREF CSSUM IOUT ILIM COMP FB DIFFOUT NCP81143 CS AMP &LIMIT ERROR AMP DIFFAMP CSREF ERROR_AMP TSENSE VSP OVP OVP VSN THERMAL MONITOR VRHOT ENABLE VSP−VSN TSENSE SDIO SVIDINTERFACE SCLK TRANSIENT DETECTION ENABLE VSP VR READY COMPARATOR INT_SEL IOUT IMAX DVIDFF ERROR_AMP CSP3 VSN DAC CURRENT BALANCE IPH1 CSP2 CSP1 RAMP1 RAMP2 RAMP3 RAMP GENERATORS OVP PWM GENERATORS COMP ENABLE ENABLE GND UVLO&EN VCC ENABLE DRON HG3 SW3 BST3 PWM2/IMAX HG1 SW1 BST1 LG1 PGND VRMP PVCC POWERSTATE STAGE ROSC VRDY CURRENT BALANCE DAC DAC MUX ADC LG3 ALERT DATA REGISTERS Figure 1. Block Diagram for NCP81143 http://onsemi.com 2 NCP81143 J2 5PIN J23 1 R68 J1 5PIN +5V_IN SDIO {5} SCLK {5} ALERT# {5} V_1P05_VCCP R187 392 7 VSN {4} U15A NL37WZ07 SER_EN C67 510pF J47 1 1 {4} ENABLE {4} VR_RDY J45 1 J26 J61 J63 J62 C86 1uF J28 1 V5S CSCOMP 26.1K ILIM 2 2 IOUT 1 2 3 4 5 6 7 8 9 ENABLE VR_HOT SDIO ALERT SCLK VR_RDY ROSC TSENSE INT_SEL J19 1 VCC3 CSCOMP CSSUM CSREF U6 CSP3 NCP81143 CSP2 CSP1 DRON PWM2/IMAX BST3 V5S C31 4.7uF R140 105K 1 2 R139 105K 1 2 R138 105K 1 2 CSREF 2 27 26 25 24 23 22 21 20 19 BST3 HG3 SW3 LG3 R12 1 R191 VDC {3} 1 J22 PWM2 J21 DRON C82 0.01uF 1 CSSUM CSREF CSP3 CSP2 CSP1 1 C85 1 R8 1 DNP 1 R193 0.1uF C83 0.1uF R29 2 2 R28 2 2 R189 100k 4.7K 1 VRMP BST3 HG3 SW3 LG3 R27 2 4.7K 1 R40 1.0K DNP 10.0 2 10.0 2 DNP J39 R37 1 1K 2 C56 R5049.9 1000pF 1 2 1 2 VCCU VCCU SWN3 {3} VCCU CSN3 {3} VCCU CSN2 {3} CSN1 {3} SWN2 {3} J40 1 C57 1 2 J41 C55 2200pF 10pF 2 2 1 R433.01K COMP R132 165K R10 2 10.0 2 DNP 1FB R38 1 1 C79 1uF COMP FB DIFFOUT VSN VSP 2 BST1 HG1 SW1 LG1 R131 75.0K 1 CSSUM R4 1 DNP 1 R195 1 1 1 R712.2 2 C610.1uF J56 1 BST1 HG1 SW1 LG1 1 RT130 220K place close to L1 C156 560pF VR_HOT SDIO ALERT# SCLK VR_RDY ROSC TSENSE {4} VR_HOT 1 1 1 1 1 C155 1500pF J42 2 C80 0.1uF 1DIFFOUT V_1P05_VCCP SER_VR_RDY {4} SER_EN 100 2 2.1K C51 1000pF VSP {4} R154 97.6K INT_SEL R18 13.7K 2 2 1 2 J59 20PIN 2ROW 1 3 5 7 9 11 13 15 17 19 R34 1 0.0 2 2 R2 1 J13 2 1 2 R184 45K 1 4.7K 1 1 1 2 4 6 8 10 12 14 16 18 20 {5} VSS_SENSE 1 2PIN 100 0.0 1 R3 R48 VSENSE TSENSE R125 0.0 1 1 2 2 place close to L1 R32 8.25K J27 2 1 8 ILIM CSP1 CSP2 R9 2 SWN1 {3} 3 2 DNP 1 http://onsemi.com {5} VCC_SENSE VCCU RT126 100K JP5 ETCH R19 DNP 1 1 R127 DNP CSP3 R30 2 Figure 2. Reference Schematic 37 36 35 34 33 32 31 30 29 28 EPAD VCC VSP VSN DIFFOUT FB COMP VRMP IOUT ILIM BST1 HG1 SW1 LG1 PGND PVCC LG3 SW3 HG3 10 11 12 13 14 15 16 17 18 2 VCCU C94 0.1uF J29 CSP2 CSP3 1 2 1 1 2 2 1 2 DNP 1 R15775.0 1 R160 2 2 DNP 1 R15654.9 1 DNP 1 R15564.9 1 R158 2 R159 2 2 4 1 2 2 1 2 CSCOMP 1 2 1 1 2 1 2 1 2 V5S 1 2 NCP81143 BST1 R45 49.9 {2} PWM2 {2} DRON R164 1 0.0 2 TP14 C1 10uF C2 10uF C3 10uF L1 .36uH MCPG1040LR36C C7 10uF C5 10uF 2 C6 10uF VDC C203 10uF SWN1 {2} CSN1 {2} VCCU C9 10uF C12 10uF 2 BST3 JP21 LG3 SW3 HG3 R166 0.0 1 2 C13 10uF TP15 DRVH3 C37 0.22uF HG3 SW3 LG3 TP18 4 DRVL3 4 1000pF C103 TP10 C34 10uF SW3 C35 C36 10uF L2 .36uH MCPG1040LR36C 10uF 1 2 10uF C202 JP19 2 C10 10uF ETCH 2 SHORTPIN R194 DNP JP18 1 1 1 2 1 C11 10uF VCCU SWN3 {2} CSN3 {2} 2 VDC 1 2 Q8 NTMFS4821N 4 4 Q10 NTMFS4852N 1 2 Q7 NTMFS4821N Q9 NTMFS4852N 1 2 VDC JP20 C201 10uF 1 SHORTPIN ETCH 2 R190 DNP JP14 1 C8 10uF 1 1 2 Q3 NTMFS4821N C101 1000pF TP8 SW1 Q26 NTMFS4821N C102 1000pF TP9 SW2 2 Q2 NTMFS4821N 4 Q5 NTMFS4852N Q20 NTMFS4821N 4 VCCU 1 2 DRVH1 4 4 4 SHORTPIN 1 1 L3 .36uH MCPG1040LR36C R192 DNP 3 2 1 C4 0.22uF HG1 TP17 DRVL1 TP13 TP16 DRVL2 CSN2 {2} Figure 3. Power Stage Schematic HG1 SW1 LG1 DRVH2 C28 0.22uF HG2 SW2 LG2 4 SWN2 {2} 4 4 8 Q4 NTMFS4852N R165 0.0 1 2 HG SW 7 LG GND 6 4 ETCH 2 http://onsemi.com 5 6 7 8 1 2 5 6 7 8 3 2 1 3 2 1 1 1 1 2 5 6 7 8 5 6 7 8 3 2 1 SW1 EN PWM BST U8 NCP5911 1 2 3 45 VCC PAD JP16 1 1 2 LG1 V5S R5 0.0 VCC3 C29 4.7uF Q27 NTMFS4852N 1 2 1 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 1 3 2 1 3 2 1 Q22 NTMFS4852N 1 3 2 1 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 1 2 3 2 1 3 2 1 5 6 7 8 5 6 7 8 1 1 1 1 1 2 5 6 7 8 3 2 1 3 2 1 5 6 7 8 3 2 1 2 1 1 2 1 2 VCC VSP VSN DIFFOUT FB COMP VRMP IOUT ILIM 36 35 34 33 32 31 30 29 28 NCP81143 ENABLE 1 27 CSCOMP VR_HOT 2 26 CSSUM SDIO 3 25 CSREF ALERT 4 24 CSP3 SCLK 5 23 CSP2 VR_RDY 6 22 CSP1 ROSC 7 21 DRON TSENSE 8 20 PWM2/IMAX INT_SEL 9 19 BST3 NCP81143 10 1 12 13 14 15 16 17 18 BST1 HG1 SW1 LG1 PGND PVCC LG3 SW3 HG3 TAB: GROUND Figure 4. NCP81143 Pin Configuration NCP81143 SINGLE ROW PIN DESCRIPTIONS Pin No. Symbol 1 ENABLE 2 VR_HOT# 3 SDIO 4 ALERT# Description Logic input. Logic high enables both outputs and logic low disables both outputs Thermal logic output for over temperature Serial VID data interface Serial VID ALERT#. 5 SCLK 6 VR_RDY Serial VID clock 7 ROSC 8 TSENSE Temp Sense input for the multiphase converter 9 INT_SEL An input pin to adjust programmable integrator setting. During start up it is used to program INT_SEL with a resistor to ground 10 BST1 High−Side bootstrap supply for phase 1. 11 HG1 High side gate driver output for phase 1 12 SW1 Current return for high side gate driver 1 13 LG1 Low−Side gate driver output for phase 1 14 PGND Power Ground for gate drivers 15 PVCC Power Supply for gate drivers 16 LG3 Low−Side gate driver output for phase 3 17 SW3 Current return for high side gate driver 3 18 HG3 High side gate driver output for phase 3 19 BST3 High−Side bootstrap supply for phase 3 20 PWM2/IMAX 21 DRON Open drain output. High indicates that the output is regulating A resistance from this pin to ground programs the oscillator frequency Phase 2 PWM output. Also as ICC_MAX Input Pin. During start up it is used to program ICC_MAX with a resistor to ground Bidirectional gate drive enable output http://onsemi.com 5 NCP81143 NCP81143 SINGLE ROW PIN DESCRIPTIONS Pin No. Symbol Description 22 CSP1 Non−inverting input to current balance sense amplifier for phase 1 23 CSP2 Non−inverting input to current balance sense amplifier for phase 2 24 CSP3 Non−inverting input to current balance sense amplifier for phase 3 25 CSREF Total output current sense amplifier reference voltage input 26 CSSUM Inverting input of total current sense amplifier 27 CSCOMP 28 ILIM Over current shutdown threshold setting. Resistor to CSCOMP to set threshold 29 IOUT Total output current monitor. 30 VRMP Feed−forward input of Vin for the ramp slope compensation. The current fed into this pin is used to control the ramp of PWM slope 31 COMP Output of the error amplifier and the inverting inputs of the PWM comparators 32 FB 33 DIFFOUT 3 VSN Inverting input to differential remote sense amplifier 35 VSP Non−inverting input to the differential remote sense amplifier 36 VCC Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground 37 FLAG /GND Output of total current sense amplifier Error amplifier voltage feedback Output of the differential remote sense amplifier Analog Ground http://onsemi.com 6 NCP81143 ABSOLUTE MAXIMUM RATINGS ELECTRICAL INFORMATION Pin Symbol VMAX VMIN COMP VCC + 0.3 V −0.3 V CSCOMP VCC + 0.3 V −0.3 V VSN GND + 300 mV GND − 300 mV DIFFOUT VCC + 0.3 V −0.3 V VR_RDY VCC + 0.3 V −0.3 V VCC 6.5 V −0.3 V ROSC VCC + 0.3 V −0.3 V IOUT 2.0 V −0.3 V VRMP +25 V −0.3 V SW 35 V 40 V ≤ 50 ns −5 V −10 V ≤ 200 ns BST 35 V wrt/ GND 40 V ≤ 50 ns wrt/GND 6.5 V wrt/ SW −0.3 V wrt/SW LG VCC + 0.3 V −0.3 V −5 V ≤ 200 ns HG BST + 0.3 V −0.3 V wrt/ SW −2 V ≤ 200 ns wrt/SW All Other Pins VCC + 0.3 V −0.3 V *All signals referenced to GND unless noted otherwise. THERMAL INFORMATION Description Thermal Characteristic QFN Package (Note 1) Operating Junction Temperature Range (Note 2) Symbol Typ RqJA 68 TJ −10 to +125 _C −40 to +125 _C _C Operating Ambient Temperature Range Maximum Storage Temperature Range TSTG − 40 to +150 Moisture Sensitivity Level QFN Package MSL 1 *The maximum package power dissipation must be observed. 1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM 2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM http://onsemi.com 7 Unit _C/W NCP81143 NCP81143 ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < TA < 125°C; VCC = 5 V; CVCC = 0.1 mF Parameter Test Conditions Min @ 1.3 V −400 Typ Max Unit 400 nA ERROR AMPLIFIER Input Bias Current Open Loop DC Gain CL = 20 pF to GND, RL = 10 kW to GND 80 dB Open Loop Unity Gain Bandwidth CL = 20 pF to GND, RL = 10 kW to GND 20 MHz DVin = 100 mV, G = −10 V/V, DVout = 1.5 V – 2.5 V, CL = 20 pF to GND, DC Load = 10k to GND 20 V/ms Slew Rate Maximum Output Voltage ISOURCE = 2.0 mA Minimum Output Voltage ISINK = 2.0 mA 3.5 V 1 V −25 25 mA −0.3 3.0 V DIFFERENTIAL SUMMING AMPLIFIER Input Bias Current VSP,VSN = 1.3 V VSP Input Voltage Range VSN Input Voltage Range −3dB Bandwidth Closed Loop DC gain −0.3 0.3 V CL = 20 pF to GND, RL = 10 kW to GND 10 MHz VS+ to VS− = 0.5 to 1.3 V 1.0 V/V CURRENT SUMMING AMPLIFIER −300 Offset Voltage (Vos), (Note 3) Input Bias Current CSSUM = CSREF= 1 V −5 Open Loop Gain Current Sense Unity Gain Bandwidth 300 CL = 20 pF to GND, RL = 10 kW to GND 5 mV mA 80 dB 10 MHz CURRENT BALANCE AMPLIFIER Maximum CSCOMP Output Voltage Minimum CSCOMP Output Voltage Input Bias Current Common Mode Input Voltage Range Differential Mode Input Voltage Range ISOURCE = 2 mA 3.5 V 0.1 V CSP1−3 = CSREF = 1.2 −50 50 nA CSPx = CSREF 0 2.3 V ISINK = 500 mA CSREF = 1.2 V −100 100 mV Input Offset Voltage Matching CSPx = CSREF = 1.2 V, Measured from the average −1.5 1.5 mV Current Sense Amplifier Gain 0 V < CSPx − CSREF < 0.1 V, 5.7 6.3 V/V CSREF= CSP = 10 mV to 30 mV −3 3 % Multiphase Current Sense Gain Matching −3dB Bandwidth 6.0 8 MHz INPUT SUPPLY 4.75 Supply Voltage Range VCC Quiescent Current EN = high, PS0,1,2 Mode 5.25 V 20 mA EN = high, PS3 Mode 11 mA EN = l ow 50 mA UVLO Threshold VCC rising VCC falling VCC UVLO Hysteresis 4.5 4 V 160 3. Guaranteed by design or characterization data, not in production test. http://onsemi.com 8 V mV NCP81143 NCP81143 ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < TA < 125°C; VCC = 5 V; CVCC = 0.1 mF Parameter Test Conditions Min Typ Max Unit 4.25 V INPUT SUPPLY UVLO Threshold VRMP Rising VRMP Falling 3 V DAC SLEW RATE Soft start slew rate 2.5 mv/ms Slew Rate Slow 2.5 mv/ms Slew Rate Fast 10 mv/ms ENABLE INPUT Enable High Input Leakage Current External 1k pull−up to 3.3 V Upper Threshold VUPPER Lower Threshold VLOWER Total Hysteresis VUPPER – VLOWER Enable Delay Time 1.0 0.8 mA V 0.3 90 Measure time from Enable transitioning HI to when DRON goes high V mV 2.5 ms DRON Output High Voltage Sourcing 500 mA Output Low Voltage Sinking 500 mA Rise Time Fall Time 3.0 V 0.1 CL (PCB) = 20 pF, DVo = 10% to 90% 300 EN = Low 70 Internal Pull Down Resistance V ns 10 kW IOUT OUTPUT Input Referred Offset Voltage Output Source Current Current Gain Ilimit to CSREF −3.5 Ilimit sink current = 80 mA (IOUTCURRENT) / (ILIMITCURRENT), RILIM = 20k, RIOUT = 5.0k , DAC = 0.8 V, 1.25 V, 1.52 V 9.67 10 3.5 mV 850 mA 10.32 OSCILLATOR 220 Switching Frequency Range 3 Phase Operation 1000 KHz 1000 kHz OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP) CSREF Absolute Over Voltage Threshold During Soft Start Over Voltage Threshold Above DAC Over Voltage Delay VSP rising 2.9 350 400 V 425 mV VSP rising to PWMx low 50 ns Under Voltage Ckt in development 300 mV Under−voltage Delay Ckt in development 5 ms VR12.5 DAC System Voltage Accuracy −40°C − +125°C 1.5 V ≤ DAC < 3.04 V 1.0 V< DAC < 1.49 V 0.5 V threshold Low Low Disabled Low Start up Delay & Calibration EN > threshold UVLO > threshold Low Low Disabled Low DRON Fault EN > threshold UVLO > threshold DRON < threshold Low Low Disabled Resistive pull up Soft Start EN > threshold UVLO > threshold DRON > High Low Operational Active / No latch High Normal Operation EN > threshold UVLO > threshold DRON > High High Operational Active / Latching High Over Voltage Low N/A DAC + 400 mV High Over Current Low Operational Last DAC Code Low VID Code = 00h Low: if Reg34h:bit0 = 0; High:if Reg34h:bit0 = 1; Clamped at 0.9 V Disabled High, PWM outputs in low state http://onsemi.com 18 Method of Reset Driver must release DRON to high N/A NCP81143 VCC > UVLO Controller POR Disable EN = 1 EN = 0 VCC < UVLO Calibrate Drive Off 3.5 ms CAL DONE VDRP > ILIM NO_CPU INVALID VID Phase Detect VCCP > UVLO and DRON HIGH Soft Start Ramp DAC = Vboot Soft Start Ramp OVP DAC = VID VS > OVP Normal VR_RDY VS > UVP UVP Figure 9. State Diagram http://onsemi.com 19 NCP81143 General The NCP81143 is a three phase dual edge modulated multiphase PWM controller, with a serial SVID control interface. The NCP81143 is optimized to meet Intel’s VR12.5 Specifications and implements PS0, PS1, PS2 and PS3 power saving states. It is designed to work in notebook, desktop, and server applications. Power Status PWM Output Operating Mode PS0 Multi−phase PWM interleaving output PS1 Single−phase RPM CCM mode (PWM1 only, PWM2~3 stay in Mid) PS2 Single−phase RPM DCM mode (PWM1 only, PWM2~3 stay in Mid) PS3 Single−phase RPM DCM mode (PWM1 only, PWM2~3 stay in Mid) The NCP81143 has two integrated drivers and one external PWM signal. Internally, there are 2 PWM signals: PWM1/3, DRV1 is driven by PWM1, DRV3 is driven by PWM3, and the third phase has a PWM output, PWM2, to dive an external driver such as the NCP81151. Phase PWM Output 3 Internal PWM 2 External PWM 1 Internal PWM Serial VID interface (SVID) The Serial VID Interface (SVID Interface) is a three wire digital interface used to transfer power management information between the CPU (Master) and the NCP81143. The 3 wires are clock (SCLK), data (SDIO) and ALERT#. The SCLK is unidirectional and generated by the master. The SDIO is bi−directional, used for transferring data from the CPU to the NCP81143 and from the NCP81143 to the CPU. The ALERT# is an open drain output from the NCP8110 to signal to the master that the Status Register should be read. SCLK, SDIO and ALERT# should be pulled high to CPU I/O voltage Vtt (which is typically 1.0 to 1.1 V) using 55 W Resistors. The SVID bus will operate at a max frequency of 43 MHz. VID code change is supported by SVID interface with three options as below: Option SVID Command Code Feature Description for NCP81143 Register Address (Indicating the slew rate of VID code change) SetVID_Fast 01h >10 mV/ms VID code change slew rate 24h SetVID_Slow 02h =1/4 of SetVID_Fast VID code change slew rate 25h SetVID_Decay 03h No control, VID code down N/A http://onsemi.com 20 NCP81143 Serial VID The NCP81143 supports the Intel serial VID interface. It communicates with the microprocessor through three wires (SCLK, SDIO, ALERT#). The table of supported registers is shown below. Index Name Description Access Default 00h Vendor ID Uniquely identifies the VR vendor. The vendor ID assigned by Intel to ON Semiconductor is 0x1Ah R 0x1Ah 01h Product ID Uniquely identifies the VR product. The VR vendor assigns this number. R 0x13 02h Product Revision Uniquely identifies the revision or stepping of the VR control IC. The VR vendor assigns this data. R 0x01 03h Product date code ID R 00 05h Protocol ID Identifies the SVID Protocol the controller supports R 0x02 06h Capability Informs the Master of the controller’s Capabilities, 1 = supported, 0 = not supported Bit 7 = Iout_format. Bit 7 = 0 when 1A = 1LSB of Reg 15h. Bit 7 = 1 when Reg 15 FFh = Icc_Max. Default = 1 Bit 6 = ADC Measurement of Temp Supported = 1 Bit 5 = ADC Measurement of Pin Supported = 0 Bit 4 = ADC Measurement of Vin Supported = 0 Bit 3 = ADC Measurement of Iin Supported = 0 Bit 2 = ADC Measurement of Pout Supported = 1 Bit 1 = ADC Measurement of Vout Supported = 1 Bit 0 = ADC Measurement of Iout Supported = 1 R 0xC7 10h Status_1 Data register read after the ALERT# signal is asserted. Conveying the status of the VR. R 00h 11h Status_2 Data register showing optional status_2 data. R 00h 12h Temp zone Data register showing temperature zones the system is operating in R 00h 15h I_out 8 bit binary word ADC of current. This register reads 0xFF when the output current is at Icc_Max R 01h 16h V_out 8 bit binary word ADC of output voltage, measured between VSP and VSN. LSB size is 8 mV R 01h 17h VR_Temp 8 bit binary word ADC of voltage. Binary format in °C, IE 100C = 64h. A value of 00h indicates this function is not supported R 01h 18h P_out 8 bit binary word representative of output power. The output voltage is multiplied by the output current value and the result is stored in this register. A value of 00h indicates this function is not supported R 01h 1Ch Status 2 Last read When the status 2 register is read its contents are copied into this register. The format is the same as the Status 2 Register. R 00h 21h Icc_Max Data register containing the Icc_Max the platform supports. The value is measured on the ICCMAX pin on power up and placed in this register. From that point on the register is read only. R 00h 22h Temp_Max R/W 64h 24h SR_fast Slew Rate for SetVID_fast commands. Binary format in mV/us. R 0Ah 25h SR_slow Slew Rate for SetVID_slow commands. It is 16, 8, 4 or 2 times slower than the SR_fast rate. Binary format in mV/us R 02h 26h Vboot The Vboot is set at 1.7 V The controller will ramp to Vboot and hold at Vboot until it receives a new SVID SetVID command to move to a different voltage. R 00h 30h Vout_Max Programmed by master and sets the maximum VID the VR will support. If a higher VID code is received, the VR should respond with “not supported” acknowledge. VR 12.5/6 VID format. RW B5h 31h VID setting Data register containing currently programmed VID voltage. VID data format. RW 00h 32h Pwr State Register containing the current programmed power state. RW 00h Data register containing the max temperature the platform supports and the level VR_hot asserts. This value defaults to 100°C and programmable over the SVID Interface http://onsemi.com 21 NCP81143 Index Name 33h Offset 34h MultiVR Config Description Sets offset in VID steps added to the VID setting for voltage margining. Bit 7 is sign bit, 0 = positive margin, 1= negative margin. Remaining 7 BITS are # VID steps for margin 2s complement. 00h = no margin 01h = +1 VID step 02h = +2 VID steps FFh = −1 VID step FEh = −2 VID steps. Access Default RW 00h BOOT VOLTAGE PROGRAMMING The Boot voltage for the NCP81143 is configured to 1.7 V. The Vboot value can be read back over the SVID interface in registers (0x26). INT_SEL The remote Sense Amplifier output is applied to a Type III compensation network formed by the error amplifier and external tuning components. The non−inverting input of the error amplifier is connected to the same reference voltage used to bias the Remote sense amplifier output. The integrating function of the Type III feedback compensation is performed internally and does not require external capacitor CF1. Figure 10. Type III Compensation Initial tuning should be based on the traditional TYPE III compensation. When ideal Type III component values have been determined, the closest setting for the internal integrator us given by the following equation : INT_SETTING + 4.83 10 −12 RF RF & Rin1 in ohms Rin1 CF1 CF1 in nF Optimization of the traditional Type 3 compensation should be rechecked unin the closest Type 3 CF1 equivalent in order to deternone if readjustment of other component values are required. The Type III CF1 value that is equivalent to the integrator setting is given by the following equation: Cf1(nF) + 2.07 10 5 INT_Settingń(RF http://onsemi.com 22 Rin1) NCP81143 Table 2. RF = 5k and Rin = 1 kW Resistor Range Int_select Setting Phase Count in PS1 Equivalent Cf1 in Type III Compensation Equivalent Rf in Type III Compensation 0 − 5.08 kW 0000 1 43 pF 5 kW 5.08 kW − 14.1 kW 0001 1 82 pF 5 kW 14.1 kW − 21.9 kW 0010 1 160 pF 5 kW 21.9 kW − 30.1 kW 0011 1 330 pF 5 kW 30.1 kW − 39.1 kW 0100 1 430 pF 5 kW 39.1 kW − 48.4 kW 0101 1 510 pF 5 kW 48.4 kW − 57.8 kW 0110 1 680 pF 5 kW 57.8 kW − 67.6 kW 0111 1 1300 pF 5 kW 67.6 kW − 78.1 kW 1000 1 2700 pF 5 kW 78.1 kW − 89.5 kW 0000 2 43 pF 5 kW 89.5 kW − 101 kW 0001 2 82 pF 5 kW 101 kW − 113 kW 0010 2 160 pF 5 kW 113 kW − 125 kW 0011 2 330 pF 5 kW 125 kW − 138 kW 0100 2 430 pF 5 kW 138 kW − 151 kW 0101 2 510 pF 5 kW 151 kW − 163 kW 0110 2 680 pF 5 kW 163 kW − 177 kW 0111 2 1300 pF 5 kW 177 kW − 193 kW 1000 2 2700 pF 5 kW Table 3. RF = 7.5k and Rin = 1 kW Resistor Range Int_select Setting Phase Count in PS1 Equivalent Cf1 in Type III Compensation Equivalent Rf in Type III Compensation 0 − 5.08 kW 0000 1 27 pF 7.5 kW 5.08 kW − 14.1 kW 0001 1 56 pF 7.5 kW 14.1 kW − 21.9 kW 0010 1 110 pF 7.5 kW 21.9 kW − 30.1 kW 0011 1 220 pF 7.5 kW 30.1 kW − 39.1 kW 0100 1 270 pF 7.5 kW 39.1 kW − 48.4 kW 0101 1 330 pF 7.5 kW 48.4 kW − 57.8 kW 0110 1 430 pF 7.5 kW 57.8 kW − 67.6 kW 0111 1 910 pF 7.5 kW 67.6 kW − 78.1 kW 1000 1 1800 pF 7.5 kW 78.1 kW − 89.5 kW 0000 2 27 pF 7.5 kW 89.5 kW − 101 kW 0001 2 56 pF 7.5 kW 101 kW − 113 kW 0010 2 110 pF 7.5 kW 113 kW − 125 kW 0011 2 220 pF 7.5 kW 125 kW − 138 kW 0100 2 270 pF 7.5 kW 138 kW − 151 kW 0101 2 330 pF 7.5 kW 151 kW − 163 kW 0110 2 430 pF 7.5 kW 163 kW − 177 kW 0111 2 910 pF 7.5 kW 177 kW − 193 kW 1000 2 1800 pF 7.5 kW http://onsemi.com 23 NCP81143 Table 4. RF = 10k and Rin = 1 kW Resistor Range Int_select Setting Phase Count in PS1 Equivalent Cf1 in Type III Compensation Equivalent Rf in Type III Compensation 0 − 5.08 kW 0000 1 20 pF 10 kW 5.08 kW − 14.1 kW 0001 1 43 pF 10 kW 14.1 kW − 21.9 kW 0010 1 82 pF 10 kW 21.9 kW − 30.1 kW 0011 1 160 pF 10 kW 30.1 kW − 39.1 kW 0100 1 200 pF 10 kW 39.1 kW − 48.4 kW 0101 1 240 pF 10 kW 48.4 kW − 57.8 kW 0110 1 330 pF 10 kW 57.8 kW − 67.6 kW 0111 1 680 pF 10 kW 67.6 kW − 78.1 kW 1000 1 1300 pF 10 kW 78.1 kW − 89.5 kW 0000 2 20 pF 10 kW 89.5 kW − 101 kW 0001 2 43 pF 10 kW 101 kW − 113 kW 0010 2 82 pF 10 kW 113 kW − 125 kW 0011 2 160 pF 10 kW 125 kW − 138 kW 0100 2 200 pF 10 kW 138 kW − 151 kW 0101 2 240 pF 10 kW 151 kW − 163 kW 0110 2 330 pF 10 kW 163 kW − 177 kW 0111 2 680 pF 10 kW 177 kW − 193 kW 1000 2 1300 pF 10 kW For further explanation on the integrator setting and operation please refer to application note. Boost Capacitor Refresh Mode The NCP81143 include a boost capacitor refresh mode which aids the correct operation of inactive phase when exiting low power states. The mode is used where phases are shed in PS1,2 and 3 modes; in these cases it is possible that the drivers boost capacitor voltage, Vbst, may drop below 1.7 V. If this occurs the Boost capacitor charge will not be able to meet the gate source requirements for the first firing of the high side MOSFET when returning to PS0 power state. For further information on the operation of the boost capacitor refresh mode please see application note. Figure 11. Boost Cap Refresh http://onsemi.com 24 NCP81143 Remote Sense Amplifier A high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of the regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points. The remote sense amplifier takes the difference of the output voltage with the DAC voltage and adds the droop voltage to V DIFFOUT + ǒV VSP * V VSNǓ ) ǒ1.3 V * V DACǓ ) ǒV DROOP * V CSREFǓ This signal then goes through a standard error compensation network and into the inverting input of the error amplifier. The non−inverting input of the error amplifier is connected to the same 1.3 V reference used for the differential sense amplifier output bias. High Performance Voltage Error Amplifier A high performance error amplifier is provided for high bandwidth transient performance. A standard type II compensation circuit is normally used to compensate the system. Differential Current Feedback Amplifiers CSNx RCSN CSPx Each phase has a low offset differential amplifier to sense that phase current for current balance. The inputs to the CSNx and CSPx pins are high impedance inputs. It is recommended that any external filter resistor RCSN does not exceed 10 kW to avoid offset issues with leakage current. It is also recommended that the voltage sense element be no less than 0.5 mW for accurate current balance. Fine tuning of this time constant is generally not required. The individual phase current is summed into the PWM comparator feedback this way current is balanced via a current mode control approach. CCSN R CSN + SWNx VOUT DCR 1 LPHASE L PHASE C CSN * DCR 2 Figure 12. Differential Current Feedback Total Current Sense Amplifier The NCP81143 uses a patented approach to sum the phase currents into a single temperature compensated total current signal. This signal is then used to generate the output voltage droop, total current limit, and the output current monitoring functions. The total current signal is floating with respect to CSREF. The current signal is the difference between CSCOMP and CSREF. The Ref(n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground. The amplifier actively filters and gains up the voltage applied across the inductors to recover the voltage drop across the inductor series resistance (DCR). Rth is placed near an inductor to sense the temperature of the inductor. This allows the filter time constant and gain to be a function of the Rth NTC resistor and compensate for the change in the DCR with temperature. Figure 13. Total Current Sense http://onsemi.com 25 NCP81143 The DC gain equation for the current sensing: Rcs1*Rth V CSCOMP−CSREF + Rcs2 ) Rcs1)Rth Rph * ǒIout Total * DCRǓ Set the gain by adjusting the value of the Rph resistors. The DC gain should be set to the output voltage droop. If the voltage from CSCOMP to CSREF is less than 100 mV at ICCMAX then it is recommend increasing the gain of the CSCOMP amp. This is required to provide a good current signal to offset voltage ratio for the ILIMIT pin. When no droop is needed, the gain of the amplifier should be set to provide ~100 mV across the current limit programming resistor at full load. The values of Rcs1 and Rcs2 are set based on the 100k NTC and the temperature effect of the inductor and should not need to be changed. The NTC should be placed near the closest inductor. The output voltage droop should be set with the droop filter divider. The pole frequency in the CSCOMP filter should be set equal to the zero from the output inductor. This allows the circuit to recover the inductor DCR voltage drop current signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning of the time constant using commonly available values. It is best to fine tune this filter during transient testing. Fz + DCR@25° C 2 * PI * L Phase Programming the Current Limit The current limit thresholds are programmed with a resistor between the ILIMIT and CSCOMP pins. The ILIMIT pin mirrors the voltage at the CSREF pin and mirrors the sink current internally to IOUT (reduced by the IOUT Current Gain) and the current limit comparators. The 100% current limit trips if the ILIMIT sink current exceeds 10 mA for 50 ms. The 150% current limit trips with minimal delay if the ILIMIT sink current exceeds 15 mA. Set the value of the current limit resistor based on the CSCOMP−CSREF voltage as shown below. Rcs1*Rth Rcs2 ) Rcs1)Rth * ǒIout LIMIT * DCRǓ R R LIMIT + ph or R LIMIT + 10m V CSCOMP−CSREF@ILIMIT 10m Programming DAC Feed−Forward Filter The DAC feed−forward implementation is realized by having a filter on the VSN pin. Programming Rvsn sets the gain of the DAC feed−forward and Cvsn provides the time constant to cancel the time constant of the system per the following equations. Cout is the total output capacitance and Rout is the output impedance of the system. Rvsn + Cout * Rout * 453.6 Cvsn + 10 6 Rout * Cout Rvsn Figure 14. DAC Feed−Forward Programming DROOP The signals CSCOMP and CSREF are differentially summed with the output voltage feedback to add precision voltage droop to the output voltage. Droop + DCR * ǒR CSńR phǓ Figure 15. Droop http://onsemi.com 26 NCP81143 Programming IOUT The IOUT pin sources a current in proportion to the ILIMIT sink current. The voltage on the IOUT pin is monitored by the internal A/D converter and should be scaled with an external resistor to ground such that a load equal to ICCMAX generates a 2 V signal on IOUT. A pull−up resistor from 5 V VCC can be used to offset the IOUT signal positive if needed. Below equation relates to the NCP81143 only: 2.0 V * R LIMIT R IOUT + 10 * Rcs1*Rth Rcs1)Rth Rph Rcs2) * ǒIout ICC_MAX * DCRǓ Programming ICC_MAX The SVID interface provides the platform ICC_MAX value at register 21h for. A resistor to ground on the IMAX pin programs these registers at the time the part is enabled. 10 mA is sourced from these pins to generate a voltage on the program resistor. The value of the register is 1 A per LSB and is set by the equation below. The resistor value should be no less than 10k. ICC_MAX 21h + R * 10 mA * 256 A 2V Programming TSENSE A temperature sense inputs are provided. A precision current is sourced out the output of the TSENSE pin to generate a voltage on the temperature sense network. The voltage on the temperature sense input is sampled by the internal A/D converter. A 100k NTC similar to the VISHAY ERT−J1VS104JA should be used. Rcomp1 is mainly used for noise. See the specification table for the thermal sensing voltage thresholds and source current. TSENSE Rcomp1 0.0 Cfilter 10nF Rcomp2 8.2K AGND RNTC 100K AGND Figure 16. TSENSE Precision Oscillator A programmable precision oscillator is provided. The clock oscillator serves as the master clock to the ramp generator circuit. This oscillator is programmed by a resistor to ground on the ROSC pin. The oscillator frequency range is between 220 kHz/phase to 1 MHz/phase. The ROSC pin provides approximately 2 V out and the source current is mirrored into the internal ramp oscillator. The oscillator frequency is approximately proportional to the current flowing in the ROSC resistor. http://onsemi.com 27 NCP81143 Figure 17. NCP81143 Operating Frequency vs. Rosc The oscillator generates triangle ramps that are 0.5~2.5 V in amplitude depending on the VRMP pin voltage to provide input voltage feed forward compensation. Programming the Ramp Feed−Forward Circuit The ramp generator circuit provides the ramp used by the PWM comparators. The ramp generator provides voltage feed−forward control by varying the ramp magnitude with respect to the VRMP pin voltage. The VRMP pin also has a 4 V UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin is high impedance input when the controller is disabled. The PWM ramp time is changed according to the following, V RAMPpkäpkPP + 0.1 * V VRMP Vin Vramp _pp Comp −IL Duty Figure 18. Ramp Feed−Forward PWM Comparators The noninverting input of the comparator for each phase is connected to the summed output of the error amplifier (COMP) and each phase current (IL*DCR*Phase Balance Gain Factor). The inverting input is connected to the oscillator ramp voltage with a 1.3 V offset. The operating input voltage range of the comparators is from 0 V to 3.0 V and the output of the comparator generates the PWM output. During steady state operation, the duty cycle is centered on the valley of the sawtooth ramp waveform. The steady state duty cycle is still calculated by approximately Vout/Vin. During a transient event, the controller will operate in a hysteretic mode with the duty cycles pull in for all phases as the error amp signal increases with respect to all the ramps. Phase Detection Sequence During start−up, the number of operational phases and their phase relationship is determined by the internal circuitry monitoring the CSP outputs. Normally, NCP81143 operates as a 3−phase VCORE PWM controller. http://onsemi.com 28 NCP81143 Figure 19. 3 Phase Mode Pulling CSP2 high to VCC configures the NCP81143 to operate in 2 phase mode. Figure 20. 2 Phase Mode Pulling CSP3 and CSP2 high to VCC configures the NCP81143 to operate in 1 phase mode. Figure 21. 1 Phase Mode The PWM outputs are logic−level devices intended for driving fast response external gate drivers such as the NCP81151. As each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one PWM output can be on at the same time to allow overlapping phases. http://onsemi.com 29 NCP81143 PROTECTION FEATURES Under voltage Lockouts There are several under voltage monitors in the system. Hysteresis is incorporated within the comparators. NCP81143 monitors the 5 V VCC supply. The gate driver monitors both the gate driver VCC and the BST voltage. When the voltage on the gate driver is insufficient it will pull DRON low and prevents the controller from being enabled. The gate driver will hold DRON low for a minimum period of time to allow the controller to hold off it’s startup sequence. In this case the PWM is set to the MID state to begin soft start. If DRON is pulled low the controller will hold off its startup DAC Gate Driver Pulls DRON Low during driver UVLO and Calibration Figure 22. Gate Driver UVLO Restart Soft Start Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the predetermined rate in the spec table. The PWM signals will start out open with a test current to collect data on phase count and for setting internal registers. After the configuration data is collected, if the controller is enabled the PWMs will be set to 2.0 V MID state to indicate that the drivers should be in diode mode. DRON will then be asserted. As the DAC ramps the PWM outputs will begin to fire. Each phase will move out of the MID state when the first PWM pulse is produced. When the controller is disabled the PWM signal will return to the MID state. http://onsemi.com 30 NCP81143 Figure 23. Soft−Start Over Current Latch− Off Protection The NCP81143 compares a programmable current−limit set point to the voltage from the output of the current−summing amplifier. The level of current limit is set with the resistor from the ILIM pin to CSCOMP. The current through the external resistor connected between ILIM and CSCOMP is then compared to the internal current limit current ICL. If the current generated through this resistor into the ILIM pin (Ilim) exceeds the internal current−limit threshold current (ICL), an internal latch−off counter starts, and the controller shuts down if the fault is not removed after 50 ms (shut down immediately for 150% load current) after which the outputs will remain disabled until the VCC voltage or EN is toggled. The voltage swing of CSCOMP cannot go below ground. This limits the voltage drop across the DCR through the current balance circuitry. An inherent per−phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. The over−current limit is programmed by a resistor on the ILIM pin. The resistor value can be calculated by the following equations, Equation related to the NCP81143: R ILIM + I LIM * DCR * R CSńR PH I CL Where ICL = 10 mA CSSUM R CS RPH RPH R PH CSCOMP RLIM ILIM CSREF Figure 24. Ilim Resistor http://onsemi.com 31 NCP81143 Under Voltage Monitor The output voltage is monitored at the output of the differential amplifier for UVLO. If the output falls more than 300 mV below the DAC−DROOP voltage the UVLO comparator will trip sending the VR_RDY signal low. The 300 mV limit can be reprogrammed using the VR_Ready_Low Limit register. Over Voltage Protection The output voltage is also monitored at the output of the differential amplifier for OVP. During normal operation, if the output voltage exceeds the DAC voltage by 400 mV, the VR_RDY flag goes low, and the output voltage will be ramped down to 0 V. At the same time, the high side gate drivers are all turned off and the low side gate drivers are all turned on. The part will stay in this mode until the VCC voltage or EN is toggled. The part will stay in the mode until the VCC voltage or EN is toggled. Figure 25. OVP Behavior at Startup Figure 26. OVP During Normal Operation Mode http://onsemi.com 32 NCP81143 OVP Threshold DAC VSP_VSN OVP Triggered Latch Off PWM Figure 27. OVP During Normal Operation Mode During start up, the OVP threshold is set to 2.9 V. This allows the controller to start up without false triggering the OVP ORDERING INFORMATION Device NCP81143MNTXG Package Shipping† QFN36 (Pb−Free) 5000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 33 NCP81143 PACKAGE DIMENSIONS QFN36 5x5, 0.4P CASE 485CC ISSUE O PIN ONE LOCATION ÉÉÉ ÉÉÉ ÉÉÉ L1 DETAIL A ALTERNATE CONSTRUCTIONS E EXPOSED Cu TOP VIEW DETAIL B 0.10 C DIM A A1 A3 b D D2 E E2 e K L L1 ÉÉÉ ÉÉÉ 0.15 C 0.15 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L A B D MOLD CMPD DETAIL B (A3) ALTERNATE CONSTRUCTION A 0.08 C A1 SIDE VIEW NOTE 4 C 0.10 M SEATING PLANE RECOMMENDED SOLDERING FOOTPRINT* C A B 5.30 D2 DETAIL A K 10 MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.15 0.25 5.00 BSC 3.40 3.60 5.00 BSC 3.40 3.60 0.40 BSC 0.35 REF 0.30 0.50 −−− 0.15 36X 0.63 3.64 0.10 19 M C A B 1 E2 36X L 5.30 3.64 1 36 e BOTTOM VIEW 36X b 0.10 M C A B 0.05 M C PKG OUTLINE NOTE 3 0.40 PITCH 36X 0.25 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 34 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP81143/D