NCP81231
High Resolution Buck
Controller with Full USB PD
Features and 100% Duty
Operation
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The NCP81231 is a synchronous buck that is optimized for
converting battery voltage or adaptor voltage into power supply rails
required in notebook, tablet, and desktop systems, as well as many
other consumer devices using USB PD standard and C−Type cables.
The NCP81231 is fully compliant to the USB Power Delivery
Specification when used in conjunction with a USB PD or C−Type
Interface Controller. NCP81231 is designed for applications requiring
dynamically controlled slew rate limited output voltage.
1
32
QFN32 5x5, 0.5P
CASE 485CE
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide Input Voltage Range: from 4.5 V to 28 V
Dynamically Programmed Frequency from 150 kHz to 1.2 MHz
I2C Interface
Real Time Power Good Indication
Controlled Slew Rate Voltage Transitioning
Feedback Pin with Internally Programmed Reference
High Resolution DAC Voltage
Two Independent Current Sensing Inputs
Support Inductor DCR Sensing
Over Temperature Protection
Adaptive Non−Overlap Gate Drivers
Filter Capacitor Switch Control
100% Duty Cycle Operation
Latched Over−Voltage and Over−Current Protection
Dead Battery Power Support
5 x 5 mm QFN32 Package
Notebooks, Tablets, Desktops
Gaming
Monitors, TVs, and Set Top Boxes
Consumer Electronics
Car Chargers
Docking Stations
Power Banks
© Semiconductor Components Industries, LLC, 2016
May, 2018 − Rev. 3
1
NCP81231
AWLYYWWG
G
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
NCP81231MNTXG
Package
QFN32
(Pb−Free)
Shipping†
2500 / Tape
& Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Typical Application
•
•
•
•
•
•
•
MARKING DIAGRAM
1
Publication Order Number:
NCP81231/D
NCP81231
V1
DBIN
DBOUT
CSP1
VDRV
CSN1
CVDRV
V2
V1
Q6
FB
RDRV
VCC
RPU
CSN2
CO1
CO2
CVCC
CSP2
Current Sense 1
CS 1
Q5
CFET1
RCS 1
Current Sense 2
CS 2
BST 1
RCS 2
Q1
CLIND
Curret Limit Indicator
Interrupt
INT
Enable
EN
SDA
I2C
CB1
HSG1
VSW 1
L1
SCL
Q2
LSG1
CP
COMP
PGND1
AGND
PDRV
RC
CC
Figure 1. Typical Application Circuit (DCR)
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2
RPD
VBUS
NCP81231
V1
V2
V1
DBIN
DBOUT
CSP1
VDRV
CSN1
CVDRV
Q6
FB
RDRV
RPU
CSN2
VCC
CO1
CO2
CVCC
CSP2
Current Sense 1
CS 1
Q5
CFET1
RCS 1
Current Sense 2
CS 2
BST 1
RCS 2
Q1
CLIND
Curret Limit Indicator
Interrupt
INT
Enable
EN
CB1
HSG1
VSW 1
SDA
I2C
L1
SCL
Q2
LSG1
PGND1
AGND
PDRV
RC
VSW1
VCC
VDRV
DBIN
DBOUT
NC
NC
Figure 2. Typical Application Circuit (Rsense)
BST1
32
31
30
29
28
27
26
25
23
NC
PGND1
3
22
PGND2
CSN1
4
21
CSP2
CSP1
5
20
CSN2
V1
6
19
FB
CS1
7
18
CS2
CLIND
8
17
PDRV
9
10
11
12
13
14
15
16
EN
2
COMP
LSG1
AGND
NC
AGND
24
CFET
1
INT
HSG1
SCL
CC
SDA
CP
COMP
Figure 3. Pinout
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3
RPD
VBUS
NCP81231
V1
DBOUT
V1
V1
4.0V
VCC
VDRV
Vcc_rdy
V1
−
Startup
INPUT
UVLO
VDRV
4.0V
IUVLOB
CS2
CLIMP1
−
CLIMP2
−
CS 2
Protection
Driver
Control
Logic
CS 2_INT
CLINDP1
PWM
CLIND
PG
CLINDP2
+
RS1
HSG1
CS 1_INT
−
+
CSN1
BST1
VDRV_rdy
CS 1
NC
CS 1_INT
BG
+
CS1
CS 1
TS
_
VCC
CSP1
Thermal
Shutdown
CONFIG
+
CSP1
BG
+
Current Limiting
Circuit
For Dead Battery
DBIN
OV
VSW1
VDRV
RS2
LSG1
CO
TS
EN
PG_Low
EN _MASK
ENPOL
0.8V
+
EN
LOGIC
VFB
EN
ADC
Value
Register
CFET
PDRV
CONFIG
I2C
Interface
Analog
Mux
CSP1
VFB
CS 1_INT
CS 2_INT
PG_High
OV_MSK
+
−
PG_MSK
+
OV
PG/
OV/
LOGIC
PG
VFB
CSP2
+
Limit
Registers
OV_REF
−
CS 2
CSN2
CS 2_INT
CSN2
Digital
Configuration
INT
INT
Interface
COMP
Oscillator
CS 2_INT
Reference
Status
Registers
PDRV
Buck Control
Logic
+
CC
VFB
CP
VDRV
CFET
VDRV
PDRV
CFET
BG
Error OTA
PG
TS
_
−
Rbld
−
+
EN
SCL
CO 2
Q2
CLIND
V2
PGND1
CLIND
SDA
Q1
PWM
_
FB
RC
VFB
R1
AGND
FLAG
Figure 4. Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin
Pin Name
Description
1
HSG1
S1 gate drive. Drives the S1 N−channel MOSFET with a voltage equal to VDRV superimposed on the switch
node voltage VSW1.
2
LSG1
Drives the gate of the S2 N−channel MOSFET between ground and VDRV.
3, 22
PGND
Power ground for the low side MOSFET drivers. Connect these pins closely to the source of the bottom
N−channel MOSFETs.
4
CSN1
Negative terminal of the current sense amplifier.
5
CSP1
Positive terminal of the current sense amplifier.
6
V1
7
CS1
8
CLIND
9
SDA
I2C interface data line.
10
SCL
I2C interface clock line.
11
INT
Interrupt is an open drain output that indicates the state of the output power, the internal thermal trip, and
other I2C programmable functions.
12
CFET
Controlled drive of an external MOSFET that connects a bulk output capacitor to the output of the power
converter. Necessary to adhere to low capacitance limits of the standard USB Specifications for power prior
to USB PD negotiation.
13, 14
AGND
The ground pin for the analog circuitry.
15
COMP
Output of the transconductance amplifier used for stability in closed loop operation.
Input voltage of the converter
Current sense amplifier output. CS1 will source a current that is proportional to the voltage across
CSP1/CSN1. Connect CS1 to a high impedance monitoring input.
Open drain output to indicate that the CS1 or CS2 voltage has exceeded the I2C programmed limit.
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4
NCP81231
Table 1. PIN FUNCTION DESCRIPTION (continued)
Pin
Pin Name
Description
16
EN
Precision enable starts the part and places it into default configuration when toggled.
17
PDRV
The open drain output used to control a PMOSFET or connect to an external resistor.
18
CS2
19
FB
20
CSN2
Negative terminal of the current sense amplifier.
21
CSP2
Positive terminal of the current sense amplifier.
23−25
NC
No connection.
26
NC
No connection.
27
DBOUT
28
DBIN
The dead battery input to the converter where 5 V is applied. A 1 mF capacitor should be placed close to the
part to decouple this line.
29
VDRV
Internal voltage supply to the driver circuits. A 1 mF capacitor should be placed close to the part to decouple
this line.
30
VCC
31
VSW1
Switch Node. VSW1 pin swings from a diode voltage drop below ground up to V1.
32
BST1
Driver Supply. The BST1 pin swings from a diode voltage below VDRV up to a diode voltage below V1 +
VDRV. Place a 0.1 mF capacitor from this pin to VSW1.
33
THPAD
Current sense amplifier output. CS2 will source a current that is proportional to the voltage across
CSP1/CSN1. Connect CS2 to a high impedance monitoring input.
Feedback voltage of the output, negative terminal of the gm amplifier.
The output of the dead battery circuit which can also be used for the VCONN voltage supply.
The VCC pin supplies power to the internal circuitry. The VCC is the output of a linear regulator which is
powered from V1. Can be used to supply up to a 100 mA load. Pin should be decoupled with a 1 mF capacitor
for stable operation.
Center pad, recommended to connect to AGND.
Table 2. MAXIMUM RATINGS
(Over operating free−air temperature range unless otherwise noted)
Rating
Symbol
Min
Max
Unit
Input of the Dead Battery Circuit
DBIN
−0.3
5.5
V
Output of the Dead Battery Circuit
DBOUT
−0.3
5.5
V
Driver Input Voltage
VDRV
−0.3
5.5
V
Internal Regulator Output
VCC
−0.3
5.5
V
Output of Current Sense Amplifiers
CS1, CS2
−0.3
3.0
V
Current Limit Indicator
CLIND
−0.3
VCC + 0.3
V
Interrupt Indicator
INT
−0.3
VCC + 0.3
V
Enable Input
EN
−0.3
5.5
V
I2C
SDA, SCL
−0.3
VCC + 0.3
V
Compensation Output
COMP
−0.3
VCC + 0.3
V
V1 Power Stage Input Voltage
V1
−0.3
32 V, 40 V (20 ns)
V
Positive Current Sense
CSP1
−0.3
32 V, 40 V (20 ns)
V
Negative Current Sense
CSN1
−0.3
32 V, 40 V (20 ns)
V
Positive Current Sense
CSP2
−0.3
32 V, 40 V (20 ns)
V
Negative Current Sense
CSN2
−0.3
32 V, 40 V (20 ns)
V
Feedback Voltage
FB
−0.3
5.5
V
CFET Driver
CFET
−0.3
VCC + 0.3
V
Driver Positive Rail
BST1
−0.3 V wrt/PGND
−0.3 V wrt/VSW
37 V, 40 V (20 ns) wrt/PGND
5.5 V wrt/VSW
V
Communication Lines
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5
NCP81231
Table 2. MAXIMUM RATINGS (continued)
(Over operating free−air temperature range unless otherwise noted)
Rating
Symbol
Min
Max
Unit
High Side Driver
HSG1
−0.3 V wrt/PGND
−0.3 V wrt/VSW
37 V, 40 V (20 ns) wrt/GND
5.5 V wrt/VSW
V
Switching Node and Return Path of Driver
VSW1
−5.0 V
32 V, 40 V (20 ns)
V
Low Side Driver
LSG1
−0.3 V
5.5
V
PMOSFET Driver
PDRV
−0.3
40
V
Voltage Differential
AGND to
PGND
−0.3
0.3
V
CSP1−CSN1, CSP2−CSN2 Differential Voltage
CS1DIF,
CS2DIF
−0.5
0.5
V
PDRV Maximum Current
PDRVI
0
10
mA
PDRV Maximum Pulse Current
(100 ms on time, with > 1 s interval)
PDRVIPUL
0
200
mA
Maximum VCC Current
VCCI
0
80
mA
Operating Junction Temperature Range (Note 1)
TJ
−40
150
°C
Operating Ambient Temperature Range
TA
−40
100
°C
Storage Temperature Range
TSTG
−55
150
°C
Thermal Characteristics (Note 2)
QFN 32 5mm x 5mm
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance Junction−to−Air with Solder
PD
RQJA
Lead Temperature Soldering (10 sec):
Reflow (SMD styles only) Pb−Free (Note 3)
RF
4.1
30
W
°C/W
260 Peak
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The maximum package power dissipation limit must not be exceeded.
2. The value of QJA is measured with the device mounted on a 3in x 3in, 4 layer, 0.062 inch FR−4 board with 1.5 oz. copper on the top and
bottom layers and 0.5 ounce copper on the inner layers, in a still air environment with TA = 25°C.
3. 60−180 seconds minimum above 237°C.
Table 3. ELECTRICAL CHARACTERISTICS
(V1 = 12 V, Vout = 5.0 V , TA = +25°C for typical value; −40°C < TA < 100°C for min/max values unless noted otherwise)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
28
V
5.5
V
POWER SUPPLY
V1 Operating Input Voltage
V1
4.5
VDRV Operating Input Voltage
VDRV
4.5
5
VCC UVLO Rising Threshold
VCCSTART
UVLO Hysteresis for VCC
VCCVHYS
VDRV UVLO Rising Threshold
VDRVSTART
UVLO Hysteresis for VDRV
VDRVHYS
Falling Hysteresis
VCC Output Voltage
VCC
With no external load
VCC Drop Out Voltage
VCCDROOP
30 mA load
VCC Output Current Limit
IOUTVCC
VCC Loaded to 4.3 V
V1 Shutdown Supply Current
IVCC_SD
EN = 0 V, 4.2 V ≤ V1 ≤ 28 V
6.7
VDRIVE Switching Current Buck
IV1_SW
EN = 5 V, Cgate = 2.2 nF,
VSW = 0 V, FSW = 600 kHz
15
Falling Hysteresis
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6
4.96
80
4.26
V
320
mV
4.27
V
340
mV
5
V
160
mV
97
mA
7.7
mA
mA
NCP81231
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(V1 = 12 V, Vout = 5.0 V , TA = +25°C for typical value; −40°C < TA < 100°C for min/max values unless noted otherwise)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
0.5
1.2
2.0
0.505
1.212
2.02
V
VOLTAGE OUTPUT
Voltage Output Accuracy
VFB
DAC_TARGET = 00110010
DAC_TARGET = 01111000
DAC_TARGET = 11001000
0.495
1.188
1.98
Voltage Accuracy Over Temperature
VFB_T
−40°C < TA < 100°C
VFB > 0.5 V
VFB < 0.5 V
−1.0
−5
1.0
5
%
mV
TA = 25°C
VFB > 0.5 V
−0.45
0.45
%
VFB_R
TRANSCONDUCTANCE AMPLIFIER
Gain Bandwidth Product
GBW
3 db (Note 4)
5.2
MHz
Transconductance
GM1
Default
500
mS
Max Output Source Current limit
GMSOC
60
83
mA
Max Output Sink Current limit
GMSIC
60
84
mA
Voltage Ramp
Vramp
0.7
V
INTERNAL BST DIODE
Forward Voltage Drop
VFBOT
IF = 10 mA, TA = 25°C
Reverse−Bias Leakage Current
DIL
BST−VSW UVLO
BST−VSW Hysteresis
0.35
0.46
0.55
V
BST−VSW = 5 V
VSW = 28 V, TA = 25°C
0.05
1
mA
BST1_UVLO
Rising (Note 4)
3.5
V
BST_HYS
(Note 4)
300
mV
FSW_0
FSW = 000, default
528
600
672
kHz
FSW_1
FSW = 001
132
150
168
kHz
FSW_7
FSW = 110
1056
1200
1344
kHz
12
%
OSCILLATOR
Oscillator Frequency
Oscillator Frequency Accuracy
FSWE
−12
Minimum On Time
MOT
Measured at 10% to 90% of VCC,
−40°C < TA < 100°C
50
ns
Minimum Off Time
MOFT
Measured at 90% to 10% of VCC,
−40°C < TA < 100°C
90
ns
Interrupt Low Voltage
VINTI
IINT(sink) = 2 mA
Interrupt High Leakage Current
INII
3.3 V
Interrupt Startup Delay
INTPG
Soft Start end to PG positive edge
2.1
ms
Interrupt Propagation Delay
PGI
Delay for power good in
3.3
ms
PGO
Delay for power good out
100
ns
PGTH
Power Good in from high
105
%
PGTH
Power Good in from low
95
%
PGTHYS
PG falling hysteresis
2.5
%
140
%
INT THRESHOLDS
Power Good Threshold
FB Overvoltage Threshold
FB_OV
Overvoltage Propagation Delay
VFB_OVDL
3
1
Cycle
4. Ensured by design. Not production tested.
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7
0.2
V
100
nA
NCP81231
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(V1 = 12 V, Vout = 5.0 V , TA = +25°C for typical value; −40°C < TA < 100°C for min/max values unless noted otherwise)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
EXTERNAL CURRENT SENSE (CS1,CS2)
Positive Current Measurement High
CS10
CSP1−CSN1 or CSP2−CSN2 =
100 mV
500
mA
Transconductance Gain Factor
CSGT
Current Sense Transconductance
Vsense = 1 mV to 100 mV
5
mS
Transconductance Deviation
CSGE
Current Sense Common Mode
Range
CSCMMR
−3dB Small Signal Bandwidth
CSBW
Input Sense Voltage Full Scale
ISVFS
CS Output Voltage Range
CSOR
VSENSE = 100 mV Rset = 6k
Current Limit Indicator Output Low
CLINDL
Input current = 500 mA
10
Current Limit Indicator Output High
Leakage Current
ICLINDH
Pull up to 5 V
500
Internal Current Sense Gain for PWM
ICG
CSPx−CSNx = 100 mV
9.2
9.9
10.5
V/V
Positive Peak Current Limit Trip
PPCLT
INT_CL = 00
34
39
44
mV
HSG Pullup Resistance
HSG_PU
BST−VSW = 4.5 V
2.9
W
HSG Pulldown Resistance
HSG_PD
BST−VSW = 4.5 V
1.1
W
LSG Pullup Resistance
LSG_PU
LSG −PGND = 2.5 V
3.4
W
LSG Pulldown Resistance
LSG_PD
LSG −PGND = 2.5 V
1.1
W
HSG Falling to LSG Rising Delay
HSLSD
15
ns
LSG Falling to HSG Rising Delay
LSHSD
15
ns
VCC
V
−20
20
%
3
28
V
VSENSE (AC) = 10 mVPP,
RGAIN = 10 kW (Note 4)
30
0
MHz
100
mV
3
V
100
mV
EXTERNAL CURRENT LIMIT (CLIND)
mA
INTERNAL CURRENT SENSE
SWITCHING MOSFET DRIVERS
CFET
CFET Drive Voltage
CFETDV
Source/Sink Current
CFETSS
CFET clamped to 2 V
2
mA
Pull Down Delay
CFETD
Measured at 10% to 90% of VCC,
−40°C < TA < 100°C
10
ms
CFET Pull Down Resistance
CFETR
Measured with 1 mA Pull up Current, after 10 ms rising edge delay
1.3
kW
Charge Slew Rate
SLEWP
Slew = 00, FB = 0.1 VOUT
Slew = 11, FB = 0.1 VOUT
0.6
4.8
mV/ms
Discharge Slew Rate
SLEWN
Slew = 00, FB = 0.1 VOUT
Slew = 11, FB = 0.1 VOUT
−0.6
−4.8
mV/ms
SLEW RATE/SOFT START
DEAD BATTERY/VCONN
Dead Battery Input Voltage Range
VDB
Dead Battery Output Voltage
VIO
Dead Battery Current Limit
DB_LIM
4.5
5
5.25
V
VDB = 5 V, −40°C < TA < 100°C,
Output Current 32 mA
4
4.7
5
V
VDB = 5 V, DBOUT > 2 V
29
57
4. Ensured by design. Not production tested.
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8
mA
NCP81231
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(V1 = 12 V, Vout = 5.0 V , TA = +25°C for typical value; −40°C < TA < 100°C for min/max values unless noted otherwise)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
800
820
mV
ENABLE
EN High Threshold Voltage
ENHT
EN Low Threshold Voltage
ENLT
EN Pull Up Current
IEN_UP
EN Pull Down Current
IEN_DN
I2C
EN_MASK = ENPU = ENPOL = 0
640
667
mV
EN = 0 V
5
mA
EN = VCC
5
mA
INTERFACE
Voltage Threshold
I2CVTH
Propagation Delay
I2CPD
(Note 4)
0.95
Communication Speed
I2CSP
(Note 4)
1
1.05
25
V
ns
1
MHz
2.55
V
INTERNAL ADC
Range
ADCRN
0
LSB Value
ADCLSB
(Note 4)
Error
ADCFE
(Note 4)
Thermal Shutdown Threshold
TSD
(Note 4)
151
°C
Thermal Shutdown Hysteresis
TSDHYS
(Note 4)
28
°C
20
mV
1
LSB
THERMAL SHUTDOWN
PDRV
0
PDRV Operating Range
28
V
PDRV Leakage Current
PDRV_IDS
FET OFF, VPDRV = 28 V
480
nA
PDRV Saturation Voltage
PDRV_VDS
ISNK = 10 mA
0.20
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Ensured by design. Not production tested.
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9
NCP81231
APPLICATION INFORMATION
Feedback and Output Voltage Profile
voltage to 5 V in default. The reference voltage can be
adjusted with 10 mV(default) or 5 mV steps from 0.3 V to
2.55 V through the voltage profile register (01H), which
makes the continuous output voltage profile possible
through an external resistor divider. For example, if the
external resistor divider has a 10:1 ratio, the output voltage
profile will be able to vary from 3 V to 25.5 V with 100 mV
steps but not above V1 voltage.
The feedback of the converter output voltage is connected
to the FB pin of the device through a resistor divider.
Internally FB is connected to the inverting input of the
internal
transconductance
error
amplifier.
The
non−inverting input of the gm amplifier is connected to the
internal reference. The internal reference voltage is by
default 0.5 V. Therefore, for example, a 10:1 resistor divider
from the converter output to the FB will set the output
Table 4. VOLTAGE PROFILE SETTINGS
dac_taget
dac_target_LSB
Voltage Profile
Hex Value
Reference
Voltage (mV)
0
0
00H
Reserved
0
0
1
00H
Reserved
0
0
1
0
01H
Reserved
…
…
…
…
…
…
…
1
1
1
0
1
1
1DH
Reserved
0
1
1
1
1
0
0
1EH
300
0
1
1
1
1
0
1
1EH
305
…
…
…
…
…
…
…
…
…
…
0
0
1
1
0
0
1
0
0
32H
500 (Default)
…
…
…
…
…
…
…
…
…
…
…
1
1
0
0
1
0
0
0
0
C8H
2000
…
…
…
…
…
…
…
…
…
…
…
1
1
1
1
1
1
1
1
0
FFH
2550
1
1
1
1
1
1
1
1
1
FFH
2555
bit_8
bit_7
bit_6
bit_5
bit_4
bit_3
bit_2
bit_1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
…
…
…
…
0
0
0
0
0
0
0
…
Transconductance Voltage Error Amplifier
1000 mS allowing the DC gain of the system to be increased
more than a decade triggered by the adding and removal of
the bulk capacitance or in response to another user input.
The default transconductance is 500 mS.
To maintain loop stability under a large change in
capacitance, the NCP81231 can change the gm of the
internal transconductance error amplifier from 87 mS to
Table 5. AVAILABLE TRANSCONDUCTANCE SETTING
AMP_2
AMP_1
AMP_0
Amplifier GM Value (mS)
0
0
0
87
0
0
1
100
0
1
0
117
0
1
1
333
1
0
0
400
1
0
1
500
1
1
0
667
1
1
1
1000
Programmable Slew Rate
The slew rate of the NCP81231 is controlled via the I2C
registers with the default slew rate set to 0.6 mV/ms
(FB = 0.1 VOUT, assume the resistor divider ratio is 10:1)
which is the slowest allowable rate change. The slew rate is
used when the output voltage starts from 0 V to a user
selected profile level, changing from one profile to another,
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10
NCP81231
depends on the bandwidth of the converter where a low
bandwidth will result in a slower slew rate than the selected
value. The available slew rates are shown in Table 6. The
selected slew rate is maintained unless the current limit is
tripped, in which case the increased voltage will be governed
by the positive current limit until the output voltage falls or
the fault is cleared.
or when the output voltage is dynamically changed. The
output voltage is divided by a factor of the external resistor
divider and connected to FB pin. The 9 Bit DAC is used to
increase the reference voltage in 10 or 5 mV increments. The
slew rate is decreased by using a slower clock that results in
a longer time between voltage steps, and conversely
increases by using a faster clock. The step monotonicity
2.56 V
DAC_TARGET
9 bit DAC
DAC_TARGET_LSB
VREF
COMP
+
VOUT
−
RC
CI
CC
FB = 0.1*VOUT
Figure 5. Slew Rate Limiting Block Diagram and Waveforms
starts in synchronous mode, the prebias voltage will be
discharged. The NCP81231 controller ensures that if a
prebias is detected, the soft start is completed in a
non−synchronous mode to prevent the output from
discharging.
It takes at least 3.3 ms for the digital core to reset all the
registers, so it is recommended not to restart a soft start until
at least 3.3 ms after the output voltage ramp down to steady
state.
Table 6. SLEW RATE SELECTION
Slew Bits
Soft Start or Voltage Transition
(FB = 0.1*VOUT)
Slew_0
0.6 mV/ms
Slew_1
1.2 mV/ms
Slew_2
2.4 mV/ms
Slew_3
4.8 mV/ms
The discharge slew rate is accomplished in much the same
way as the charging except the reference voltage is
decreased rather than increased.
Frequency Programming
The switching frequency of the NCP81231 can be
programmed from 150 kHz to 1.2 MHz via the I2C interface.
The default switching frequency is set to 600 kHz. Once the
part is enabled, the frequency is set and cannot be changed
while the part remains enabled. The part must be disabled
with no switching prior to writing the frequency bits into the
appropriate I2C register.
Soft Start
During a 0 V soft start, standard converters can start in
synchronous mode and have a monotonic rising of output
voltage. If a prebias exists on the output and the converter
Table 7. FREQUENCY PROGRAMMING TABLE
Name
Bit
Definition
Freq1
03H [2:0]
Frequency Setting
Description
3 Bits that Control the Switching Frequency from 150 kHz to 1 MHz.
000: 600 kHz
001: 150 kHz
010: 300 kHz
011: 450 kHz
100: 750 kHz
101: 900 kHz
110: 1.2 MHz
111: Reserved
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11
NCP81231
100% Duty Cycle Operation
Current Sense Amplifiers
NCP81231 can operate in a 100% duty cycle mode when
the high side switch works as a bypass switch. A detection
circuit will constantly monitor the high side gate voltage and
turn on low side switch to refresh the boost capacitor when
the voltage across the boost capacitor is below the boost
UVLO voltage. If the system stays in the 100% duty cycle
operation, the output will always follow the input regardless
the COMP voltage and COMP is likely to creep up. If a fast
COMP recovery is required, the following clamping
circuitry can be considered with a larger than 1.5 V clamping
voltage set as the target.
Internal differential amplifiers measure the potential
between the terminal CSP1/CSN1 or CSP2/CSN2. The
potential difference between CSPx and CSNx is level
shifted from the high voltage domain to the low voltage
VCC domain.
Both current sense signals can be monitored externally by
CS1 and CS2 pins. They are fixed gm amplifier outputs,
allowing users to set output gain by shunting resistors. CS1
correlates to the CSP1/CSN1 reading, CS2 correlates to the
CSP2/CSN2 reading. When not used, CSP1/CSN1 pin can
be shorted therefore CS1 reading is omitted.
NCP81231 also uses CSP2/CSN2 current sense signal for
current mode modulation and cycle by cycle positive and
negative peak current limiting. The inputs of CSP2/CSN2
can be a current sense resistor or configured for inductor
DCR sensing shown as Figure 8. A resistor Rs1 connects
from switch node to CSP2 and Rs2 connects from the output
voltage to CSN2 respectively. Two capacitors, Cs1 and Cs2,
are common mode filtering capacitors from CSP2 and CSN2
to the ground. Choose Rs1=Rs2=Rs, Cs1=Cs2=Cs; In order
to replicate inductor current sensing information, Rs*Cs
needs to be equal or slightly higher than the ratio of output
inductance over its DC resistance or L/DCR. Additional
resistor network may be added to expand the actual current
limit tripping range.
VCC
R2
NCP81231
D1
COMP
1.5 V
R1
Figure 6. External Comp Clamping Circuit
Internal Path
10x(CSP2-CSN2)
+
CLIP
10X
+
+
−
−
−
10x(CSP2-CSN2)
CLIN
CSP1/CSP2
+
−
−
RAMP 1
RAMP 2
CS1 or CS2
+
−
Negative Current
+
Limit
−
VCM
+
Positive Current
Limit
ADC
+
−
CS2 MUX
−
CS1 MUX
CSN1/CSN2
2
+
VCC
2
CLIND
CS2
CS1
CCS
RCS
CCS
Figure 7. Block Diagram for Current Sense Channel
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12
RCS
NCP81231
S1
L
SWN
DCR
VOUT
RS2
RS1
CS1
CS2
S2
CSP2
CSN2
Figure 8. Inductor DCR Sensing Using CSP2/CSN2
Positive Current Limit Internal Path
this way, current is limited on a pulse by pulse basis. Pulse
by pulse current limiting is advantageous for limiting energy
into a load in over current situations but are not up to the task
of limiting energy into a low impedance short. To address the
low impedance short, the NCP81231 will go to latch up
mode if pulse by pulse current limiting continues for more
than 4 cycles. Toggling the enable pin or resetting the input
voltage (V1) will clear the latched OCP fault.
The NCP81231 has a pulse by pulse current limiting
function activated when a positive current limit triggers.
When a positive current limit is triggered, the current pulse
is truncated. For NCP81231, the CSP2/CSN2 pins will be
the positive current limit sense channel.
The S1 switch is turned off to limit the energy during an
over current event. The current limit is reset every switching
cycle and waits for the next positive current limit trigger. In
Table 8. INTERNAL PEAK CURRENT LIMIT
CLIP_1
CLIP_0
CLIM delta Value (mV)
CSP2−CSN2 (mV)
Trip Current Inductor DCR = 2 mW (A)
0
0
380
38
19
0
1
230
23
11.5
1
0
110
11
5.5
1
1
700
70
35
External Path (CS1, CS2, CLIND)
The speed and accuracy of the dual amplifier stage allows
the reconstruction of the input and output current signal,
creating the ability to limit the peak current. If the user would
like to limit the mean DC current of the switch, a capacitor
can be placed in parallel with the RCS resistors.
The external CS voltages are connected to 2 high speed
low offset comparators. The comparators output can be used
to suspend operation until reset or restart of the part
depending on I2C configuration. When one of the
comparators trips if not masked, the external CLIND flag is
triggered to indicate that the internal comparator has
exceeded the preset limit. The default comparator setting is
250 mV which is a limit of 500 mA with a current sense
resistor of 5 mW and an RCS resistor of 20 kW. The block
diagram in Figure 9 shows the programmable comparators
and the settings are shown in Table 9.
CLIND may misbehave when EN toggles. It is because
the internal analog circuit is not fully functional when EN is
just asserted. One solution is to force the CLIND low during
EN is low and release CLIND after certain time after EN
goes high.
The voltage drop across CSP1/CSN1 or CSP2/CSN2 as
a result of the load can be observed on the CS1 and CS2 pins.
The voltage drop is converted into a current by
a transconductance amplifier with a typical GM of 5 mS.
The final gain of the output is determined by the end users
selection of the RCS resistors or the inductor DCR resistor.
The output voltage of the CS pin can be calculated from
Equation 1. The user must be careful to keep the dynamic
range below 3.0 V when considering the maximum short
circuit current.
V CS + (I LOAD_MAX * R SENSE * Trans) * R CS ³
³ 2.967 V + (8.5 A * 5 mW * 5 mS) * 13.96 kW
R CS +
V CS
³
I LOAD * R SENSE * Trans
³ 13.96 kW +
2.967 V
8.5 A * 5 mW * 5 mS
(eq. 1)
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13
NCP81231
CS1
CS1
RCS2
CS2
CLIM MUX
CS2_LIM
CS2
+
CS2
Resistor
Network
CLIND
MUX
−
RCS2
Buffer
Buffer
−
MUX
BG
+
CS1
CS1_LIM
Figure 9. Block Diagram for CLIM Comparator
Table 9. REGISTER SETTING FOR THE CLIM COMPARATORS
CLIMx_1
CLIMx_0
CSx_LIM (V)
Current at RSENSE = 5 mW
RSET = 20 kW (A)
Current at RSENSE = 5 mW
RSET = 10 kW (A)
0
0
0.25
.5
1
0
1
0.75
1.5
3
1
0
1.5
3
6
1
1
2.5
5
10
Overvoltage Protection (OVP)
When the divided output voltage is 140% (typical) above
the internal reference voltage, a latched OV fault will be
triggered. At 0 V reference voltage, it’s easy to trigger OVP
falsely. So one should avoid using output voltage profile
under 0.3 V for safety in normal operation. When 0 V output
voltage is needed, one can disable NCP81231 by pulling EN
pin down, instead of setting output voltage profile to 0 via
I2C. Toggling the enable pin will not clear the latched OVP
fault. Only resetting the input voltage (V1) can clear it.
Power Not Good
107.5%
105%
Power Not Good
PG
NCP81231 provides two window comparators to monitor
the internal feedback voltage. The target voltage window is
±5% of the reference voltage (typical). Once the feedback
voltage is within the power good window, a power good
indication is asserted once a 3.3 ms timer has expired. If the
feedback voltage falls outside a ±7.5% window for greater than
1 switching cycle, the power good register is reset. Power
good is indicated on the INT pin if the related I2C register is
set to display the PG state. During startup, INT is set until the
feedback voltage is within the specified range for 3.3 ms.
Figure 11. PG Diagram
Table 10. POWER GOOD MASKING
PG_MSK
Description
0
PG Action and Indication Unmasked
1
PG Action and Indication Masked
Thermal Shutdown
PG_MSK
−
The NCP81231 protects itself from overheating with an
internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown threshold
(typically 150°C), all MOSFETs will be driven to the off
state, and the part will wait until the temperature decreases
to an acceptable level. The fault will be reported to the fault
register and the INT flag will be set unless it is masked.
When the junction temperature drops below 125°C
(typical), the part will discharge the output voltage to 0 V.
PG
+
VFB
−
PG_High
Power Good
95%
92.5%
Power Good Monitor (PG)
PG_Low
VFB
100%Vref
+
Figure 10. PG Block Diagram
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14
NCP81231
CFET Turn On
incorporates a right drive circuit that regulates current into
the gate of the MOSFET such that the MOSFET turns on
slowly reducing the drain to source resistance gradually.
Once the transition from high to low has occurred in
a controlled way, a strong pulldown driver is used to ensure
normal operation does not turn on the power N−MOSFET
engaging the bulk capacitance. The CFET must be activated
through the I2C interface where it can be engaged and
disengaged. The default state is to have the CFET
disengaged.
The CFET is used to engage the output bulk capacitance
after successful negotiations between a consumer and
a provider. The USB Power Delivery Specification requires
that no more than 30 mF of capacitance be present on the
VBUS rail when sinking power. Once the consumer and
provider have completed a power role swap, a larger
capacitance can be added to the output rail to accommodate
a higher power level. The bulk capacitance must be added in
such a way as to minimize current draw and reduce the
voltage perturbation of the bus voltage. The NCP81231
VBUS
HSG2
CBULK
LSG2
30μF
10 μH
QCFET
VCC
CFET_O
2μA
CFET
10 ms Rising
Edge Delay
2μA
Figure 12. CFET Drive
Table 11. CFET ACTIVATION TABLE
CFET_0
Description
0
CFET Pin Pulldown
1
CFET Pin Pull Up
VBUS
PFET Drive
The PMOS drive is an open drain output used to control
the turn on and turn off of PMOSFET switches at a floating
potential or to create an external discharging path.
The RDSon of the pulldown NMOSFET is typically 20 W
allowing the user to quickly turn on for a fast output
discharge or to control the external pass FETs.
PDRV
PFET_DRV
NFET
Table 12. PFET ACTIVATION TABLE
PFET_DRV
Description
0
NFET OFF (Default)
1
NFET ON
Figure 13. PFET Drive
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15
NCP81231
Analog to Digital Converter
ADC, thus the range of the measurement is 0 V−2.55 V, same
as FB. The resolution of the V1 and FB voltage is 20 mV at
the analog mux, but since the voltage is divided by 10 output
voltage resolution will be 200 mV. When CS1 and CS2 are
sampled, the range is 0 V−2.55 V. The resolution will be
20 mV in the CS monitoring case. The actual current can be
calculated by dividing the CS1 or CS2 values with the factor
of Rsense*5mS*RCSx, the total gain from the current input
to the external current monitoring outputs.
The analog to digital converter is a 7−bit A/D which can
be used as an event recorder, an input voltage sampler,
output voltage sampler, input current sampler, or output
current sampler. The converter digitizes real time data
during the sample period. The internal precision reference is
used to provide the full range voltage; in the case of input
voltage V1 or the feedback voltage FB (with 10:1 external
resistor divider) the full range is 0 V to 25.5 V. V1 is
internally divided down by 10 before it is digitized by the
0.1*V1
Figure 14. Analog to Digital Converter
Table 13. ADC BYTE
DATA
MSB
5
4
3
2
1
LSB
D6
D5
D4
D3
D2
D1
D0
Table 14. REGISTER SETTING FOR ENABLING DESIRED ADC BEHAVIOUR
ADC_1
ADC_0
Description
0
0
Sets Amux to VFB
0
1
Sets Amux to V1
1
0
Sets Amux to CS2
1
1
Sets Amux to CS1
Interrupt Control
The interrupt source registers (14h,15h) always read 0
when any interrupt happens. The solution is to first keep
Int_mask_XXX registers (09h) low by default. INT can
toggle after any fault happens. Then set int_mask_XXX
registers to high, it will flag the corresponding interrupt
source registers if the fault is still there. Now the interrupt
source registers can be read. In the end, set int_mask_XXX
registers to low again after reading interrupt status registers.
The interrupt controller continuously monitors internal
interrupt sources, generating an interrupt signal when
a system status change is detected. Individual bits
generating interrupts will be set to 1 in the INTACK register
(I2C read only registers), indicating the interrupt source. All
interrupt sources can be masked by writing 1 in register
INTMSK. Masked sources will never generate an interrupt
request on the INT pin. The INT pin is an open drain output.
A non−masked interrupt request will result in the INT pin
being driven high. Figure 15 illustrates the interrupt process.
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NCP81231
OV
OV
OV_MASK
SHUTDN
OV _REG
SHUTDN_MASK
TEMP
PG
TEMP_MASK
INT
PG
PG_MASK
PG_REG
INTOCP
INTOCP_MASK
TEMP
EXTOC
EXTOC_MASK
INTACK
TEMP_REG
INTACK_MASK
VCHN
INT
VCHN_MASK
Figure 15. Interrupt Logic
I2C Address
Table 15. INTERPRETATION TABLE
Interrupt Name
OV
Shutdown
TEMP
PG
The default address is set to 77h.
Description
Output Over Voltage
Shutdown Detection (EN=low)
IC Thermal Trip
Power Good Trip Thresholds Exceeded
INTOCP
Internal Current Limit Trip
EXTOC
External Current Trip from CLIND
VCHN
Output Negative Voltage Change
INTACK
I2C ACK signal to the host
Table 16. I2C ADDRESS
I2C Address
Hex
A6
A5
A4
A3
A2
A1
A0
ADD0 (default)
0x77
1
1
1
0
1
1
1
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17
NCP81231
I2C interface
external processor by means of a serial link using a 400 kHz
up to 1.2 MHz I2C two−wire interface protocol. The I2C
interface provided is fully compatible with the Standard,
Fast, and High−Speed I2C modes. The NCP81231 is not
intended to operate as a master controller; it is under the
control of the main controller (master device), which
controls the clock (pin SCL) and the read or write operations
through SDA. The I2C bus is an addressable interface (7−bit
addressing only) featuring two Read/Write addresses.
The I2C interface can support 5 V TTL, LVTTL, 2.5 V and
1.8 V interfaces with two precision SCL and SDA
comparators with 1V thresholds shown in Figure 16. The
part cannot support 5 V CMOS levels as there can be some
ambiguity in voltage levels.
I2C Compatible Interface
The NCP81231 can support a subset of I2C protocol as
detailed below. The NCP81231 communicates with the
5V CMOS
Vcc =4.5V−5.5V
TTL
Vcc =4.5V−5.5V
V OH = 4.44V
LVTTL
Vcc =2.7V−3.6V
EIS/JEDEC 8−5
V IH = 0.7*vcc
VTH = 0.5* vcc
VIL = 0.3*vcc
V OH = 2.4V
2.5
Vcc =2.3V−2. 7V
EIS/JEDEC 8−5
V OH = 2.4V
VIH = 2.0V
VIH = 2. 0V
1.8V
Vcc =1.65V−1.95V
EIS/JEDEC 8−7
VOH = 2. 0V
VIH = 1.7V
VOH = VCC−0.45V
V IH = 0. 65*Vcc
VIL = 0.8V
VOL = 0.4V
V IL = 0.7V
VOL = 0.4V
VTH = 1. 5V
VIL = 0.8V
VOL = 0.4V
VOL = 0.5V
V IL = 0.35*Vcc
1.0V Threshold
VOL = 0.45V
Figure 16. I2C Thresholds and Comparator Thresholds
I2C Communication Description
The first byte transmitted is the chip address (with the LSB
bit set to 1 for a Read operation, or set to 0 for a Write
operation). Following the 1 or 0, the data will be:
• In case of a Write operation, the register address
(@REG) pointing to the register for which it will be
written is followed by the data that will written in that
location. The writing process is auto−incremental, so
•
the first data will be written in @REG, the contents of
@REG are incremented, and the next data byte is
placed in the location pointed to @REG + 1 ..., etc.
In case of a Read operation, the NCP81231 will output
the data from the last register that has been accessed by
the last write operation. Like the writing process, the
reading process is auto−incremental.
From MCU to NCP81231
From NCP81231 to MCU
Start
1
IC ADDRESS 1
ACK
DATA 1
ACK
Data n
ACK
DATA 1
ACK
Data n
/ACK STOP
READ OUT
FROM PART
Read
/ACK
Start
IC ADDRESS 0
STOP Write Inside Part
ACK
If part does not Acknowledge, the /NACK will be followed by a STOP or Sr. If part
Acknowledges, the ACK can be followed by another data or STOP or Sr.
0
Write
Figure 17. General Protocol Description
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NCP81231
Read out from part
then start or a repeated start will initiate the Read transaction
from the register address the initial Write transaction was
pointed to:
The master will first make a “Pseudo Write” transaction
with no data to set the internal address register. Then, a stop
From MCU to NCP81231
From NCP81231 to MCU
Start
0
IC ADDRESS
0
Sets Internal
Register Pointer
Register Address
ACK
ACK STOP
Write
Start
IC ADDRESS
1
ACK
DATA 1
ACK
Data n
/ACK STOP Write Inside Part
Register Address + (n+1)
Value
Register Address
Value
N Register Read
1
Read
Figure 18. Read Out From Part
From MCU to NCP81231
From NCP81231 to MCU
Start
IC ADDRESS
0
Sets Internal
Register Pointer
ACK
Write Value in
Register REG + (n−1)
Write Value in
Register REG
Register REG Address ACK
REG Value
REG + (n−1) Value
ACK
N Register Read
0
Write
Start
IC ADDRESS
1
ACK
DATA 1
ACK
Data n
/ACK STOP
Register Address +(n+1)+
(k−1) Value
Register Address + (n−1)
Value
k Register Read
1
Read
Figure 19. Write Followed by Read Transaction
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19
ACK STOP
NCP81231
Write In Part
Write operation will be achieved by only one transaction.
After the chip address, the MCU first data will be the internal
register desired to access, the following data will be the data
written in REG, REG + 1, REG + 2, ..., REG + (n−1).
From MCU to NCP81231
From NCP81231 to MCU
Start
IC ADDRESS 0
Write Value in
Register REG + (n−1)
Write Value in
Register REG
Sets Internal
Register pointer
ACK Register REG Address ACK
REG Value
REG + (n−1) Value
ACK
ACK STOP
N Register Read
0
Write
Figure 20. Write in n Registers
DESIGN CONSIDERATIONS
allowed maximum total gate charge Qg can be estimated by
Equation 2:
dv/dt Induced False Turn On
In synchronous buck converters, there is a well−known
phenomenon called “low side false turn−on,” or “dv/dt
induced turn on”, which can be potentially dangerous for the
switch itself and the reliability of the entire converter.
Qg +
Vin
4−Switch
Buck−boost
Controller
L
Vsw1
Drain
Cgd
Rpu_ds(on)
Rg_ext
Rg_int
S2
LSG1
Gate
Rpd_ds(on)
GND
+
dV/dt
Cgs
Vgs’
−
(eq. 2)
where Idriver is the gate drive current and fsw is the switching
frequency.
It is recommended to select the MOSFETs with smaller
than 3 nF input capacitance (Ciss). The gate threshold
voltage should be higher than 1.0 V due to the internal
adaptive non−overlap gate driver circuit.
In order to prevent dv/dt induced turn−on, the criteria for
selecting a rectifying switch is based on the Qgd/Qgs(th) ratio.
Qgs(th) is the gate−to−source charge before the gate voltage
reaches the threshold voltage. Lowering Cgd will reduce
dv/dt induced voltage magnitude. Moreover, it also depends
on dt/Cgs, Vds and threshold voltage Vth. One way of
interpreting the dv/dt induced turn−on problem is when Vds
reaches the input voltage, the Miller charge should be
smaller than the total charge on Cgs at the Vth level, so that
the rectifying switches will not be turned on. Then we will
have the following relation:
Buck phase dv/dt induced false
turn on equivalent circuit
S1
I driver
f sw
Source
Figure 21. dv/dt Induced False Turn−on Equivalent
Circuit of a Buck Converter
V gs +
C gd
C gd ) C gs
V ds t V gs(th)
(eq. 3)
Figure 21 shows false turn on equivalent circuit of the
buck converter at the moment a positive dv/dt transition
appears across the drain−to−source junction. The detailed
analysis of this phenomenon can be found in Gate Driver
Design Considerations for 4−Switch Buck−Boost
Converters.
We can simply use Equation 4 to evaluate the rectifying
device’s immunity to dv/dt induced turn on. Ideally, the
charge Qgd should not be greater than 2*Qgs(th) in order to
leave enough margin.
Select the Switching Power MOSFET
Select Gate Drive Resistors
Q gd t Q GS(th)
(eq. 4)
To increase the converter’s dv/dt immunity, the dv/dt
control is one approach which is usually related to the gate
driver circuit. A first intuitive method is to use higher pull
up resistance and gate resistance for the active switch. This
would slow down the turn on of the active switch, effectively
decreasing the dv/dt. Table 17 shows the recommended
value for MOSFETs’ external gate drive resistors.
The MOSFETs used in the power stage of the converter
should have a maximum drain−to−source voltage rating that
exceeds the sum of steady state maximum drain−to−source
voltage and the turn−off voltage spike with a considerable
margin (20%~50%).
When selecting the switching power MOSFET, the
MOSFET gate capacitance should be considered carefully
to avoid overloading the 5 V LDO. For one MOSFET, the
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20
NCP81231
• V1 Pin: Input for the internal LDO. Place a decoupling
Table 17. RECOMMENDED VALUE FOR EXTERNAL
GATE DRIVE RESISTORS
HSG1
(3.3~5.1)W
LSG1
0W
•
An alternative approach is to add an RC snubber circuit to
the switching nodes VSW1. This is the most direct way to
reduce the dv/dt. The side effect of the above two methods
are that losses would be increased because of slow switching
speed.
•
LAYOUT GUIDELINES
•
Electrical Layout Considerations
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction.
• Current Sensing: Run two dedicated trace with decent
width in parallel (close to each other to minimize the
loop area) from the two terminals of the input side or
output side current sensing resistor to the IC. Place the
common−mode RC filter components in general
proximity of the controller.
•
•
Route the traces into the pads from the inside of the current
sensing resistor. The drawing below shows how to rout the
traces.
Current Path
•
•
Current Sense
Resistor
PCB Trace
•
CSP/CSN
•
• Gate Driver: Run the high side gate, low side gate and
•
switching node traces in a parallel fashion with decent
width. Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing
VSW1 trace to high−side MOSFET source pin instead
of copper pour area. The controller should be placed
close to the switching MOSFETs gate terminals and
keep the gate drive signal traces short for a clean
MOSFET drive. It’s OK to place the controller on the
opposite side of the MOSFETs.
I2C Communication: SDA and SCL pins are digital
pins. Run SDA and SCL traces in parallel and reduce
the loop area. Avoid any sensitive analog signal trace or
noise source from crossing over or getting close.
capacitor in general proximity of the controller. Run a
dedicated trace from system input bus to the pin and do
not route near the switching traces.
VCC Decoupling: Place decoupling caps as close as
possible to the controller VCC pin. Place the RC filter
connecting with VDRV pin in general proximity of the
controller. The filter resistor should be not higher than
10 W to prevent large voltage drop.
VDRV Decoupling: Place decoupling caps as close as
possible to the controller VDRV pin.
Input Decoupling: The device should be well
decoupled by input capacitors and input loop area
should be as small as possible to reduce parasitic
inductance, input voltage spike, and noise emission.
Usually, a small low−ESL MLCC is placed very close
to the input port. Place these capacitors on the same
PCB layer with the MOSFETs instead of on different
layers and using vias to make the connection.
Output Decoupling: The output capacitors should be
as close as possible to the load.
Switching Node: The converter’s switching node
should be a copper pour to carry the current, but
compact because it is also a noise source of electrical
and magnetic field radiation. Place the inductor and the
switching MOSFETs on the same layer of the PCB.
Bootstrap: The bootstrap cap and an option resistor
need to be in general close to the controller and directly
connected between pin BST1 and pin VSW1
respectively.
Ground: It would be good to have separated ground
planes for PGND and AGND and connect the AGND
planes to PGND through a dedicated net tie or 0 W
resistor.
Voltage Sense: Route a “quiet” path for the input and
output voltage sense. AGND could be used as a remote
ground sense when differential sense is preferred.
Compensation Network: The compensation network
should be close to the controller. Keep FB trace short to
minimize it capacitance to ground.
Thermal Layout Considerations
Good thermal layout helps power dissipation and junction
temperature reduction.
• The exposed pads must be well soldered on the board.
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• More free vias are welcome to be around IC and
underneath the exposed pads to connect the inner
ground layers to reduce thermal impedance.
• Use large area copper pour to help thermal conduction
and radiation.
• Do not put the inductor too close to the IC, thus the heat
sources are distributed.
www.onsemi.com
21
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 485CE
ISSUE O
DATE 07 FEB 2012
1 32
SCALE 2:1
A
B
D
ÉÉÉ
ÉÉÉ
ÉÉÉ
PIN ONE
REFERENCE
0.15 C
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
E
TOP VIEW
(A3)
DETAIL B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
ÉÉÉ
ÇÇÇ
ÇÇÇ
EXPOSED Cu
0.15 C
L
L
MOLD CMPD
DETAIL B
0.10 C
ALTERNATE
CONSTRUCTION
A
0.08 C
NOTE 4
A1
SIDE VIEW
D2
DETAIL A
C
SEATING
PLANE
GENERIC
MARKING DIAGRAM*
K
8
1
XXXXXXXX
XXXXXXXX
AWLYYWWG
17
E2
32X
24
1
L
XXXXX
A
WL
YY
WW
G
25
32
32X
e
e/2
BOTTOM VIEW
b
0.10
M
C A-B B
0.05
M
C
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
32X
0.62
3.70
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
5.30
3.70
MILLIMETERS
MIN
MAX
0.80
1.00
−−−
0.05
0.20 REF
0.20
0.30
5.00 BSC
3.40
3.60
5.00 BSC
3.40
3.60
0.50 BSC
0.20
−−−
0.30
0.50
−−−
0.15
5.30
0.50
PITCH
32X
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34336E
TDFN8, 2X3, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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