NCP81252MNTXG

NCP81252 Single-Phase Voltage Regulator with SVID Interface for Computing Applications www.onsemi.com High Switching Frequency, High Efficiency, Integrated Power MOSFETs The NCP81252, a single−phase synchronous buck regulator, integrates power MOSFETs to provide a high−efficiency and compact−footprint power management solution for new generation computing CPUs. The device is able to deliver up to 14 A TDC output current on an adjustable output with SVID interface. Operating in high switching frequency up to 1.2 MHz allows employing small size inductors and capacitors while maintaining high efficiency due to integrated solution with high performance power MOSFETs. Current−mode RPM control with feedforward from both input power supply and output voltage ensures stable operation over wide operation condition. The NCP81252 is in a QFN48 6 x 6 mm package. Features • • • • • • • • • • • • • • • • Meets Intel® Server Specifications 5 V to 20 V Input Voltage Range 0.9 V/1.35 V Fixed Boot Voltage Adjustable Output Voltage with SVID Interface Integrated Gate Driver and Power MOSFETs Up to 14 A TDC Output Current 500 kHz ~ 1.2 MHz Switching Frequency Current−Mode RPM Control Programmable SVID Address and ICCMax Adaptive Voltage Positioning (AVP) Programmable DVID Feed−Forward to Support Fast DVID Feedforward Operation for Input Supply Voltage and Output Voltage Output Over−Voltage and Under−Voltage Protections External Current Limitation Programming with Inductor Current Sense QFN48, 6 x 6 mm, 0.4 mm Pitch Package This is a Pb−Free Device MARKING DIAGRAM 1 1 48 NCP81252 AWLYYWWG QFN48 CASE 485CJ NCP81252 A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device NCP81252MNTXG Package Shipping† QFN48 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Typical Applications • Server Applications © Semiconductor Components Industries, LLC, 2015 September, 2015 − Rev. 1 1 Publication Order Number: NCP81252/D 48 47 46 45 44 43 42 41 40 39 38 37 EN VCC VSP VSN DIFFOUT FB COMP FREQ CSREF CSSUM CSCOMP ILIM NCP81252 1 VRHOT# 2 SDIO 3 ALERT# 4 SCLK VCCP 33 5 GND GND 32 6 VRRDY 7 VIN 8 BST 9 IOUT 36 IMAX 35 GND 49 TSENSE 34 VBOOT 31 GL 30 SW 29 VIN 50 GH SW 51 SW 28 SW PGND PGND PGND PGND PGND PGND SW 25 VIN 12 VIN VIN SW 26 VIN 11 VIN VIN SW 27 VIN 10 SW 13 14 15 16 17 18 19 20 21 22 23 24 Figure 1. Pin Configuration (Top View) VIN BST VIN GH +5V PGND SW VCCP SW VOUT GL ILIM VCC CSCOMP GND EN VRHOT# SDIO ALERT# SCLK CSSUM NCP81252 CSREF VBOOT VRRDY TSENSE COMP FB DIFFOUT IMAX FREQ VSP IOUT VSN Figure 2. Typical Application Circuit www.onsemi.com 2 NCP81252 BST VCCP GH VIN VIN VCC UVLO SW Gate Drive EN VCCP GND PGND DAC VRRD Y Control Logic & Protections & VR Ready VSP−VSN GL OCP PWM IMON IOUT Current Measurement and Limit OCP ILIM VRH OT# VCS PWM Control Thermal Management CSREF TSENSE CSS UM FREQ VBO OT Frequency & VBOOT Detection VIN Current Sense 0.5 TSEN SE CSR EF DAC CSCOMP VDROOP COMP VSP−VSN CSC OMP COMP VBOOT IMAX MUX Error Amp IOUT ADC IMAX Vref TSENSE FB 1.3V DIFF OUT SDIO SCLK SVID Interface VSP Differential Amplifier Registers Vref DAC ALE RT# DAC DAC DVID FeedForward Figure 3. Functional Block Diagram www.onsemi.com 3 VSN NCP81252 Table 1. PIN DESCRIPTION Pin Name Type 1 VRHOT# Logic Output Description 2 SDIO Logic Bidirectional 3 ALERT# Logic Output 4 SCLK Logic Input 5, 32, 49 GND Analog Ground 6 VRRDY Logic Output Voltage Regulator Ready. Open−drain output. Provides a logic high valid power good output signal, indicating the regulator’s output is in regulation window. 7, 11−17, 50 VIN Power Input Power Supply Input. These pins are the power supply input pins of the device, which are connected to drain of internal high−side power MOSFET. 22 mF or more ceramic capacitors must bypass this input to power ground. The capacitors should be placed as close as possible to these pins. 8 BST Power Bidirectional 9 GH Analog Output Gate of High−Side MOSFET. Directly connected with the gate of the high−side power MOSFET. 10 SW Power Return Switching Node. Provides a return path for integrated high−side gate driver. It is internally connected to source of high−side MOSFET. 18, 25−29, 51 SW Power Output Switch Node. Pins to be connected to an external inductor. These pins are interconnection between internal high−side MOSFET and low−side MOSFET. 19−24 PGND Power Ground Power Ground. These pins are the power supply ground pins of the device, which are connected to source of internal low−side power MOSFET. Must be connected to the system ground. 30 GL Analog Output Gate of Low−Side MOSFET. Directly connected with the gate of the low−side power MOSFET. 31 VBOOT Analog Input 33 VCCP Analog Power 34 TSENSE Analog 35 IMAX Analog Input 36 IOUT Analog Output OUT Current Monitor. Provides output signal representing output current by connecting a resistor from this pin to ground. Shorting this pin to ground disables IMON function. 37 ILIM Analog Output Limit of Current. A resistor from this pin to CSCOMP programs over−current threshold with inductor current sense. 38 CSCOMP Analog Output Current Sense COMP. Output pin of current sense amplifier. 39 CSSUM Analog Input Current Sense SUM. Inverting input of current sense amplifier. 40 CSREF Analog Input Current Sense Reference. Non−Inverting input of current sense amplifier. 41 FREQ Analog Input Frequency. A resistor from this pin to ground programs switching frequency. 42 COMP Analog VR HOT. Logic low output represents over temperature. Serial Data IO Port. Data port of SVID interface. ALERT. Open−drain output. Provides a logic low valid alert signal of SVID interface. Serial Clock. Clock input of SVID interface. Analog Ground. Ground of internal control circuits. Must be connected to the system ground. Bootstrap. Provides bootstrap voltage for the high−side gate driver. A 0.1 mF ~ 1 mF ceramic capacitor is required from this pin to SW (pin10). A 1 ~ 2 W resistor may be employed in series with the BST cap to reduce switching noise and ringing when needed. Boot−Up Voltage. A resistor from this pin to ground programs SVID address. Voltage Supply of Gate Driver. Power supply input pin of internal gate driver. A 4.7 mF or larger ceramic capacitor bypasses this input to ground. This capacitor should be placed as close as possible to this pin. Temperature Sense. An external temperature sense network is connected to this pin. Current Maximum. A resistor from this pin to ground programs IMAX. Compensation. Output pin of error amplifier. 43 FB Analog Input 44 DIFFOUT Analog Output Feedback. Inverting input to error amplifier. 45 VSN Analog Input Voltage Sense Negative Input. Inverting input of differential voltage sense amplifier. It is also used for DVID feed forward function with an external resistor. Differential Amplifier Output. Output pin of differential voltage sense amplifier. 46 VSP Analog Input Voltage Sense Positive Input. Non−inverting input of differential voltage sense amplifier. 47 VCC Analog Power Voltage Supply of Controller. Power supply input pin of control circuits. A 1 mF or larger ceramic capacitor bypasses this input to ground. This capacitor should be placed as close as possible to this pin. 48 EN Logic Input Enable. Logic high enables the device and logic low makes the device in standby mode. www.onsemi.com 4 NCP81252 Table 2. MAXIMUM RATINGS Value Rating Symbol Power Supply Voltage to PGND Min VVIN Switch Node to PGND VSW Max Unit 30 V 30 V VCC, VCCP −0.3 6.5 V BST_PGND −0.3 33 38 ( threshold Low Low Disabled Soft Start EN > threshold UVLO > threshold Low Operational Active / No latch Normal Operation EN > threshold UVLO > threshold High Operational Active / Latching Over Voltage Low N/A DAC + 400 mV Over Current Low Operational Last DAC Code Vout = 0 V Low: if Reg34h:bit0 = 0; High:if Reg34h:bit0 = 1 Clamped at 0.9 V Disabled www.onsemi.com 10 Method of Reset N/A NCP81252 DETAILED DESCRIPTION General mode, the inductor current is continuous and the device operates in quasi−fixed switching frequency in medium and heavy load range, while the inductor current becomes discontinuous and the device automatically operates in PFM mode with an adaptive fixed on time and variable switching frequency in light load range. The NCP81252, a single−phase synchronous buck regulator, integrates power MOSFETs to provide a high−efficiency and compact−footprint power management solution for new generation computing CPUs. The device is able to deliver up to 14 A TDC output current on an adjustable output with SVID interface. Operating in high switching frequency up to 1.2 MHz allows employing small size inductors and capacitors while maintaining high efficiency due to integrated solution with high performance power MOSFETs. Current−mode RPM control with feedforward from both input power supply and output voltage ensures stable operation over wide operation condition. Serial VID interface (SVID) Current−Mode RPM Operation Boot Voltage and SVID Address The NCP81252 operates with the current−mode Ramp−Pulse−Modulation (RPM) scheme in PS0/1/2/3 operation modes. In forced CCM mode, the inductor current is always continuous and the device operates in quasi−fixed switching frequency, which has a typical value programmed by users through a resistor at pin FREQ. In auto CCM/DCM Table 5 shows two boot voltage options of 0.9 V and 1.35 V programmed by an external 1% resistor Rvboot from Vboot pin to GND, which programs SVID address as well. Both values are set on power up and cannot be changed after the initial power up sequence is complete. The NCP81252 supports Intel serial VID interface. It communicates with the microprocessor through three wires (SCLK, SDIO, ALERT#). For NCP81252, VID code change rate is controlled by the SVID interface with three options. Information regarding SVID interface can be obtained from Intel. Table 5. BOOT VOLTAGE AND SVID ADDRESS CONFIGURATION Vboot Pin Voltage (mV) Rvboot (W) Min Typ Max Address Vboot (V) 0 0 0 102 0x0 0.9 14.0k 102 140 180 0x1 0.9 22.1k 180 219 258 0x2 0.9 30.1k 258 301 344 0x3 0.9 39.2k 344 391 438 0x4 0.9 48.7k 438 484 531 0x5 0.9 57.6k 531 578 625 0x6 0.9 68.1k 625 676 727 0x7 0.9 78.7k 727 781 836 0x8 0.9 88.7k 836 894 953 0x0 1.35 100k 953 1007 1062 0x1 1.35 113k 1062 1125 1188 0x2 1.35 124k 1188 1250 1312 0x3 1.35 137k 1312 1378 1445 0x4 1.35 150k 1445 1511 1578 0x5 1.35 165k 1578 1648 1719 0x6 1.35 178k 1719 1789 1859 0x7 1.35 196k 1859 1950 − 0x8 1.35 www.onsemi.com 11 NCP81252 Switching Frequency Switching frequency is programmed by a resistor RFREQ to ground at the FREQ pin. The typical frequency range is from 500 kHz to 1.2 MHz. The FREQ pin provides approximately 2 V out and the source current is mirrored into the internal ramp generator. The switching frequency can be found in Figure 5 with a given RFREQ. The frequency shown in Figure 5 is under condition of 10 A output current at VID = 1 V. The frequency has a variation over VID voltage and loading current, which maintains similar output ripple voltage over different operation condition. Figure 6 shows frequency variations over the VID voltage range. Figure 5. Switching Frequency vs. RFREQ Figure 6. Switching Frequency vs. VID Voltage www.onsemi.com 12 NCP81252 Remote Voltage Sense The VDROOP voltage is a half of the voltage difference between the CSCOMP pin and the CSREF pin. A high performance differential amplifier is provided to accurately sense the output voltage of the regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points. The output (DIFOUT) of the remote sense amplifier is a sum of the error voltage (between the output VSP−VSN and the DAC), a load−line voltage VDROOP, and a 1.3 V DC bias. V DROOP + 0.5 @ V CS + 0.5 @ ǒV CSREF * V CSCOMPǓ (eq. 2) The DIFOUT signal then goes through a compensation network and into the inverting input (FB pin) of an error amplifier. The non−inverting input of the error amplifier is connected to the same 1.3 V used for the differential sense amplifier output bias. V DIFOUT + ǒV VSP * V VSNǓ ) ǒ1.3 V * V DACǓ ) V_DROOP (eq. 1) IOUT 36 RIOUT Vcs 0.5 35 ILIM 37 RILIM VDROOP ICCMAX & IOUT & ILIM RICCMAX ICCMAX L Current Sense CSREF VOUT Rcs_NTC IOUT Ccs1 Ccs2 Rcs2 CSSUM DCR 38 Rcs1 CSCOMP SW Rcs3 39 40 Figure 7. Differential Current−Sense Circuit Diagram Differential Current Sense The values of Rcs1 and Rcs2 are set based on a 220k NTC thermistor and the temperature effect of the inductor and thus usually they should not need to be changed. The gain Gcs can be adjusted by the value change of the Rcs3 resistor. The internal Vcs voltage should be set to the output voltage droop in applications with a DC load line requirement. In order to recover the inductor DCR voltage drop current signal, the pole frequency in the CSCOMP filter should be set equal to the zero from the output inductor, that means The differential current−sense circuit diagram is shown in Figure 7. An internally−used voltage signal Vcs, representing the inductor current level, is the voltage difference between CSREF and CSCOMP. The output side of the inductor is used to create a low impedance virtual ground. The current−sense amplifier actively filters and gains up the voltage applied across the inductor to recover the voltage drop across the inductor’s DC resistance (DCR). RCS_NTC is placed close to the inductor to sense the temperature. This allows the filter time constant and gain to be a function of the Rth_NTC resistor and compensate for the change in the DCR with temperature. The DC gain in the current sensing loop is G CS + V CS V DCR + V CSREF * V CSCOMP I OUT @ DCR + R CS R CS3 C CS1 ) C CS2 + R CS + R CS2 ) (eq. 3) LL + R CS1 ) R CS_NTC (eq. 5) Ccs1 and Ccs2 are in parallel to allow for a fine tuning of the time constant using commonly available values. In applications with a droop voltage VDROOP, the DC load line LL can be obtained by Where R CS1 @ R CS_NTC L DCR @ R CS (eq. 4) V DROOP I OUT + 0.5 @ www.onsemi.com 13 + R CS R CS3 0.5ǒV CSREF * V CSCOMPǓ I OUT @ DCR (eq. 6) NCP81252 Over Current Protection ground such that a load equal to ICCMAX generates a 2 V signal on IOUT. A pull−up resistor to 5 V VCC can be used to offset the IOUT signal positive if needed. The NCP81252 provides two different types of current limit protection. Current limits are programmed with a resistor RILIM between the CSCOMP pin and the ILIM pin. The current from the ILIM pin to this resistor is then compared to two internal currents (10 mA and 15 mA) corresponding to two different current limit thresholds ILIM and ILIM_Fast (150% of ILIM level). If the ILIM pin current exceeds the 10 mA level, an internal latch−off timer starts. The controller shuts down if the fault is not removed after 50 ms. If the current into the pin exceeds 15 mA the controller will shut down immediately. To recover from an OCP fault the EN pin must be cycled low. The value of RILIM can be designed using the following equation with a required over current protection threshold ILIM and a known current−sense network. R ILIM + + V CS@I LIM R CS R CS3 10 m @ ǒ + I LIM ) R CS R CS3 R IOUT + 2 @ L @ F SW @ V IN Ǔ @ R ILIM 1 + 5@ RCS RCS3 @ R ILIM (eq. 9) @ ICC_MAX @ DCR Input UVLO Protection NCP81252 monitors supply voltages at the VCC pin and the VIN pins in order to provide under voltage protection. If either supply drops below its threshold, the controller will shut down the outputs. Upon recovery of the supplies, the controller reenters its startup sequence, and soft start begins. Output Under−Voltage Protection @ I LIM_PK @ DCR @ 10 5 ǒVIN * VOUTǓ @ VOUT 2 10 @ V CS@ICC_MAX The output voltage is monitored by a dedicated differential amplifier. If the output falls below target by more than “Under Voltage Threshold below DAC−Droop”, the UVL comparator sends the VR_RDY signal low. (eq. 7) @ DCR @ 10 5 Output Over−Voltage Protection ICC_MAX During normal operation the output voltage is monitored at the differential inputs VSP and VSN. If the output voltage exceeds the DAC voltage by “Over Voltage Threshold above DAC”, GH will be forced low, and GL will go high. After the OVP trips, the DAC ramps slowly down to zero to avoid a negative output voltage spike during shutdown. If the DAC+OVP Threshold drops below the output, GL will again go high, and will toggle between low and high as the output voltage follows the DAC+OVP Threshold down. When the DAC gets to zero, the GH will be held low and the GL will remain high. To reset the part, the EN pin must be cycled low. During soft−start, the OVP threshold is set to 2.9 V. This allows the controller to start up without false triggering the OVP. A resistor connected from IMAX pin to ground sets ICC_MAX value at startup. A 10 mA current is sourced from this pin to generate a voltage on the program resistor. The resistor value can be determined by the following equation. The resistor value should be no less than 10 k. ICC_MAX + R ICCMAX @ 10 m @ 64 2 + R ICCMAX @ 3.2 @ 10 −4 (eq. 8) IOUT The IOUT pin sources a current equal to the ILIM sink current gained by the IOUT Current Gain (10 typ.). The voltage of the IOUT pin is monitored by the internal A/D converter and should be scaled with an external resistor to (b) During Start Up (a) Normal Operation Mode Figure 8. Function of Over Voltage Protection www.onsemi.com 14 NCP81252 Temperature Sense and Thermal Alert monitors the voltage at the TSENSE pin and compares the voltage to internal thresholds and assert ALERT# or VRHOT# once it trips the thresholds. The DC voltage at TSENSE pin can be calculated by The NCP81252 provides an external temperature sense and a thermal alert in normal operation mode. The temperature sense and thermal alert circuit diagram is shown in Figure 9. A precision current ITSENSE is sourced out the output of the TSENSE pin to generate a voltage across the temperature sense network, which consists of a NTC thermistor R_NTC (100 kW typ.), two resistors R_COMP1 (0 W typ.) and R_COMP2 (8.2 kW typ.), and a filter capacitor C_Filter (0.1 mF typ.). The voltage on the temperature sense input is sampled by the internal A/D converter and then digitally converted to temperature and stored in SVID register 17h. Usually the thermistor is placed close to a hot spot like inductor or NCP81252 itself. A 100k NTC thermistor similar to the Murata NCP15WF104D03RC should be used. The NCP81252 also ǒ R COMP1 ) ǒ ǒ ǓǓ R NTC_T + R NTC_T @ exp B @ 0 where RNTC_T0 is a known resistance of R_NTC at an absolute temperature T0, and B is the B−constant of R_NTC. TSENSE VRHOT# R_COMP2 C_Filter 3.3V ALERT# 3 1 1 * T T0 (eq. 11) R_NTC 1 Ǔ R COMP2 ) R NTC_T RNTC_T is the resistance of R_NTC at an absolute temperature T, which is obtained by Thermal Management VRHOT# R COMP2 @ R NTC_T (eq. 10) R_COMP1 34 V TSENSE + I TSENSE @ ALERT# Figure 9. Temperature Sense and Thermal Alert Circuit Diagram www.onsemi.com 15 NCP81252 LAYOUT GUIDELINES Electrical Layout Considerations limiting, and IOUT reporting. The filter cap from CSCOMP to CSREF should be close to the controller. The temperature compensating thermistor should be placed as close as possible to the inductor. The wiring path should be kept as short as possible and well away from the switch node. − Compensation Network: The small feedback cap from COMP to FB should be as close to the controller as possible. Keep the FB traces short to minimize their capacitance to ground. − SVID Bus: The Serial VID bus is a high speed data bus and the bus routing should be done to limit noise coupling from the switching node. The signals should be routed with the Alert# line in between the SVID clock and SVID data lines. The SVID lines must be ground referenced and each line’s width and spacing should be such that they have nominal 50 W impedance with the board stackup. Good electrical layout is a key to make sure proper operation, high efficiency, and noise reduction. Electrical layout guidelines are: − Power Paths: Use wide and short traces for power paths (such as VIN, VOUT, SW, and PGND) to reduce parasitic inductance and high−frequency loop area. It is also good for efficiency improvement. − Power Supply Decoupling: The device should be well decoupled by input capacitors and input loop area should be as small as possible to reduce parasitic inductance, input voltage spike, and noise emission. Usually, a small low−ESL MLCC is placed very close to VIN and PGND pins. − VCC Decoupling: Place decoupling caps as close as possible to the controller VCC and VCCP pins. The filter resistor at VCC pin should be not higher than 2.2 W to prevent large voltage drop. − Switching Node: SW node should be a copper pour, but compact because it is also a noise source. − Bootstrap: The bootstrap cap and an option resistor need to be very close and directly connected between pin 8 (BST) and pin 10 (SW). No need to externally connect pin 10 to SW node because it has been internally connected to other SW pins. − Ground: It would be good to have separated ground planes for PGND and GND and connect the two planes at one point. Directly connect GND pin to the exposed pad and then connect to GND ground plane through vias. − Voltage Sense: Use Kelvin sense pair and arrange a “quiet” path for the differential output voltage sense. − Current Sense: Careful layout for current sensing is critical for jitter minimization, accurate current Thermal Layout Considerations Good thermal layout helps high power dissipation from a small package with reduced temperature rise. Thermal layout guidelines are: − The exposed pads must be well soldered on the board. − A four or more layers PCB board with solid ground planes is preferred for better heat dissipation. − More free vias are welcome to be around IC and underneath the exposed pads to connect the inner ground layers to reduce thermal impedance. − Use large area copper pour to help thermal conduction and radiation. − Do not put the inductor to be too close to the IC, thus the heat sources are distributed. Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries. www.onsemi.com 16 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN48 6x6, 0.4P CASE 485CJ ISSUE A 1 48 SCALE 2:1 ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉ ÉÉ EXPOSED Cu A B D PIN ONE REFERENCE 2X 0.15 C DETAIL B ALTERNATE CONSTRUCTION E L L DIM A A1 A3 b D D2 D3 D4 D5 E E2 E3 E4 e G3 G4 H2 H3 H4 L L1 L2 DETAIL A TOP VIEW 0.08 C L2 A1 SIDE VIEW NOTE 4 ALTERNATE TERMINAL CONSTRUCTIONS A (A3) DETAIL B 0.10 C D3 DETAIL A 45 5 SEATING PLANE C D2 DETAIL C D4 13 25 E3 G3 DETAIL C G4 13 E4 25 E2 NOTE 5 1 48X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. POSITIONAL TOLERANCE APPLIES TO ALL THREE EXPOSED PADS IN BOTH X AND Y AXIS. L1 0.15 C 2X MOLD CMPD DATE 09 AUG 2012 48 L 0.10 37 48X e e/2 BOTTOM VIEW C A B M b 0.10 M C A B 0.05 M C 0.58 4.81 48X 2.09 4.80 6.30 0.40 PITCH 2.54 1.91 1 XXXXXXXXX XXXXXXXXX AWLYYWWG 37 D5 SUPPLEMENTAL BOTTOM VIEW XXXXX A WL YY WW G 6.30 0.25 H2 1 48 RECOMMENDED SOLDERING FOOTPRINT* 48X GENERIC MARKING DIAGRAM* H3 NOTE 3 H4 MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.15 0.25 6.00 BSC 4.53 4.73 1.64 1.84 2.42 2.62 4.58 4.78 6.00 BSC 1.86 2.06 2.41 2.61 2.30 2.50 0.40 BSC 1.45 BSC 1.06 BSC 1.40 BSC 1.19 BSC 1.10 BSC 0.25 0.45 −−− 0.15 0.15 REF = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 2.66 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON80730E QFN48, 6x6, 0.4MM PITCH Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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