NCP81258MNTBG

NCP81258 Product Preview Synchronous Buck MOSFET Driver The NCP81258 is a high−performance dual MOSFET gate driver in a small 2 mm x 2 mm package, optimized to drive the gates of both high−side and low−side power MOSFETs in a synchronous buck converter. A zero−current detection feature allows for a high−efficiency solution even at light load conditions. VCC UVLO ensures the MOSFETs are off when supply voltages are low. A bi−directional Enable pin provides a fault signal to the controller when a UVLO fault is detected. www.onsemi.com 1 DFN8 MN SUFFIX CASE 506AA Features • • • • • • • • • • • Space−efficient 2 mm x 2 mm DFN8 Thermally−enhanced Package VCC Range of 4.5 V to 13.2 V Internal Bootstrap Diode 5 V 3−stage PWM Input Zero Current Detect Function Provides Power Saving Operation during Light Load Conditions Bi−directional Enable Feature pulls Enable Pin Low during a UVLO Fault Pre−OVP Function Protects Load during HS FET Short Adaptive Anti−cross Conduction Circuit Protects against Cross−conduction during FET Turn−on and Turn−off Output Disable Control Turns Off Both MOSFETs via Enable Pin VCC Undervoltage Lockout These Devices are Pb−free, Halogen−free/BFR−free and are RoHS Compliant MARKING DIAGRAM 1 CRMG G CR = Specific Device Code M = Date Code G = Pb−Free Device (Note: Microdot may be in either location) PIN CONNECTIONS PWM 2 Typical Applications • Power Solutions for Notebook and Desktop Systems 8 DRVH BST 1 FLAG 9 EN 3 This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. VCC 7 SW 6 GND 5 DRVL 4 (Top View) ORDERING INFORMATION Device Package Shipping† NCP81258MNTBG DFN8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2017 June, 2017 − Rev. P0 1 Publication Order Number: NCP81258/D NCP81258 BST VCC DRVH Logic PWM SW Anti−Cross Conduction VCC DRVL VCC EN VCC UVLO ZCD Detection SW Fault Figure 1. Simplified Block Diagram Table 1. PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 1 BST Floating bootstrap supply pin for the high−side gate driver. Connect the external bootstrap capacitor between this pin and SW. 2 PWM Control input: PWM = High ³ DRVH is high, DRVL is low. PWM = Mid ³ Zero current detect enabled. Diode emulation mode. PWM = Low ³ DRVH is low, DRVL is high. 3 EN 4 VCC Power supply input. Connect a bypass capacitor (1 mF) from this pin to ground. 5 DRVL Low−side gate drive output. Connect to the gate of the low−side MOSFET. 6 GND Bias and reference ground. All signals are referenced to this node. 7 SW 8 DRVH High−side gate drive output. Connect to the gate of the high−side MOSFET. 9 FLAG Thermal flag. There is no electrical connection to the IC. Connect to the ground plane. Control input: EN = High ³ Driver is enabled. EN = Low ³ Driver is disabled. Switch node. Connect this pin to the source of the high−side MOSFET and drain of the low− side MOSFET. www.onsemi.com 2 NCP81258 Table 2. ABSOLUTE MAXIMUM RATINGS Rating Symbol Min Max Main Supply Voltage (Note 1) VCC −0.3 V 15 V 16 V (< 50 ns) Bootstrap Supply Voltage BST −0.3 V wrt/SW 35 V wrt/GND 40 V (v 50 ns) wrt/GND 15 V wrt/SW Switch Node Voltage SW −5 V −10 V (v 200 ns) 35 V 40 V (v 50 ns) High−Side Driver Output DRVH −0.3 V wrt/SW −2 V (v 200 ns) wrt/SW BST + 0.3 V SW + 15 V (< 80 ns) Low−Side Driver Output DRVL −0.3 V −5 V (v 200 ns) VCC + 0.3 V 15 V (< 80 ns) PWM, EN −0.3 V 6.5 V Ground GND 0V 0V Storage Temperature Range TSTG −55°C 150°C TJ −40°C 150°C DRVH/DRVL Control Input, Enable Pin Operating Junction Temperature Range Moisture Sensitivity Level MSL 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area. Table 3. THERMAL CHARACTERISTICS Rating Symbol Value Unit RθJA 74 °C/W Thermal Characteristics, DFN8, 2x2 mm (Note 2) Thermal Resistance, Junction−to−Air 2. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. Table 4. OPERATING RANGES (Note 3) Rating Symbol Min Max Unit VCC 4.5 13.2 V TA −10 125 °C Input Voltage Ambient Temperature 3. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area. www.onsemi.com 3 NCP81258 Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.5 V to 13.2 V, BST−SW = 4.5 V to 13.2 V, BST = 4.5 V to 30 V, SW = 0 V to 21 V; for typical values TA = 25°C, for min/max values TA = −10°C to 125°C; unless otherwise noted. (Notes 4, 5) Parameter Test Conditions Symbol Min Typ Max Unit 13.2 V 2.75 3.2 V 4.35 4.5 V SUPPLY VOLTAGE VCC Operation Voltage 4.5 Pre−OVP VCC Threshold UNDERVOLTAGE LOCKOUT VCC Start Threshold VCC rising VCC UVLO Hysteresis Output Overvoltage Trip Threshold at Startup VUVLO 3.8 VUVLO_HYS 150 200 250 mV 2.1 2.25 2.4 V VCC > Pre−OVP VCC Threshold SUPPLY CURRENT Normal Mode ICC + IBST, EN = 5 V, PWM = 100 kHz, CLOAD = 3 nF for DRVH, 3 nF for DRVL Inormal 12.2 Shutdown Mode mA ICC + IBST, EN = GND Ishutdown 0.5 Standby Current 1 ICC + IBST, EN = 5 V, PWM = 0 V, No loading on DRVH & DRVL Istandby1 2.1 mA Standby Current 2 ICC + IBST, EN = 5 V, PWM = 5 V, No loading on DRVH & DRVL Istandby2 2.2 mA 1.9 mA BOOTSTRAP DIODE Forward Voltage VCC = 12 V, Forward bias current = 2 mA 0.1 0.4 0.6 V PWM INPUT PWM Input High PWMHI 3.4 PWM Mid−State PWMMID 1.3 PWM Input Low PWMLO ZCD Blanking Timer V 2.7 V 0.7 V 250 ns HIGH−SIDE DRIVER (VCC = 12 V) W Output Impedance, Sourcing Current (VBST – VSW) = 12 V 2.0 3.5 Output Impedance, Sinking Current (VBST – VSW) = 12 V DRVH Rise Time VCC = 12 V, 3 nF load, (VBST – VSW) = 12 V trDRVH 1.0 2.0 W 16 30 ns DRVH Fall Time VCC = 12 V, 3 nF load, (VBST – VSW) = 12 V tfDRVH 11 25 ns DRVH Turn−Off Propagation Delay Cload = 3 nF, [PWM = PWMLO] to [VDRVH = 90%] tpdlDRVH 30 ns DRVH Turn−On Propagation Delay Cload = 3 nF, [VDRVL = 1 V] to [VDRVH−VSW = 10%] tpdhDRVH 30 ns SW Pull−down Resistance SW to PGND 37.5 kW DRVH Pull−down Resistance DRVH to SW, (VBST – VSW) = 0 V 37.5 kW Output Impedance, Sourcing Current (VBST – VSW) = 5 V 2.5 W Output Impedance, Sinking Current (VBST – VSW) = 5 V 1.6 W DRVH Rise Time VCC = 5 V, 3 nF load, (VBST – VSW) = 5 V trDRVL 30 ns DRVH Fall Time VCC = 5 V, 3 nF load, (VBST – VSW) = 5 V tfDRVL 27 ns DRVH Turn−Off Propagation Delay CLOAD = 3 nF, [PWM = PWMLO] to [VDRVH = 90%] tpdlDRVL 20 ns DRVH Turn−On Propagation Delay CLOAD = 3 nF, [VDRVL = 1 V] to [VDRVH−VSW = 10%] tpdhDRVL 27 ns SW Pull−down Resistance SW to PGND 37.5 kW 8 HIGH−SIDE DRIVER (VCC = 5 V) www.onsemi.com 4 NCP81258 Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.5 V to 13.2 V, BST−SW = 4.5 V to 13.2 V, BST = 4.5 V to 30 V, SW = 0 V to 21 V; for typical values TA = 25°C, for min/max values TA = −10°C to 125°C; unless otherwise noted. (Notes 4, 5) Parameter Test Conditions Symbol Min Typ Max Unit HIGH−SIDE DRIVER (VCC = 5 V) DRVH Pull−down Resistance DRVH to SW, (VBST – VSW) = 0 V 37.5 Output Impedance, Sourcing Current VCC = 12 V 2.0 3.5 W Output Impedance, Sinking Current VCC = 12 V 0.7 1.8 W DRVL Rise Time VCC = 12 V, CLOAD = 3 nF trDRVL 16 35 ns DRVL Fall Time VCC = 12 V, CLOAD = 3 nF tfDRVL 11 20 ns DRVL Turn−Off Propagation Delay CLOAD = 3 nF, [PWM = PWMHI] to [VDRVL = 90%] tpdlDRVL 35 ns DRVL Turn−On Propagation Delay CLOAD = 3 nF, [VDRVH−VSW] = 1 V to [VDRVL = 10%] tpdhDRVL 30 ns DRVL Pull−down Resistance DRVL to GND, VCC = GND 37.5 kW Output Impedance, Sourcing Current VCC = 5 V 2.5 W Output Impedance, Sinking Current VCC = 5 V 1.0 W DRVL Rise Time VCC = 5 V, CLOAD = 3 nF trDRVL 30 ns DRVL Fall Time VCC = 5 V, CLOAD = 3 nF tfDRVL 22 ns DRVL Turn−Off Propagation Delay CLOAD = 3 nF, [PWM = PWMHI] to [VDRVL = 90%] tpdlDRVL 27 ns DRVL Turn−On Propagation Delay CLOAD = 3 nF, [VDRVH−VSW = 1 V] to [VDRVL = 10%] tpdhDRVL 12 ns DRVL Pull−down Resistance DRVL to GND, VCC = GND 37.5 kW kW LOW−SIDE DRIVER (VCC = 12 V) 8 LOW−SIDE DRIVER (VCC = 5 V) EN INPUT Enable Voltage High ENHI Enable Voltage Low ENLO 2.0 V 1.0 Hysteresis 500 V mV Normal Bias Current −1 1 mA Enable Pin Sink Current 4 30 mA 60 ms 20 mA EN High Propagation Delay Time PWM = 0 V, EN going from 0 V to ENHI to DRVL rising to 10% tpdEN_HI SWITCH NODE SW Node Leakage Current Zero Cross Detection Threshold Voltage Ramp slowly until DRVL goes off (start in DCM mode) −3 mV 4. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area. 5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 6. Values based on design and/or characterization. Table 6. ZCD DECODER TRUTH TABLE PWM Input ZCD DRVL DRVH PWM High ZCD Reset Low High PWM Mid (positive current) Positive current through the inductor High Low PWM Mid (negative current) Zero current through the inductor (after ZCD blanking timer) Low Low PWM Low ZCD Reset High Low www.onsemi.com 5 NCP81258 12V_POWER VIN R2 C2 0.0 0.1 uF Q1 R1 1.02 C4 C5 4.7 uF 4.7 uF NCP81258 C6 C7 4.7 uF 390 uF R3 BST DRVH PWM SW L 0.0 PWM Q2 DRON Q3 EN C1 1 uF C3 2700 pF DRVL VCC 235 nH R4 2.2 PAD Figure 2. Application Circuit PWM tpdlDRVL tfDRVL DRVL 90% 90% 1V 10% 10% tpdhDRVH tpdlDRVH tfDRVH trDRVH 90% DRVH− SW trDRVL 90% 10% 1V 10% tpdh DRVL Figure 3. Gate Timing Diagram www.onsemi.com 6 VCCP NCP81258 PWM DRVH−SW DRVL IL Figure 4. PWM/EN Logic Diagram APPLICATIONS INFORMATION (MLCC) with a value greater than 100 nF should be used for CBST. The NCP81258 gate driver is a single−phase MOSFET driver designed for driving N−channel MOSFETs in a synchronous buck converter topology. Power Supply Decoupling The low−side driver is designed to drive a ground−referenced low−RDS(on) N−channel MOSFET. The voltage supply for the low−side driver is internally connected to the VCC and GND pins. The NCP81258 can source and sink relatively large currents to the gate pins of the MOSFETs. In order to maintain a constant and stable supply voltage, a low−ESR capacitor should be placed near the VCC and GND pins. A MLCC between 1 mF and 4.7 mF is typically used. High−Side Driver Undervoltage Lockout The high−side driver is designed to drive a floating low−RDS(on) N−channel MOSFET. The gate voltage for the high−side driver is developed by a bootstrap circuit referenced to the SW pin. The bootstrap circuit is comprised of the integrated diode and an external bootstrap capacitor. When the NCP81258 is starting up, the SW pin is held at ground, allowing the bootstrap capacitor to charge up to VCC through the bootstrap diode. When the PWM input is driven high, the high−side driver will turn on the high−side MOSFET using the stored charge of the bootstrap capacitor. As the high−side MOSFET turns on, the SW pin rises. When the high−side MOSFET is fully turned on, SW will settle to VIN, and BST will settle to VIN + VCC (excluding parasitic ringing). DRVH and DRVL are low until VCC reaches the VCC UVLO threshold, typically 4.35 V. Once VCC reaches this threshold, the PWM signal will control DRVH and DRVL. There is a 200 mV hysteresis on VCC UVLO. There are pull−down resistors on DRVH, DRVL and SW to prevent the gates of the MOSFETs from accumulating enough charge to turn on when the driver is powered off. Low−Side Driver Pre−Overvoltage Protection The pre−Overvoltage Protection (pre−OVP) feature is used to protect the load if there is a short across the high−side FET. When VCC is greater than 2.75 V, the voltage on SW is monitored. During startup, if SW is determined to be greater than Output Overvoltage Trip Threshold, DRVL will be latched high to turn on the synchronous FET and provide a path from VIN to ground. This also pulls the EN pin low. To exit this behavior, power to the driver must be turned off (VCC less than VUVLO minus VUVLO_HYS) and then VCC powered back on. When VCC rises above VUVLO and EN is Bootstrap Circuit The bootstrap circuit relies on an external charge storage capacitor (CBST) and an integrated diode to provide current to the high−side driver. A multi−layer ceramic capacitor www.onsemi.com 7 NCP81258 tpdhDRVL from the time DRVH – SW falls to 1 V, before DRVL is allowed to turn on. When PWM enters the mid−state voltage range, PWMMID, DRVL goes high after the non−overlap delay, and stays high for the duration of the ZCD blanking timer and an 80 ns de−bounce timer. Once these timers expire, SW is monitored for zero current detection and pulls DRVL low once zero current is detected. above ENHI, the gate driver enters normal PWM operation if SW is no longer above the Output Overvoltage Trip Threshold. Bi−Directional EN Signal The Enable pin (EN) is used to disable the DRVH and DRVL outputs to prevent power transfer. When EN is above the ENHI threshold, DRVH and DRVL change their states according to the PWM input. A UVLO fault turns on the internal MOSFET that pulls the EN pin towards ground. By connecting EN to the DRON pin of a controller, the controller is alerted when the driver encounters a fault condition. Every time EN is brought from a low to a high state, the NCP81258 conducts an auto−calibration cycle on the ZCD SW threshold. During the auto−calibration cycle, the driver outputs are prevented from responding to the PWM input, and both outputs are in the low state. This auto−calibration cycle is guaranteed to complete by 60 ms. Thermal Considerations As power in the NCP81258 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. When the NCP81258 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power applications. The maximum dissipation the NCP81258 can handle is given by: Three−State PWM Input Switching PWM between logic−high and logic−low states will allow the driver to operate in continuous conduction mode as long as VCC is greater than the UVLO threshold and EN is high. The threshold limits are specified in the electrical characteristics table in this datasheet. Refer to Figure 21 for the gate timing diagrams and Table 1 for the EN/PWM logic table. When PWM is set above PWMHI, DRVL will first turn off after a propagation delay of tpdlDRVL. To ensure non−overlap between DRVL and DRVH, there is a delay of tpdhDRVH from the time DRVL falls to 1 V, before DRVH is allowed to turn on. When PWM falls below PWMLO, DRVH will first turn off after a propagation delay of tpdlDRVH. To ensure non−overlap between DRVH and DRVL, there is a delay of P D(MAX) + ƪTJ(MAX) * TAƫ R qJA (eq. 1) Since TJ is not recommended to exceed 150°C, the NCP81258, soldered on to a 645 mm2 copper area, using 1 oz. copper and FR4, can dissipate up to 2.3 W when the ambient temperature (TA) is 25°C. The power dissipated by the NCP81258 can be calculated from the following equation: P D [ VCC ƪǒnHS (eq. 2) Qg HS ) n LS Qg LSǓ f ) I standby ƫ Where nHS and nLS are the number of high−side and low−side FETs, respectively, QgHS and QgLS are the gate charges of the high−side and low−side FETs, respectively and f is the switching frequency of the converter. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8 2x2, 0.5P CASE 506AA−01 ISSUE E DATE 22 JAN 2010 1 SCALE 4:1 D PIN ONE REFERENCE 2X 0.10 C 2X A B ÇÇ ÇÇ ÇÇ 0.10 C L1 DETAIL A E OPTIONAL CONSTRUCTIONS DIM A A1 A3 b D D2 E E2 e K L L1 ÉÉ ÉÉ EXPOSED Cu TOP VIEW A DETAIL B 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L MOLD CMPD DETAIL B OPTIONAL CONSTRUCTION 0.08 C (A3) NOTE 4 SIDE VIEW A1 C SEATING PLANE GENERIC MARKING DIAGRAM* 1 DETAIL A D2 1 8X 4 L 8 5 e/2 e 8X XXMG G XX = Specific Device Code M = Date Code G = Pb−Free Device E2 K MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.30 REF 0.25 0.35 −−− 0.10 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. b 0.10 C A B 0.05 C NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* BOTTOM VIEW 1.30 PACKAGE OUTLINE 0.90 8X 0.50 2.30 1 8X 0.30 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON18658D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFN8, 2.0X2.0, 0.5MM PITCH PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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