NCP81274MNTXG

NCP81274 8/7/6/5/4/3/2/1 Phase Buck Controller with PWM_VID and I2C Interface The NCP81274 is a multiphase synchronous controller optimized for new generation computing and graphics processors. The device is capable of driving up to 8 phases and incorporates differential voltage and phase current sensing, adaptive voltage positioning and PWM_VID interface to provide and accurately regulated power for computer or graphic controllers. The integrated power saving interface (PSI) allows for the processors to set the controller in one of three modes, i.e. all phases on, dynamic phases shedding or fixed low phase count mode, to obtain high efficiency in light-load conditions. The dual edge PWM multiphase architecture ensures fast transient response and good dynamic current balance. www.onsemi.com 1 QFN40 CASE 485CR MARKING DIAGRAM 1 Features Typical Applications NCP81274 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package (Note: Microdot may be in either location) PSI EN SCL SDA VCC VSN VSP 36 35 34 33 32 31 PGOOD 37 38 VID_BUFF PWM_VID 40 39 PIN CONNECTIONS REFIN 1 30 COMP VREF 2 29 FB VRMP 3 PWM8/SS 4 NCP81274 28 DIFF 27 FSW 26 LLTH/I2C_ADD 25 IOUT 24 ILIM PWM7/OCP 5 PWM6/LPC1 6 PWM5/LPC2 7 PWM4/PHTH1 8 23 CSCOMP PWM3/PHTH2 9 22 CSSUM PWM2/PHTH3 10 21 CSREF (TOP VIEW) 16 17 18 19 20 CSP5 CSP4 CSP3 CSP2 CSP1 15 13 14 CSP8 CSP7 CSP6 12 Tab: GROUND 11 • • • • • ON NCP 81274 AWLYYWWG G DRON • • Compliant with NVIDIA® OVR4+ Specifications Supports Up to 8 Phases 4.5 V to 20 V Supply Voltage Range 250 kHz to 1.2 MHz Switching Frequency (8 Phase) Power Good Output Under Voltage Protection (UVP) Over Voltage Protection (OVP) Over Current Protection (OCP) Per Phase Over Current Protection Startup into Pre-Charged Loads while Avoiding False OVP Configurable Adaptive Voltage Positioning (AVP) High Performance Operational Error Amplifier True Differential Current Balancing Sense Amplifiers for Each Phase Phase-to-Phase Dynamic Current Balancing Current Mode Dual Edge Modulation for Fast Initial Response to Transient Loading Power Saving Interface (PSI) Automatic Phase Shedding with User Settable Thresholds PWM_VID and I2C Control Interface Compact 40 Pin QFN Package (5 × 5 mm Body, 0.4 mm Pitch) This Device is Pb-Free and is RoHS Compliant PWM1/ PHTH4 • • • • • • • • • • • • • 40 ORDERING INFORMATION • GPU and CPU Power • Graphic Cards • Desktop and Notebook Applications Device Package Shipping† NCP81274MNTXG QFN40 (Pb-Free) 5000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2017 June, 2017 − Rev. 14 1 Publication Order Number: NCP81274/D VCC_DUT PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 R4 10k 1k R9 R7 10k C1 0.01uF R8 DNP R6 DNP R5 DNP VIN R3 DNP R1 DNP R2 10k TP40 TP41 TP39 TP38 TP42 TP37 R13 1k R12 DNP R11DNP R10 10k VREF TP43 C2 R14 1k R21 16.5k R18 33k 10nF C4 C3 4.7nF R16 309R 4.7nF DRON R22 68k 20.5k R28 TP62 R32 215k R36 215k R35 215k R34 215k R33 215k R31 215k R29 215k 40 PWM1/PHTH4 PWM2/PHTH3 PWM3/PHTH2 PWM4/PHTH1 PWM5/LPC2 PWM6/LPC1 PWM7/OCP PWM8/SS VRAMP VREF REFIN REFIN U1 6.19k R37 R30 215k 10 9 8 7 6 5 4 3 2 1 TP44 39 PWM_VID TP36 38 NCP81274 PGOOD CSP8 TP1 14 CSP7 PGOOD 15 VID_BUFF 11 36 EN CSP6 PSI 16 CSP5 EN 17 DRON 12 PSI 37 SCL 35 13 34 SDA CSP4 31 32 FSW DIFF FB COMP 1uF C5 C6 0.1uF 1 PAD CSREF CSSUM CSCOMP ILIM IOUT LLTH/I2C ADD VSP SCL C13 390nF 0.1uF C14 C12 0.1uF C11 0.1uF C10 0.1uF C9 0.1uF C8 0.1uF C7 0.1uF 41 21 22 23 24 25 26 27 28 29 30 TP52 R49 1k 49.9R 680pF R48 C18 C17 1000pF TP53 9.69k R43 68pF 2.2nF C16 C15 J3 10R R38 2.2R 10R SDA 10R VCC_DUT TP54 TP61 TP60 TP55 TP56 TP57 VSN_sense VSP_sense C19 J4 51k TP51 TP58 TP59 47k 33 VCC CSP3 18 R1270R R54 VSN CSP2 19 CSP1 20 R1260R R55 TP50 C21 470pF J1 R17 2k32 SWN7 R152k32 SWN8 R192k32 SWN6 R24 2k32 R50 R51 R1240R R5610k PWM_VID in SWN5 2R202k32 R232k32 SWN4 75k 165k R25 4.32k SWN3 R26 2k32 SWN2 R272k32 SWN1 R39 R1420R 10R R44 10R R40 R143 0R CSN8 CSN7 R42 R145 0R 10R R41 R144 0R CSN6 10R R47 R149 0R 10R R45 R146 0R R147 R0 CSN5 CSN4 R46 R1480R CSN2 www.onsemi.com CSN3 Figure 1. Typical Controller Application Circuit CSN1 RT1 220k 1000pF 2 C20 36pF R1250R R57 26.1k 1 TP45 TP46 TP47 TP48 TP49 NCP81274 VCC_DRV DRON PWMx R133 0R R59 0R R60 0R TP87 C22 4.7uF 4 3 2 1 VCC EN PWM BST U2 PAD 7 8 LG 5 GND 6 SW HG NCP81161 2.2R TP63 C27 0.22uF Q1 www.onsemi.com S2 SW NTMFD4C85N 8 G2 1 G1 2 S1 3 4 9 10 3 7 6 5 TP64 Q6 S2 SW NTMFD4C85N 8 G2 1 G1 2 S1 3 4 9 10 R69 7 6 5 C32 0.1uF TP65 C37 DNP R75 DNP C39 10uF L1 0.22uH C47 10uF C52 10uF R82 330uF 2 2 SHORTPIN 1 R83 SHORTPIN 1 C65 10uF VOUT + C62 C57 10uF SWNx CSNx 330uF + C72 C75 10uF VIN + C92 DNP DNP 56uF + C95 + C82 C85 10uF C102 22uF C107 22uF C112 22uF C117 22uF NCP81274 Figure 2. Typical Phase Application Circuit NCP81274 Table 1. PIN FUNCTION DESCRIPTION Pin Number Pin Name Pin Type 1 REFIN I Reference voltage input for output voltage regulation. 2 VREF O 2.0 V output reference voltage. A 10 nF ceramic capacitor is required to connect this pin to ground. 3 VRMP I Feed-forward input of VIN for the ramp slope compensation. The current fed into this pin is used to control of the ramp of PWM slope. 4 PWM8/SS I/O PWM 8 output/Soft Start setting. During startup it is used to program the soft start time with a resistor to ground. 5 PWM7/OCP I/O PWM 7 output/Per OCP setting. During startup it is used to program the OCP level per phase and latch off time with a resistor to ground. 6 PWM6/LPC1 I/O PWM 6 output/Low phase count 1. During startup it is used to program the power zone (PSI set low) with a resistor to ground. 7 PWM5/LPC2 I/O PWM 5 output/Low phase count 2. During startup it is used to program boot-up power zone (PSI set low) with a resistor to ground. 8 PWM4/PHTH1 I/O PWM 4 output/Phase Shedding Threshold 1. During startup it is used to program the phase shedding threshold 1 (PSI set to mid state) with a resistor to ground. 9 PWM3/PHTH2 I/O PWM 3 output/Phase Shedding Threshold 2. During startup it is used to program the phase shedding threshold 2 (PSI set to mid state) with a resistor to ground. 10 PWM2/PHTH3 I/O PWM 2 output/Phase Shedding Threshold 3. During startup it is used to program the phase shedding threshold 3 (PSI set to mid state) with a resistor to ground. 11 PWM1/PHTH4 I/O PWM 1 output/Phase Shedding Threshold 4. During startup it is used to program the phase shedding threshold 4 (PSI set to mid state) with a resistor to ground. 12 DRON I/O Bidirectional gate driver enable for external drivers. 13 CSP8 I Non-inverting input to current balance sense amplifier for phase 8. Pull-up to VCC to disable the PWM8 output. 14 CSP7 I Non-inverting input to current balance sense amplifier for phase 7. Pull-up to VCC to disable the PWM7 output. 15 CSP6 I Non-inverting input to current balance sense amplifier for phase 6. Pull-up to VCC to disable the PWM6 output. 16 CSP5 I Non-inverting input to current balance sense amplifier for phase 5. Pull-up to VCC to disable the PWM5 output. 17 CSP4 I Non-inverting input to current balance sense amplifier for phase 4. Pull-up to VCC to disable the PWM4 output. 18 CSP3 I Non-inverting input to current balance sense amplifier for phase 3. Pull-up to VCC to disable the PWM3 output. 19 CSP2 I Non-inverting input to current balance sense amplifier for phase 2. Pull-up to VCC to disable the PWM2 output. 20 CSP1 I Non-inverting input to current balance sense amplifier for phase 1. Pull-up to VCC to disable the PWM1 output. 21 CSREF I Total output current sense amplifier reference voltage input. 22 CSSUM I Inverting input of total current sense amplifier. 23 CSCOMP O Output of total current sense amplifier. 24 ILIM O Over current shutdown threshold setting output. The threshold is set by a resistor between ILIM and to CSCOMP pins. 25 IOUT O Total output current. A resistor to GND is required to provide a voltage drop of 2 V at the maximum output current. 26 LLTH/I2C_ADD I Load line selection from 0% to 100% and I2C address pin. 27 FSW I Resistor to ground form this pin sets the operating frequency of the regulator. 28 DIFF O Output of the regulators differential remote sense amplifier. Description www.onsemi.com 4 NCP81274 Table 1. PIN FUNCTION DESCRIPTION (continued) Pin Number Pin Name Pin Type 29 FB I Error amplifier inverting (feedback) input. 30 COMP O Output of the error amplifier and the inverting input of the PWM comparator. 31 VSP I Differential Output Voltage Sense Positive terminal. 32 VSN I Differential Output Voltage Sense Negative terminal. 33 VCC I Power for the internal control circuits. A 1 mF decoupling capacitor is requires from this pin to ground. 34 SDA I/O 35 SCL I Serial Bus clock pin, requires pull-up resistor to VCC. 36 EN I Logic input. Logic high enables regulator output logic low disables regulator output. 37 PSI I Power Saving Interface control pin. This pin can be set low, high or left floating. Use a current limiting resistor of 100 kW when driving the pin with 5 V logic. 38 PGOOD O Open Drain power good indicator. 39 PWM_VID I PWM_VID buffer input. 40 VID_BUFF O PWM_VID pulse output from internal buffer. 41 AGND GND Description Serial Data bi-directional pin, requires pull-up resistor to VCC. Analog ground and thermal pad, connected to system ground. Table 2. MAXIMUM RATINGS Rating Pin Voltage Range (Note 1) Pin Current Range Pin Symbol Min Max Unit VSN GND−0.3 Typ GND + 0.3 V VCC −0.3 6.5 V VRMP −0.3 25 V PWM_VID −0.3 (−2, < 50 ns) VCC + 0.3 V All Other Pins with the exception of the DRON Pin −0.3 VCC + 0.3 V COMP −2 2 mA −1 1 mA CSCOMP DIFF PGOOD VSN Moisture Sensitivity Level MSL 1 − Lead Temperature Soldering Reflow (SMD Styles Only), Pb-Free Versions (Note 2) TSLD 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. All signals referenced to GND unless noted otherwise. 2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 5 NCP81274 Table 3. THERMAL CHARACTERISTICS Rating Symbol Thermal Characteristics, (QFN40, 5 × 5 mm) Thermal Resistance, Junction-to-Air (Note 1) RθJA Operating Junction Temperature Range (Note 2) Min Typ Max Unit °C/W − 68 − TJ −40 − 150 _C Operating Ambient Temperature Range TA −10 − 100 _C Maximum Storage Temperature Range TSTG −55 − 150 _C 1. JESD 51−5 (1S2P Direct-Attach Method) with 0 LFM. 2. JESD 51−7 (1S2P Direct-Attach Method) with 0 LFM. Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −10°C < TA < 100°C; 4.6 V < VCC < 5.4 V; CVCC = 0.1 mF) Parameter Test Conditions Symbol Min VRMP 4.5 Typ Max Unit 20 V 4.2 V VRMP Supply Range UVLO VRMP Rising VRMPrise VRMP Falling VRMPfall VRMP UVLO Hysteresis 3 VRMPhyst V 800 mV BIAS SUPPLY VCC Supply Voltage Range VCC Quiescent current UVLO Threshold Enable Low 4.6 5.4 40 ICC V mA 8 Phase Operation 50 mA 1 Phase-DCM Operation 10 mA VCC Rising UVLORise VCC Falling UVLOFall VCC UVLO Hysteresis 4.5 4 UVLOHyst V V 200 mV SWITCHING FREQUENCY Switching Frequency Range 8 Phase Configuration Switching Frequency Accuracy FSW = 810 kHz FSW 250 1200 kHz DFSW −4 +4 % 1.0 mA ENABLE INPUT Input Leakage IL −1.0 Upper Threshold EN = 0 V or VCC VIH 1.2 Lower Threshold VIL V 0.6 V DRON Output High Voltage Sourcing 500 mA VOH Output Low Voltage Sinking 500 mA VOL Rise Time Cl(PCB) = 20 pF, DVO = 10% to 90% tR 160 ns Fall Time Cl(PCB) = 20 pF, DVO = 10% to 90% tF 3 ns RPULL−UP 2.0 kW RPULL_DOWN 70 kW Internal Pull-up Resistance Internal Pull-down Resistance VCC = 0 V www.onsemi.com 6 3.0 V 0.1 V NCP81274 Table 4. ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise stated: −10°C < TA < 100°C; 4.6 V < VCC < 5.4 V; CVCC = 0.1 mF) Parameter Test Conditions Symbol Min Typ Max Unit VOL 0.4 V IL 0.2 mA T_init 1.5 ms PGOOD Output Low Voltage IPGOOD = 10 mA (Sink) Leakage Current PGOOD = 5 V Output Voltage Initialization Time Minimum Output Voltage Ramp Time T_rampMIN 0.15 ms Maximum Output Voltage Ramp Time T_rampMAX 10 ms UVP 300 mV TUVP 5 ms OVP 400 mV TOVP 5 ms PROTECTION-OCP, OVP, UVP Under Voltage Protection (UVP) Threshold Relative to REFIN Voltage Under Voltage Protection (UVP) Delay Over Voltage Protection (OVP) Threshold Relative to REFIN Voltage Over Voltage Protection (OVP) Delay PWM OUTPUTS Output High Voltage Sourcing 500 mA Output Mid Voltage VOH VCC − 0.2 VMID 1.9 Output Low Voltage Sinking 500 mA VOL Rise and Fall Time CL(PCB) = 50 pF, DVO = 10% to 90% of VCC tR, tF Tri-state Output Leakage Gx = 2.0 V, x = 1−8, EN = Low Minimum On Time FSW = 600 kHz 0% Duty Cycle IL V 2.0 2.1 V 0.7 V 10 −1.0 ns 1.0 mA Ton 12 ns Comp Voltage when PWM Outputs Remain LOW VCOMP0% 1.3 V 100% Duty Cycle Comp Voltage when PWM Outputs Remain HIGH VCOMP100% 2.5 V PWM Phase Angle Error Between Adjacent Phases ø ±15 ° PHASE DETECTION Phase Detection Threshold Voltage CSP2 to CSP8 VPHDET Phase Detect Timer CSP2 to CSP8 TPHDET VCC − 0.1 1.1 V ms ERROR AMPLIFIER IBIAS Input Bias Current −400 400 nA Open Loop DC Gain CL = 20 pF to GND, RL = 10 kW to GND GOL 80 dB Open Loop Unity Gain Bandwidth CL = 20 pF to GND, RL = 10 kW to GND GBW 20 MHz Slew Rate DVIN = 100 mV, G = −10 V/V, DVOUT = 0.75–1.52 V, CL = 20 pF to GND, RL = 10 kW to GND SR 5 V/ms Maximum Output Voltage ISOURCE = 2 mA VOUT Minimum Output Voltage ISINK = 2 mA VOUT www.onsemi.com 7 3.5 V 1 V NCP81274 Table 4. ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise stated: −10°C < TA < 100°C; 4.6 V < VCC < 5.4 V; CVCC = 0.1 mF) Parameter Test Conditions Symbol Min Input Bias Current IBIAS VSP Input Voltage VIN VIN −0.3 Typ Max Unit −400 400 nA 0 2 V DIFFERENTIAL SUMMING AMPLIFIER VSN Input Voltage −3dB Bandwidth CL = 20 pF to GND, RL = 10 kW to GND Closed Loop DC Gain (VSP−VSN to DIFF) VSP to VSN = 0.5 to 1.3 V Droop accuracy CSREF − DROOP = 80 mV, VREFIN = 0.8 V to 1.2 V Maximum Output Voltage Minimum Output Voltage 0.3 V BW 12 MHz G 1 V/V DDROOP 78 ISOURCE = 2 mA VOUT 3 ISINK = 2 mA VOUT 82 mV V 0.8 V CURRENT SUMMING AMPLIFIER Offset Voltage Input Bias Current CSSUM = CSREF = 1 V Open Loop Gain VOS −500 500 mV IL −7.5 7.5 mA G 80 dB Current sense Unity Gain Bandwidth CL = 20 pF to GND, RL = 10 kW to GND GBW 10 MHz Maximum CSCOMP Output Voltage ISOURCE = 2 mA VOUT Minimum CSCOMP Output Voltage ISINK = 2 mA 3.5 V VOUT 0.1 V CURRENT BALANCE AMPLIFIER Input Bias Current CSPX − CSPX+1 = 1.2 V IBIAS −50 50 nA Common Mode Input Voltage Range CSPX = CSREF VCM 0 2 V Differential Mode Input Voltage Range CSREF = 1.2 V VDIFF −100 100 mV Closed Loop Input Offset Voltage Matching CSPX = 1.2 V, Measured from the Average −1.5 1.5 mV Current Sense Amplifier Gain 0 V < CSPX < 0.1 V Multiphase Current Sense Gain Matching CSREF = CSP = 10 mV to 30 mV −3dB Bandwidth G 5.7 DG −3 BW 6.0 V/V 3 8 % MHz IOUT Input Reference Offset Voltage ILIM to CSREF VOS Output Current Max ILIM Sink Current 20 mA IOUT Current Gain IOUT/ILIM, RLIM = 20 kW, RIOUT = 5 kW −3 +3 mV mA 200 G 9.5 10 10.5 A/A VREF 1.98 2 2.02 V VOLTAGE REFERENCE VREF Reference Voltage IREF = 1 mA VREF Reference accuracy TJMIN < TJ < TJMAX DVREF www.onsemi.com 8 1 % NCP81274 Table 4. ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise stated: −10°C < TA < 100°C; 4.6 V < VCC < 5.4 V; CVCC = 0.1 mF) Parameter Test Conditions Symbol Min VIH 1.45 VMID 0.8 Typ Max Unit PSI PSI High Threshold PSI Mid threshold PSI Low threshold PSI Input Leakage Current V 1 VIL VPSI = 0 V IL −1 Upper Threshold VIH 1.21 Lower Threshold VIL V 0.575 V 1 mA PWM_VID BUFFER PWM_VID Switching Frequency FPWM_VID Output Rise Time 400 tR Output Fall Time V 0.575 V 5000 kHz 3 ns tF 3 ns Rising and Falling Edge Delay Dt = tR − tF Dt 0.5 ns Propagation Delay tPD = tPDHL = tPDLH tPD 8 ns Propagation Delay Error DtPD = tPDHL − tPDLH DtPD 0.5 ns REFIN Discharge Switch ON-Resistance IREEFIN(SINK) = 2 mA RDISCH 10 W Ratio of Output Voltage Ripple Transferred from REFIN/REFIN Voltage Ripple FPWM_VID = 400 kHz, FSW ≤ 600 kHz VORP/VREFIN 10 % FPWM_VID = 1000 kHz, FSW ≤ 600 kHz VORP/VREFIN 30 REFIN I2C Logic High Input Voltage VIH Logic Low Input Voltage VIL 1.7 0.5 Hysteresis (Note 4) Output Low Voltage 80 ISDA = −6 mA VOL Input Current IL Input Capacitance (Note 4) Clock Frequency V −1 CSDA, CSCL SCL Low Period (Note 4) tLOW 1.3 SCL High Period (Note 4) tHIGH 0.6 SCL/SDA Rise Time (Note 4) 0.4 V 1 mA 400 kHz 5 fSCL See Figure 3 tR V mV pF ms ms 300 ns 300 ns SCL/SDA Fall Time (Note 4) tF Start Condition Setup Time (Note 4) tSU;STA 600 ns Start Condition Hold Time (Note 1, 4) tHD;STA 600 ns Data Setup Time (Note 2, 4) tSU;DAT 100 ns Data Hold Time (Note 2, 4) tHD;DAT 300 ns Stop Condition Setup Time (Note 3, 4) tSU;STO 600 ns tBUF 1.3 ms Bus Free Time between Stop and Start (Note 4) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Time from 10% of SDA to 90% of SCL. 2. Time from 10% or 90%of SDA to 10% of SCL. 3. Time from 90% of SCL to 10% of SDA. 4. Guaranteed by design, not production tested. www.onsemi.com 9 NCP81274 tR tLOW tF tHD:STA SCLK tHIGH tHD:STA tHD:DAT tSU:STA tSU:STO tSU:DAT SDATA tBUF STOP START START STOP Figure 3. I2C Timing Diagram EN VOUT PGOOD T_ramp T_init Figure 4. Soft Start Timing Diagram Applications Information between the sensed voltage and the REFIN pin average voltage will change the PWM outputs duty cycle until the two voltages are identical. The load current is current is continuously monitored on each phase and the PWM outputs are adjusted to ensure adjusted to ensure even distribution of the load current across all phases. In addition, the total load current is internally measured and used to implement a programmable adaptive voltage positioning mechanism. The device incorporates overcurrent, under and overvoltage protections against system faults. The communication between the NCP81274 and the user is handled with two interfaces, PWM_VID to set the output voltage and I2C to configure or monitor the status of the controller. The operation of the internal blocks of the device is described in more details in the following sections. The NCP81274 is a buck converter controller optimized for the next generation computing and graphic processor applications. It contains eight PWM channels which can be individually configured to accommodate buck converter configurations up to eight phases. The controller regulates the output voltage all the way down to 0 V with no load. Also, the device is functional with VRMP voltages as low as 3.3 V. The output voltage is set by applying a PWM signal to the PWM_VID input of the device. The controller converts the PWM_VID signal with variable high and low levels into a constant amplitude PWM signal which is then applied to the REFIN pin. The device calculates the average value of this PWM signal and sets the regulated voltage accordingly. The output voltage is differentially sensed and subtracted from the REFIN average value. The result is biased up to 1.3 V and applied to the error amplifier. Any difference www.onsemi.com 10 NCP81274 VID_BUFF VREF VCC REF EN UVLO & EN PWM_VID 1.3V EN + S VSP − S VSN DIFFOUT EN PGOOD PGOOD Comparator VSP VSN LLTH REFIN Soft start LLTH − FB CSCOMP + OVP 1.3V VSP + CSREF − CSSUM VSN COMP OVP ILIM Total Output Current Measurment , ILIM & OCP PSI OCP Mux Data Registers SDA SCL FSW IPH1 IPH2 IPH3 IPH4 IPH5 IPH6 IPH7 IPH8 Control Interface FSW VRMP IOUT PWM1 to PWM8 LLTH/I2C_ADD CSP1 to CSP8 ADC IOUT Ramp Generators PWM Generators CSP7 CSP8 Power State Stage PWM1/PHTH4 PWM2/PHTH3 PWM3/PHTH2 PWM4/PHTH1 PWM5/LPC2 PWM6/LPC1 PWM7/OCP PWM8/SS DRON EN OCP OVP PSI Ramp1 Ramp2 Ramp3 Ramp4 Ramp5 Ramp6 Ramp7 Ramp8 Current Balance Amplifiers and per Phase OCP Comparators CSP1 CSP2 CSP3 CSP4 CSP5 CSP6 GND LLTH/I2C_ADD Figure 5. NCP81274 Functional Block Diagram www.onsemi.com 11 NCP81274 PWM_VID Interface The output voltage ramp-up time is user settable by connecting a resistor between pin PWM8/SS and GND. The controller will measure the resistance value at power-up by sourcing a 10 mA current through this resistor and set the ramp time (tramp) as shown in Table 16. PWM_VID is a single wire dynamic voltage control interface where the regulated voltage is set by the duty cycle of the PWM signal applied to the controller. The device controller converts the variable amplitude PWM signal into a constant 2 V amplitude PWM signal while preserving the duty cycle information of the input signal. In addition, if the PWM_VID input is left floating, the VID_BUFF output is tri-stated (floating). The constant amplitude PWM signal is then connected to the REFIN pin through a scaling and filtering network (see Figure 6). This network allows the user to set the minimum and maximum REFIN voltages corresponding to 0% and 100% duty cycle values. Remote Voltage Sense A high performance true differential amplifier allows the controller to measure the output voltage directly at the load using the VSP (VOUT) and VSN (GND) pins. This keeps the ground potential differences between the local controller ground and the load ground reference point from affecting regulation of the load. The output voltage of the differential amplifier is set by the following equation: V DIFOUT + ǒV VSP * V VSNǓ ) ǒ1.3 V * V REFINǓ ) VCC Internal precision reference VREF = 2 V ) ǒV DROOP ) V CSREFǓ 0.1 mF VREF R1 10nF R2 C1 Where: VDIFOUT is the output voltage of the differential amplifier. VVSP − VVSN is the regulated output voltage sensed at the load. VREFIN is the voltage at the output pin set by the PWM_VID interface. VDROOP − VCSREF is the expected drop in the regulated voltage as a function of the load current (load-line). 1.3 V is an internal reference voltage used to bias the amplifier inputs to allow both positive and negative output voltage for VDIFOUT. VID_BUFF PWM_VID GND R3 REFIN Controller Figure 6. PWM_VID Interface The minimum (0% duty cycle), maximum (100% duty cycle) and boot (PWM_VID input floating) voltages can be calculated with the following formulas: 1 R 1@R 3 V MAX + V REF @ 1) 1) Error Amplifier A high performance wide bandwidth error amplifier is provided for fast response to transient load events. Its inverting input is biased internally with the same 1.3 V reference voltage as the one used by the differential sense amplifier to ensure that both positive and negative error voltages are correctly handled. An external compensation circuit should be used (usually type III) to ensure that the control loop is stable and has adequate response. (eq. 1) R 2@ǒR 1)R 3Ǔ 1 V MIN + V REF @ R 1@ǒR 2)R 3Ǔ V BOOT + V REF @ (eq. 2) R 2@R 3 1 1) R1 (eq. 4) (eq. 3) Ramp Feed-Forward Circuit R2 The ramp generator circuit provides the ramp used to generate the PWM signals using internal comparators (see Figure 7) The ramp generator provides voltage feed-forward control by varying the ramp magnitude with respect to the VRMP pin voltage. The PWM ramp time is changed according to the following equation: Soft Start Soft start is defined as the transition from Enable assertion high to the assertion of Power good as shown in Figure 4. The output is set to the desired voltage in two steps, a fixed initialization step of 1.5 ms followed by a ramp-up step where the output voltage is ramped to the final value set by the PWM_VID interface. During the soft start phase, PGOOD pin is initially set low and will be set high when the output voltage is within regulation and the soft start ramp is complete. The PGOOD signal only de-asserts (pull low) when the controller shuts down due to a fault condition (UVLO, OVP or OCP event). V RAMPpk+pk pp + 0.1 @ V VRMP (eq. 5) The VRMP pin also has a UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin is high impedance input when the controller is disabled. www.onsemi.com 12 NCP81274 When PSI = Low, the controller is set to a fixed power zone regardless of the load current. The LPC2 setting controls the power zone used during boot-up (after EN is set high) while the LPC1 configuration sets the power zone during normal operation. If PSI = Low during power-up, the configuration set by LPC1 is activated only after PSI leaves the low state (set to Mid or High) and set again to the low state. VIN Vramp_pp Comp-IL Duty Figure 7. Ramp Feed-Forward Circuit PWM Output Configuration By default the controller operates in 8 phase mode, however with the use of the CSP pins the phases can be disabled by connecting the CSP pin to VCC. At power-up the NCP81274 measures the voltage present at each CSP pin and compares it with the phase detection threshold. If the voltage exceeds the threshold, the phase is disabled. The phase configurations that can be achieved by the device are listed in Table 6. The active phase (PWMX) information is also available to the user in the phase status register. LLTH/I2C_ADD The LLTH/I2C_ADD pin enables the user to change the percentage of the externally programmed droop that takes effect on the output. In addition, the LLTH/I2C_ADD pin sets the I2C slave address of the NCP81274. The maximum load line is controlled externally by setting the gain of the current sense amplifier. On power up a 10 mA current is sourced from the LLTH/I2C_ADD pin through a resistor and the resulting voltage is measured. The load line and I2C slave address configurations achievable using the external resistor is listed in the table below. The percentage load line can be fine-tuned over the I2C interface by writing to the LL configuration register. PSI, LPCX, PHTHX The NCP81274 incorporates a power saving interface (PSI) to maximize the efficiency of the regulator under various loading conditions. The device supports up to six distinct operation modes, called power zones using the PSI, LPCX and PHTHX pins (see Table 7). At power-up the controller reads the PSI pin logic state and sources a 10 mA current through the resistors connected to the LPCX and PHTHX pins, measures the voltage at these pins and configures the device accordingly. The configuration can be changed by the user by writing to the LPCX and PHTHX configuration registers. After EN is set high, the NCP81274 ignores any change in the PSI pin logic state until the output voltage reaches the nominal regulated voltage. When PSI = High, the controller operates with all active phases enabled regardless of the load current. If PSI = Mid, the NCP81274 operates in dynamic phase shedding mode where the voltage present at the IOUT pin (the total load current) is measured every 10 ms and compared to the PHTHX thresholds to determine the appropriate power zone. The resistors connected between the PHTHX and GND should be picked to ensure that a 10 mA current will match the voltage drop at the IOUT pin at the desired load current. Please note that the maximum allowable voltage at the IOUT pin at the maximum load current is 2 V. Any PHTHX threshold can be disabled if the voltage drop across the PHTHX resistor is ≥ 2 V for a 10 mA current, the pin is left floating or 0xFF is written to the appropriate PHTHX configuration register. At power-up, the automatic phase shedding mode is only enabled after the output voltage reaches the nominal regulated voltage. Table 5. LLTH/I2C_ADD PIN SETTING Resistor (kW) Load Time (%) Slave Address (Hex) 10 100 0x20 23.2 0 0x20 37.4 100 0x30 54.9 0 0x30 78.7 100 0x40 110 0 0x40 147 100 0x50 249 0 0x50 NOTE: www.onsemi.com 13 1% tolerance. NCP81274 Table 6. PWM OUTPUT CONFIGURATION CSP Pin Configuration (3 = Normal Connection, X = Tied to VCC) Configuration Phase Configuration CSP1 CSP2 CSP3 CSP4 CSP5 CSP6 CSP7 CSP8 Enabled PWM Outputs (PWMX Pins) 1 8 Phase 3 3 3 3 3 3 3 3 1, 2, 3, 4, 5, 6, 7, 8 2 7 Phase 3 3 3 3 3 3 3 X 1, 2, 3, 4, 5, 6, 7 3 6 Phase 3 3 3 3 3 3 X X 1, 2, 3, 4, 5, 6 4 5 Phase 3 3 3 3 3 X X X 1, 2, 3, 4, 5 5 4 Phase 3 3 3 3 X X X X 1, 2, 3, 4 6 3 Phase 3 3 3 X X X X X 1, 2, 3 7 2 Phase 3 3 X X X X X X 1, 2 8 1 Phase 3 X X X X X X X 1 Table 7. PSI, LPCX, PHTHX CONFIGURATION (Note 1) Power Zone (Note 2) PSI Logic State LPCX Resistor (kW) IOUT vs. PHTHX Comparison 8 Phase 7 Phase 6 Phase 5 Phase 4 Phase 3 Phase 2 Phase 1 Phase High Disabled Function Disabled 0 0 0 0 0 0 0 0 Low 10 0 0 0 0 0 0 0 0 23.2 1 0 0 0 0 0 0 0 37.4 2 0 2 0 2 0 0 0 54.9 3 3 3 3 3 3 3 0 78.7 Mid Function Disabled 4 4 4 4 4 4 4 4 IOUT > PHTH4 0 0 0 0 0 0 0 0 PTHT4 > IOUT > PHTH3 1 0 0 0 0 0 0 0 PHTH3 > IOUT > PHTH2 2 0 2 0 2 0 0 0 PHTH2 > IOUT > PHTH1 3 3 3 3 3 3 3 0 IOUT < PHTH1 4 4 4 4 4 4 4 4 1. 1% tolerance. 2. Power zone 4 is DCM @100 kHz switching frequency, while zones 0 to 3 are CCM. Table 8. PHASE SHEDDING CONFIGURATIONS PWM Output Status (3 = Enabled, X = Disabled) Power Zone PWM Output Configuration PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 0 8 Phase 3 3 3 3 3 3 3 3 1 3 X 3 X 3 X 3 X 2 3 X X X 3 X X X 3 3 X X X X X X X 3 X X X X X X X 3 3 3 3 3 3 3 X 3 X X X X X X X 4 0 7 Phase 3 3 X X X X X X X 3 3 3 3 3 3 X X 2 3 X 3 X 3 X X X 3 3 X X X X X X X 4 3 X X X X X X X 4 0 6 Phase www.onsemi.com 14 NCP81274 Table 8. PHASE SHEDDING CONFIGURATIONS (continued) PWM Output Status (3 = Enabled, X = Disabled) Power Zone PWM Output Configuration PWM1 0 5 Phase 3 3 3 3 3 X X X 3 3 X X X X X X X 4 3 X X X X X X X 3 3 3 3 X X X X 2 3 X 3 X X X X X 3 3 X X X X X X X 0 4 Phase PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 3 X X X X X X X 3 3 3 X X X X X 3 X X X X X X X 3 X X X X X X X 3 3 X X X X X X 3 3 X X X X X X X 4 3 X X X X X X X 3 X X X X X X X 3 X X X X X X X 4 0 3 Phase 3 4 0 0 2 Phase 1 Phase 4 Power Zone Transition/Phase Shedding When PSI = Low and the user requires to change the power zone, the transition to the new power zone is identical to the transition process used when PSI is set to the Mid-state. The only exception is when the target power zone is disabled in automatic phase shedding mode. In this case, the controller will automatically enable the target power zone and allow the transition. When the controller is set to automatic phase shedding, the power zone will be automatically disabled. The power zones supported by the NCP81274 are set by the resistors connected to the LPCX pins (PSI = Low) or PHTHX pins (PSI = Mid). When PSI is set to the Mid-state, the NCP81274 employs a phase shedding scheme where the power zone is automatically adjusted for optimal efficiency by continuously measuring the total output current (voltage at the IOUT pin) and compare it with the PHTHX thresholds. When the comparison result indicates that a lower power zone number is required (an increase in the IOUT value), the controller jumps to the required power zone immediately. A decrease in IOUT that indicates that the controller needs to switch into a higher power zone number, the transition will be executed with a delay of 200 ms set by the phase shed delay configuration register. The value of the delay can be adjusted by the user in steps of 10 ms if required. To avoid excessive ripple on the output voltage, all power zone changes are gradual and include all intermediate power zones between the current zone and the target zone set by the comparison of the output current with the PHTHX thresholds, each transition introducing a programmable 200 ms delay. To avoid false changes from one power zone to another caused by noise or short IOUT transients, the comparison between IOUT and PHTHX threshold uses hysteresis. The switch to a lower power zone is executed if IOUT exceeds the PHTHX threshold values while a transition to a higher power zone number is only executed if IOUT is below PHTHX-Hysteresis value. The hysteresis value is set to 0x10h and can be changed by the user by writing to the phase shedding configuration register. If a power zone/PHTHX threshold is disabled, the controller will skip it during the power zone transition process. Switching Frequency A programmable precision oscillator is provided. The clock oscillator serves as the master clock to the ramp generator circuit. This oscillator is programmed by a resistor to ground on the FSW pin. The FSW pin provides approximately 2 V out and the source current is mirrored into the internal ramp oscillator. The oscillator frequency is approximately proportional to the current flowing in the resistor. Table 19 lists the switching frequencies that can be set using discrete resistor values for each phase configuration. Also, the switching frequency information is available in the FSW configuration register and it can be changed by the user by writing to the FSW configuration register. Total Current Sense Amplifier The controller uses a patented approach to sum the phase currents into a single temperature compensated total current signal (Figure 8). This signal is then used to generate the output voltage droop, total current limit, and the output current monitoring functions. The total current signal is floating with respect to CSREF. The current signal is the difference between www.onsemi.com 15 NCP81274 100% current limit trips if the ILIMIT sink current exceeds 10 mA for 50 ms. The 150% current limit trips with minimal delay if the ILIMIT sink current exceeds 15 mA. Set the value of the current limit resistor based on the CSCOMP−CSREF voltage as shown below. CSCOMP and CSREF. The REF(n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground. The amplifier actively filters and gains up the voltage applied across the inductors to recover the voltage drop across the inductor series resistance (DCR). RTH is placed near an inductor to sense the temperature of the inductor. This allows the filter time constant and gain to be a function of the NTC’s resistance (RTH) and compensate for the change in the DCR with temperature. The DC gain equation for the current sensing: RILIM + 10 mA (eq. 8) or (eq. 6) RCS1@RTH RCS1)RTH @ I OUT @ DCR Total RPH RILIM + RCS2 ) V CSCOMP*CSREF + * V CSCOMP*CSREF@ILIMIT RCS1@RTH RCS2) RCS1)RTH @ I OUT @ DCR RPH LIMIT 10 mA (eq. 9) Programming DROOP VCC The signals CSCOMP and CSREF are differentially summed with the output voltage feedback to add precision voltage droop to the output voltage. Controller CSN1 RREF1 CREF 1:10 Droop + DCR @ CSN8 RREF8 SWN1 + CSREF − SWN8 RPH8 − RCS2 CSCOMP RCS1 ILIM RILIM IOUT RIMON R IOUT + RTH Figure 8. Total Current Summing Amplifier Set the gain by adjusting the value of the RPH resistors. The DC gain should be set to the output voltage droop. If the voltage from CSCOMP to CSREF is less than 100 mV at the maximum output current IOUTMAX then it is recommend increasing the gain of the CSCOMP amp. This is required to provide a good current signal to offset voltage ratio for the ILIMIT pin. The NTC should be placed near the inductor used by phase 1. The output voltage droop should be set with the droop filter divider. The pole frequency in the CSCOMP filter should be set equal to the zero from the output inductor. This allows the circuit to recover the inductor DCR voltage drop current signal. It is best to fine tune this filter during transient testing. FZ + DCR@25C 2 @ p @ L Phase (eq. 10) The IOUT pin sources a current in proportion to the ILIMIT sink current. The voltage on the IOUT pin is monitored by the internal A/D converter and should be scaled with an external resistor to ground such that a load equal to system max current generates a 2 V signal on IOUT. A pull-up resistor to VCC can be used to offset the IOUT signal positive if needed. + CCS RPH Programming IOUT RPH1 CSSUM ǒRCS1 ø RTHǓ ) RCS2 2.0 V @ RILIM RCS1@RTH RCS2) RCS1)RTH @ I OUT @ DCR 10 @ MAX RPH (eq. 11) PROTECTIONS OCP The device incorporates an over current protection mechanism to shut down and latch off to protect against damage due to an over current event. The current limit threshold set by the ILIM pin on a full system basis. The current limit thresholds are programmed with a resistor between the ILIMIT and CSCOMP pins. The ILIMIT pin mirrors the voltage at the CSREF pin and mirrors the sink current internally to IOUT (reduced by the IOUT Current Gain) and the current limit comparators. Set the value of the current limit resistor based on the CSCOMP−CSREF voltage as shown in the Programming the Current Limit ILIM section. In addition to the total current protection, the device incorporates an OCP function on a per phase basis by continuously monitoring the CSPX−CSREF voltage. The per-phase OCP limit is selected on startup when a 10 mA current is sourced from the PWM6/OCP. The resulting voltage read on the pin selects both the max per phase current and delay time (see Table 9). These can also be programmed over I2C (see Table 17). (eq. 7) Programming the Current Limit ILIM The current limit thresholds are programmed with a resistor between the ILIMIT and CSCOMP pins. The ILIMIT pin mirrors the voltage at the CSREF pin and mirrors the sink current internally to IOUT (reduced by the IOUT Current Gain) and the current limit comparators. The www.onsemi.com 16 NCP81274 peripherals connected to the serial bus respond to the START condition, and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit, which determines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge Bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master will write to the slave device. If the R/W bit is a 1, the master will read from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an Acknowledge Bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a STOP signal. The number of data bytes that can be transmitted over the serial bus in a single READ or WRITE operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will override the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a STOP condition. 4. Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. To write data to one of the device data registers or read data from it, the Address Pointer Register must be set so that the correct data register is addressed, and then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the Address Pointer Register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. The device address is sent over the bus followed by R/W set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the Address Pointer Register. The second data byte is the data to be written to the internal data register. Table 9. PER PHASE OCP SETTINGS Resistance (kW) Per Phase Voltage (mV) Latch Off Delay (ms) 10 65 4 14.7 75 4 20 100 4 26.1 134 4 33.2 65 6 41.2 75 6 49.9 100 6 60.4 134 6 71.5 65 8 84.5 75 8 100 100 8 NOTE: 118.3 134 8 136.6 65 10 157.7 75 10 182.1 100 10 249 134 10 1% tolerance. Under Voltage Lock-Out (VCC UVLO) VCC is constantly monitored for the under voltage lockout (UVLO) During power up both the VRMP and the VCC pin are monitored Only after both pins exceed their individual UVLO threshold will the full circuit be activated and ready for the soft start ramp. Over Voltage Protection An output voltage monitor is incorporated into the controller. During normal operation, if the output voltage is 400 mV over the REFIN value, the PGOOD pin will go low, the DRON will assert low and the PWM outputs are set low. The limit will be clamped at 2 V if REFIN is driven above 2 V. The outputs will remain disabled until the power is cycled or the EN pin is toggled. I2C Interface The controller is connected to this bus as a slave device, under the control of a master controller. Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high might be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line, SCL, remains high. This indicates that an address/data stream will follow. All slave www.onsemi.com 17 NCP81274 READ A SINGLE WORD bit R/W which is Read for this case. Controller acknowledges it by an ACK signal on the bus. This will start the read operation and controller sends the high byte of the register on the bus. Master reads the high byte and asserts an ACK on the SDA line. Controller now sends the low byte of the register on the SDA line. The master acknowledges it by a no acknowledge NACK on the SDA line. The master then asserts the stop condition to end the transaction. The master device asserts the start condition. The master then sends the 7-bit slave address. It is followed by a R/W bit that indicates the direction of operation, which will be a write operation in this case. The slave whose address is on the bus acknowledges it by an ACK signal on the bus (by holding SDA line low). The master then sends register address on the bus. The slave device accepts it by an ACK. The master then asserts a repeated start condition followed by a 7-bit slave address. The master then sends a direction S Slave Address 0 ACK Register Address ACK Sr Slave Address 1 ACK Register Data NACK P = Generated by the Master S = Start Condition Sr = Repeated Start Condition = Generated by the Slave P = Stop Condition ACK/NACK = Acknowledge/No Acknowledge Figure 9. Single Register Read Operation READING THE SAME REGISTERS MULTIPLE TIMES 1. The slave device sends the high byte of the register on the bus. 2. The master reads the high byte and asserts an ACK on the SDA line. 3. The slave device now sends the low byte of the register on the SDA line. 4. The master acknowledges it by an ACK signal on the SDA line. 5. The master and slave device keeps on repeating steps 1−4 until the low byte of the last reading is transferred. After receiving the low byte of the last register, the master asserts a not acknowledge NACK on the SDA. The master then asserts a stop condition to end the transaction. The master device asserts the start condition. The master then sends the 7-bit slave address. It is followed by a R/W bit that indicates the direction of operation, which will be a write operation in this case. The slave whose address is on the bus acknowledges it by an ACK signal on the bus (holding SDA line low). The master then sends register address on the bus. The slave device accepts it by an ACK. The master then asserts a repeated start condition followed by a 7-bit slave address. The master then sends a direction bit R/W which is Read for this case. Slave device acknowledges it by an ACK signal on the bus. This will start the read operation: S Slave Address 0 ACK Register Address ACK Sr Slave Address 1 ACK RD1 ACK RD2 ACK = Generated by the Master S = Start Condition Sr = Repeated Start Condition = Generated by the Slave P = Stop Condition ACK/NACK = Acknowledge/No Acknowledge Figure 10. Multiple Register Read Operation www.onsemi.com 18 RDN NACK P RD1…N = Register Data 1…N NCP81274 WRITING A SINGLE WORD The master device asserts the start condition. The master then sends the 7-bit to the slave address. It is followed by a R/W bit that indicates the direction of operation, which will be a write operation in this case. The slave whose address is on the bus acknowledges it by an ACK signal on the bus (by holding SDA line low). The master then sends register address on the bus. The slave device accepts it by an ACK. S Slave Address 0 ACK The master then sends a data byte of the high byte of the register. The slave device asserts an acknowledge ACK on the SDA line. The master then sends a data byte of the low byte of the register. The slave device asserts an acknowledge ACK on the SDA line. The master asserts a stop condition to end the transaction. Register Address ACK = Generated by the Master S = Start Condition = Generated by the Slave P = Stop Condition Register Data ACK P ACK = Acknowledge Figure 11. Single Register Write Operation WRITING MULTIPLE WORDS TO DIFFERENT REGISTERS The master then sends the second register address on the bus. The slave device accepts it by an ACK. The master then sends a data byte of the high byte of the second register. The slave device asserts an acknowledge ACK on the SDA line. The master then sends a data byte of the low byte of the second register. The slave device asserts an acknowledge ACK on the SDA line. A complete word must be written to a register for proper operation. It means that both high and low bytes must be written. The master device asserts the start condition. The master then sends the 7-bit slave address. It is followed by a bit (R/W) that indicates the direction of operation, which will be a write operation in this case. The slave whose address is on the bus acknowledges it by an ACK signal on the bus (by holding SDA line low). The master then sends first register address on the bus. The slave device accepts it by an ACK. The master then sends a data byte of the high byte of the first register. The slave device asserts an acknowledge ACK on the SDA line. The master then sends a data byte of the low byte of the first register. The slave device asserts an acknowledge ACK on the SDA line. S Slave Address 0 ACK RA1 ACK RD1 ACK RA2 ACK RD2 ACK = Generated by the Master S = Start Condition RA1…N = Register Address 1…N = Generated by the Slave P = Stop Condition RD1…N = Register Data 1…N Figure 12. Multiple Register Write Operation www.onsemi.com 19 RAN ACK RDN ACK ACK = Acknowledge P NCP81274 Table 10. REGISTER MAP Address R/W Default Value 0x20 R/W 0xFF IOUT_OC_WARN_LIMIT 0x21 R 0x00 STATUS BYTE 0x22 R/W 0x00 Fault Mask 0x23 R 0x00 STATUS Fault 0x24 R 0x00 STATUS Warning 0x26 R 0x00 READ_IOUT 0x27 R 0x1A MFR_ID 0x28 R 0x74 MFR_MODEL 0x29 R 0x04 MFR_REVISION 0x2A R/W 0x00 Lock/Reset 0x2B R 0x00 Soft Start Status 0x2C N/A 0x00 Reserved 0x2D R 0x2E R/W 0x2F R 0x30 R/W 0x00 Switching Frequency Configuration 0x31 N/A 0x00 Reserved 0x32 R PSI Status 0x33 R Phase Status 0x34 R/W 0x35 R 0x36 R/W 0x38 R 0x39 R/W 0x03 LL Configuration 0x3A RW 0x00 PHTH1 Configuration 0x3B R 0x3C R/W Description OCP Status 0x00 OCP Configuration Switching Frequency Status 0x1F LPC_Zone_enable LPC Status 0x00 LPC Configuration LL Status PHTH1 Status 0x00 PHTH2 Configuration 0x3D R 0x3E R/W PHTH2 Status 0x3F R 0x40 R/W 0x41 R 0x44 R/W 0x08 Phase Shedding Hysteresis 0x45 R/W 0x14 Phase Shedding Delay 0x46 R/W 0x00 Second Function Configuration Register Latch A 0x47 R/W 0x00 Second Function Configuration Register Latch B 0x48 N/A N/A Reserved 0x49 N/A N/A Reserved 0x4A N/A N/A Reserved 0x4B N/A N/A Reserved 0x4C N/A N/A Reserved 0x00 PHTH3 Configuration PHTH3 Status 0x00 PHTH4 Configuration PHTH4 Status www.onsemi.com 20 NCP81274 IOUT_OC_WARN_LIMIT Register (0x20) STATUS Fault Register (0x23) This sets the high current limit. Once the READ_IOUT register value exceeds this limit IOUT_OC_WARN_LIMIT bit is set in the Status Warning register and an ALERT is generated. Table 13. STATUS FAULT REGISTER SETTINGS STATUS BYTE Register (0x21) Bits Name 7:5 Reserved 4 Clim1 This bit gets set when IOUT exceeds the ILIM value and its corresponding bit from the fault mask register is cleared. 3 Clim2 This bit gets set when IOUT exceeds the ILIM value and its corresponding bit from the fault mask register is cleared. 2 Clim_phase This bit gets set when the phase Current (VCSN−VCSREF) exceeds the OCP configuration value and its corresponding bit from the fault mask register is cleared. 1 OVP This bit is set when an OVP event is detected and its corresponding bit from the fault mask register is cleared. 0 UVP This bit is set when an UVP event is detected and its corresponding bit from the fault mask register is cleared. Table 11. STATUS BYTE REGISTER SETTINGS Bits Name 7:6 Reserved N/A Description 5 VOUT_OV This bit gets set whenever the NCP81274 goes into OVP mode. 4 IOUT_OC This bit gets set whenever the NCP81274 latches off due to an over current event. 0:3 Reserved N/A Fault Mask Register (0x22) Table 12. FAULT MASK REGISTER SETTINGS Bits Name 7:5 Reserved 4 Clim1 3 2 Clim2 Clim_phase Description When this bit is set, the Clim1 bit from the STATUS FAULT does not get set when an overcurrent event occurs. STATUS Warning Register (0x24) Table 14. STATUS WARNING REGISTER SETTINGS When this bit is set, the Clim2 bit from the STATUS FAULT does not get set when an overcurrent event occurs. When this bit is set, the Clim_phase bit from the STATUS FAULT register does not get set when an overcurrent event occurs. 1 OVP When this bit is set, the OVP bit from the STATUS FAULT register does not get set when an overvoltage event occurs. 0 UVP When this bit is set, the UVP bit from the STATUS FAULT register does not get set when an under voltage event occurs. Description N/A Bits Name Description 7:1 Reserved 0 IOUT Overcurrent Warning Reserved N/A This bit gets set if IOUT exceeds its programmed high warning limit(register 0x20). This bit is only cleared when EN is toggled. READ_IOUT Register (0x26) Read back output current. ADC conversion 0xFF = 2 V on IOUT pin which should equate to max current. Lock/Reset Register (0x2A) Table 15. LOCK/RESET REGISTER SETTINGS Bits Name 7:1 Reserved 0 Lock www.onsemi.com 21 Description N/A Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become read-only and cannot be modified until the NCP81274 is powered down and powered up again. This prevents rogue programs such as viruses from modifying critical system limit settings (Lockable). NCP81274 Soft Start Status Register (0x2B) Table 17. OCP STATUS AND CONFIGURATION REGISTER SETTINGS This register contains the value that sets the slew rate of the output voltage during power-up. When EN is set high, the controller reads the value of the resistor connected to the SS pin and sets the slew rate. The codes corresponding to each resistor setting are shown in Table 16. The resistor settings are updated on every rising edge of the EN signal. Bits Name 7:4 Reserved 3:2 Per Phase OCP Limit 00 = 65 mV 01 = 75 mV 10 = 100 mV 11 = 134 mV 1:0 OCP_latch Off Delay 00 = 4 ms 01 = 6 ms 10 = 8 ms 11 = 10 ms Table 16. SOFT START STATUS REGISTER SETTINGS TRAMP Resistor (kW) Bits Name Value T_ramp (ms) − 7:4 Reserved N/A N/A 10 3:0 T_Ramp 0000 0.15 14.7 0001 0.3 20 0010 0.45 Description N/A Switching Frequency Status and Configuration Registers (0x2F, 0x30) 26.1 0011 0.6s 33.2 0100 0.75 41.2 0101 0.9 49.9 0110 1 60.4 0111 2 71.5 1000 3 84.5 1001 4 100 1010 5 These registers contain the values that set the switching frequency of the controller. When EN is set high, the controller reads the value of the resistor connected to the FSW pin and sets the switching frequency according to Table 19. The codes corresponding to each setting are also shown in Table 19. The resistor settings are updated on every rising edge of the EN signal. The switching frequency configuration register allows the user to dynamically change the switching frequency through the I2C interface provided that the FSW bits from the second function configuration registers A and B (0x46, 0x47) are set. 118.3 1011 6 PSI Status Register (0x32) 136.6 1100 7 157.7 1101 8 The PSI status register provides the information regarding the current status of the PSI pin though the I2C interface as shown in Table 18. 182.1 1110 9 249 1111 10 NOTE: Table 18. PSI STATUS REGISTER SETTINGS Bits 1% tolerance. OCP Status Register and Configuration Register (0x2D, 0x2E) Reserved 1:0 00 = PSI MID 01 = PSI LOW 10 = PSI HIGH These registers contain the values that set the OCP current levels for each phase individually as well as the latch off delay time for the OCP event. When EN is set high, the controller reads the value of the resistor connected to the PWM7/OCP pin and sets the OCP threshold and latch off delay time according to Table 9. The codes corresponding to each setting are shown in Table 17. The resistor settings are updated on every rising edge of the EN signal. The OCP configuration register allows the user to dynamically change the OCP threshold and latch off delay through the I2C interface provided that the OCP bits from the second function configuration registers A and B (0x46, 0x47) are set. In addition, the OCP levels and latch off delay times can be adjusted independently when the OCP configuration register is used. The achievable switching frequency settings are listed in Table 17. www.onsemi.com 22 Description 7:2 NCP81274 Table 19. SWITCHING FREQUENCY STATUS AND CONFIGURATION REGISTER SETTINGS FSW Pin Resistor Value (kW) Value Switching Frequency (kHz) Bits Status Register Configuration Register 8 Phase 7 Phase 6 Phase 5 Phase 4 Phase 3 Phase 2 Phase 1 Phase 7:5 Reserved Reserved N/A N/A N/A N/A N/A N/A N/A N/A 4:0 00000 00000 221 253 295 355 221 293 223 232 − 00001 244 276 330 399 244 329 243 252 00010 00010 266 309 355 425 266 358 264 272 − 00011 293 327 387 460 293 381 294 297 20 00100 00100 307 351 412 501 307 407 317 322 − 00101 333 384 441 542 333 450 335 340 26.1 00110 00110 351 409 480 561 351 480 352 361 − 00111 373 431 499 615 373 510 380 385 33.2 01000 01000 394 451 528 639 394 530 399 413 − 01001 421 481 559 676 421 562 420 435 01010 01010 449 495 593 725 449 600 436 456 − 01011 469 525 612 746 469 614 454 478 01100 01100 479 563 639 757 479 631 483 500 − 01101 509 570 681 799 509 663 508 509 60.4 01110 01110 518 588 697 831 518 688 526 518 − 01111 543 617 722 874 543 722 543 540 71.5 10000 10000 581 665 779 930 581 789 583 578 − 10001 649 718 881 1043 649 859 656 638 84.5 10010 10010 708 790 937 1129 708 930 698 698 − 10011 751 868 1010 1211 751 1010 771 758 10100 10100 799 918 1073 1278 799 1095 807 818 − 10101 866 1003 1136 1372 866 1147 860 878 10110 10110 919 1025 1220 1449 919 1233 899 938 − 10111 964 1111 1297 1533 964 1260 950 972 136.6 11000 11000 993 1140 1339 1610 993 1341 1003 1014 − 11001 1059 1198 1438 1687 1059 1372 1052 1067 157.7 11010 11010 1098 1262 1485 1734 1098 1450 1096 1106 − 11011 1141 1295 1533 1821 1141 1539 1154 1155 182.1 11100 11100 1200 1338 1587 1890 1200 1619 1205 1201 − 11101 1236 1405 1608 1954 1236 1618 1227 1245 11110 11110 1291 1459 1707 2012 1291 1674 1274 1280 − 11111 1312 1493 1724 2096 1312 1724 1316 1330 10 14.7 41.2 49.9 100 118.3 249 NOTE: 1% tolerance. www.onsemi.com 23 NCP81274 Phase Status Register (0x33) Table 22. LPC STATUS AND CONFIGURATION REGISTER SETTINGS The Phase Status register provides the information about the status of each of the eight available phases as shown in Table 20. Table 20. PHASE STATUS REGISTER SETTINGS Bits Name 7 Phase 8 0 = Disabled 1 = Enabled 6 Phase 7 0 = Disabled 1 = Enabled Phase 6 0 = Disabled 1 = Enabled 4 Phase 5 0 = Disabled 1 = Enabled 3 Phase 4 0 = Disabled 1 = Enabled 2 Phase 3 0 = Disabled 1 = Enabled 1 Phase 2 0 = Disabled 1 = Enabled 0 Phase 1 0 = Disabled 1 = Enabled Table 21. LPC_ZONE_ENABLE REGISTER SETTINGS Reserved 3 Zone 4 Level 7:3 Reserved N/A N/A 2:0 LPC1 Configuration 000 0 001 1 010 2 011 3 100 4 101 = Reserved N/A 110 = Reserved N/A 111 = Reserved N/A These registers contain the values that set the fraction of the externally configured load line (see Total Current Sense Amplifier section) to be used during the normal operation of the device. When EN is set high, the controller reads the value of the resistor connected to the LL/I2C_ADD pin and sets the load line according to Table 5. The codes corresponding to each setting are shown in Table 23. The load line resistor setting is updated on every rising edge of the EN signal. The LL configuration register allows the user to dynamically change the load line settings through the I2C interface provided that the LL bits from the second function configuration registers A and B (0x46, 0x47) are set. The achievable load line settings are listed in Table 23. The LPC_Zone_enable register allows the user to enable or disable power zones while the controller has the PSI set low using the I2C interface as shown in Table 21. 7:4 Value LL Status and Configuration Registers (0x38, 0x39) LPC_Zone_enable Register (0x34) Name Name Description 5 Bits Bits Description Table 23. LL STATUS AND CONFIGURATION REGISTER SETTINGS N/A 0 = Disabled 1 = Enabled 2 Zone 3 0 = Disabled 1 = Enabled 1 Zone 2 0 = Disabled 1 = Enabled 0 Zone 1 0 = Disabled 1 = Enabled Bits Description 7:2 Reserved 1:0 00 = 100% of externally set load line (default) 01 = 50% of externally set load line 10 = 25 of externally set load line 11 = 0% of externally set load line PHTH1 to PHTH4 Configuration Registers (0x3A, 0x3C, 0x3E, 0x40) LPC Status and Configuration Registers (0x35, 0x36) These registers contain the values that control the phase shedding thresholds and are active when the PHTHX bits from the second function configuration registers A and B (0x46 and 0x47) are set be set. These thresholds allow the user to dynamically change the thresholds through the I2C interface. The values written to these registers should match the value of the READ_IOUT register (0x26) at the desired load current. If 0xFF is written to a register, the phase shedding threshold corresponding to that register is disabled. These registers contain the values that set the operating power zone when the PSI pin is set low. When EN is set high, the controller reads the value of the resistor connected to the PWM6/LPC1 and PWM5/LPC2 pins and sets the power zone according to Table 7. The codes corresponding to each setting are shown in Table 22. The LPCX resistor settings are updated on every rising edge of the EN signal. The LPC configuration register allows the user to dynamically change the power zone (PSI = Low) through the I2C interface provided that the LPC bits from the second function configuration registers A and B (0x46, 0x47) are set. The achievable power zone settings are listed in Table 22. www.onsemi.com 24 NCP81274 PHTH1 to PHTH4 Status Registers (0x3B, 0x3D, 0x3F 0x41) Table 24. SECOND CONFIGURATION LATCH REGISTER A AND B These registers contain the phase shedding threshold values set by the resistors connected to the PHTHX pins. The values of the thresholds are updated on every rising edge of the EN signal. The resistor values should be chosen to ensure that the voltage drop across them developed by the 10 mA current sourced by the NCP81274 during power-up (EN set high) matches the value of the READ_IOUT register (0x26) at the desired load current. Setting the resistors to generate a voltage above 2 V will disable the PHTHX threshold for that pin. Bits Second Function Configuration Register 7:6 Reserved 5 FSW 0 = set by external resistor (see Table 19) 1 = set by register 0x30 (see Table 19) 4 LL 0 = set by external resistor (see Table 5) 1 = set by register 0x39 3 Reserved 2 OCP 1 Reserved 0 PHTHX Phase Shedding Hysteresis Register (0x44) This register sets the hysteresis during a transition from a high count phase to a low count phase configuration. The hysteresis is expressed in codes (LSBs) of the PHTHX threshold values. Phase Shedding Delay Register (0x45) This register sets the delay during a transition from a high count phase to a low count phase configuration. The power-up default value is 200 ms and it can be dynamically changed in steps of 10 ms (1 LSB) through the I2C interface. Second Function Configuration Register Latch A and B Registers (0x46, 0x47) These registers allow the user to select whether the second functions settings (LL, Soft Start, OCP, LPC and PHTHX) are controlled by the external resistors or the configuration registers (see Table 24). When/EN is toggled the default control mode for the second functions is the external resistor. Switching between the two modes can be done by simply writing the appropriate byte (the same byte) to both registers (the order doesn’t matter). www.onsemi.com 25 Description N/A N/A 0 = set by external resistor (see Table 9) 1= set by register 0x2E N/A 0 = set by external resistors connected between PHTHX pins and GND 1 = set by registers 0x3A, 0x3C, 0x3E and 0x40 NCP81274 PACKAGE DIMENSIONS QFN40 5x5, 0.4P CASE 485CR ISSUE C ÉÉÉ ÉÉÉ PIN ONE LOCATION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L2 A B D L2 DETAIL A E DIM A A1 A3 b D D2 E E2 e L L1 L2 L L 0.15 C L1 0.15 C TOP VIEW DETAIL B 0.10 C DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS (A3) A 0.08 C A1 SIDE VIEW NOTE 4 EXPOSED Cu C SEATING PLANE ÉÉ ÉÉ MOLD CMPD DETAIL B 0.10 M ALTERNATE CONSTRUCTION C A B D2 DETAIL A MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.15 0.25 5.00 BSC 3.40 3.60 5.00 BSC 3.40 3.60 0.40 BSC 0.30 0.50 −−− 0.15 0.12 REF RECOMMENDED SOLDERING FOOTPRINT 5.30 40X 11 0.10 21 M 0.63 3.64 C A B 1 E2 40 40X L 5.30 3.64 1 e e/2 BOTTOM VIEW 40X b 0.10 M C A B 0.05 M C PKG OUTLINE NOTE 3 0.40 PITCH 40X 0.25 DIMENSIONS: MILLIMETERS NVIDIA is a registered trademark of of NVIDIA Corporation in the U.S. and/or other countries. All other brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders. 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