NCP81278MNTXG

NCP81278 Compact 2-Phase Synchronous Buck Controller with Integrated Gate Drivers and PWM VID Interface The NCP81278, a general−purpose two−phase synchronous buck controller, integrates gate drivers and PWM VID interface in a QFN−20 package and provides a compact−footprint power management solution for new generation computing processors. It has a programmable power save interface (PSI) and is able to operate in 1−phase diode emulation mode to obtain high efficiency in light−load condition. Operating in high switching frequency up to 800 kHz allows employing small size inductor and capacitors. The part is able to support all−ceramic−capacitor applications. www.onsemi.com QFN20 CASE 485BC MARKING DIAGRAM 81278 ALYWG G Features 3.6 V to 24 V Input Voltage Range Output Voltage up to 2.0 V with PWM VID Interface Differential Output Voltage Sense Integrated Gate Drivers 200 kHz ~ 800 kHz Switching Frequency Power Saving Interface (PSI) Support both 3.3 V and 1.8 V VID Power Good Output Programmable Over Current Protection Over Voltage Protection Under Voltage Protection Thermal Shutdown Protection QFN20, 3x3 mm, 0.4 mm Pitch Package 81278 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS PH1 LG1 PVCC LG2 PH2 • • • • • • • • • • • • • 1 BST1 HG1 EN PSI VID Typical Applications VIDBUF REFIN VREF FS FBRTN • GPU and CPU Power • Graphics Card Applications • Desktop and Notebook Applications GND BST2 HG2 PGOOD COMP/ILMT FB (Top View) ORDERING INFORMATION Device NCP81278MNTXG Package Shipping† QFN20 (Pb−Free) 4,000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 April, 2017 − Rev. 4 1 Publication Order Number: NCP81278/D NCP81278 VIN +5V 18 PVCC 21 GND HG1 2 BST1 1 PH1 20 LG1 19 VOUT 3.3V/1.8V VIN EN 3 EN PSI 4 PSI PG 13 5 VID PGOOD HG2 14 BST2 15 PH2 16 LG2 17 FBRTN 10 FB 11 COMP/ ILMT 12 VID 8 VREF 7 REFIN 6 VIDBUF 9 NCP81278 FS Figure 1. Typical Application Circuit with PWM−VID Interface VIN +5V 18 PVCC 21 GND HG1 2 BST1 1 PH1 20 LG1 19 VOUT 3.3V/1.8V VIN EN 3 EN PSI 4 PSI PG 13 5 PGOOD HG2 14 BST2 15 PH2 16 LG2 17 FBRTN 10 FB 11 VID 8 VREF 7 REFIN 6 VIDBUF 9 NCP81278 FS COMP/ 12 ILMT Figure 2. Typical Application Circuit without PWM−VID Interface www.onsemi.com 2 NCP81278 PVCC PVCC 3 13 EN UVLO & PGOOD BST1 FAULT HG1 PGOOD PWM1 PH1 Gate Drive 1 PVCC Thermal Shutdown PSI PSI Control Ramp Generator PH1 BST2 Protections (OVP,UVP,OCP) HG2 RAMP2 PWM2 8 5 6 VREF Reference Voltage PVCC GND VID VIDBUF PWM1 PH1 REFIN LG1 FB CS2 PWM2 PH2 LG2 10 FBRTN GND GND 12 21 15 14 16 LG2 17 Current Sense 11 PH2 Gate Drive 2 CS1 7 20 PVCC & FS 2 LG1 GND PWM Control RAMP1 9 1 19 2/1 Phase 4 18 COMP/ILMT Figure 3. Functional Block Diagram www.onsemi.com 3 NCP81278 PIN DESCRIPTION Pin Name Type Description 1 BST1 Analog Power Bootstrap 1. Provides bootstrap voltage for the high−side gate drive of phase 1. A 0.1 mF ~ 1 mF ceramic capacitor is required from this pin to PH1 (pin 20). 2 HG1 Analog Output High−Side Gate 1. Directly connected with the gate of the high−side power MOSFET of phase 1. 3 EN Logic Input Enable. Logic high enables the device and logic low makes the device in standby mode. 4 PSI Logic Input Power Saving Interface. Logic high enables 2−phase CCM operation, mid level enables 1−phase CCM operation, and logic low enables 1−phase auto CCM/DCM operation. 5 VID Logic Input Voltage ID. Voltage ID input from processor. 6 VIDBUF Analog Output 7 REFIN Analog Input Reference Input. Reference voltage input for output voltage regulation. The pin is connected to a non−inverting input of internal error amplifier. 8 VREF Analog Output Output Reference Voltage. Precise 2 V reference voltage output. A 10 nF ceramic capacitor is required from this pin to GND. 9 FS Analog Input Frequency Selection. A resistor from this pin to ground programs switching frequency. 10 FBRTN Analog Input Voltage Feedback Return Input. An inverting input of internal error amplifier. Feedback. An inverting input of internal error amplifier. Voltage ID Buffer. VID PWM pulse output from an internal buffer. 11 FB Analog Input 12 COMP/ILMT Analog Output Compensation / ILMT. Output pin of error amplifier. A resistor may be applied between this pin and GND to program OCP threshold. 13 PGOOD Logic Output Power GOOD. Open−drain output. Provides a logic high valid power good output signal, indicating the regulator’s output is in regulation window. 14 HG2 Analog Output High−Side Gate 2. Connected with the gate of the high−side power MOSFET in phase 2. 15 BST2 Analog Power Bootstrap 2. Provides bootstrap voltage for the high−side gate drive of phase 2. A 0.1 mF ~ 1 mF ceramic capacitor is required from this pin to PH2 (pin 16). 16 PH2 Analog Input Phase Node 2. Connected to interconnection between high−side MOSFET and low−side MOSFET in phase 2. 17 LG2 Analog Output Low−Side Gate 2. Connected with the gate of the low−side power MOSFET in phase 2. 18 PVCC Analog Power Voltage Supply of Controller and Gate Driver. Power supply input pin of control circuit and internal gate drivers. A 4.7 mF or larger ceramic capacitor bypasses this input to ground. This capacitor should be placed as close as possible to this pin. 19 LG1 Analog Output Low−Side Gate 1. Connected with the gate of the low−side power MOSFET in phase 1. 20 PH1 Analog Input Phase Node 1. Connected to interconnection between high−side MOSFET and low−side MOSFET in phase 1. 21 THERM/GND Analog Ground Thermal Pad and Ground. Common ground of internal control circuits and gate drivers. Must be connected to the system ground. www.onsemi.com 4 NCP81278 MAXIMUM RATINGS Value Rating PH to GND Supply Voltage PVCC to GND BST to GND Symbol Min Max Unit VPH −2 −8 (