NCS20084DR2G

Operational Amplifier, Low Power, 1.2 MHz, 42 mA NCS20081/2/4, NCV20081/2/4 The NCS20081/2/4 is a family of single, dual and quad Operational Amplifiers (Op Amps) with 1.2 MHz of Gain−Bandwidth Product (GBWP) While consuming only 42 mA of Quiescent current per opamp. The NCS2008x has Input Offset Voltage of 4 mV and operates from 1.8 V to 5.5 V supply voltage over a wide temperature range (−40°C to +125°C). The Rail−to−Rail In/Out operation allows the use of the entire supply voltage range while taking advantage of the 1.2 MHz GBWP. Thus, this family offers superior performance over many industry standard parts. These devices are AEC−Q100 qualified which is denoted by the NCV prefix. NCS2008x’s low current consumption and low supply voltage performance in space saving packages, makes them ideal for sensor signal conditioning and low voltage current sensing applications in Automotive, Consumer and Industrial markets. • Wide Bandwidth: 1.2 MHz Low Supply Current/ Channel: 42 mA typ (VS = 1.8 V) Low Input Offset Voltage: 4 mV max Wide Supply Range: 1.8 V to 5.5 V Wide Temperature Range: −40°C to +125°C Rail−to−Rail Input and Output Unity Gain Stable Available in Single, Dual and Quad Packages NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Applications • • • • • • January, 2021 − Rev. 18 1 SC70−5 CASE 419A TSOP−5/SOT23−5 CASE 483 8 1 SOIC−8 CASE 751 14 1 TSSOP−8 CASE 948S TSSOP−14 CASE 948G 6 14 1 SOIC−14 CASE 751A 1 UDFN6 CASE 517AP DEVICE MARKING INFORMATION Automotive Battery Powered/ Portable Sensor Signal Conditioning Low Voltage Current Sensing Filter Circuits Unity Gain Buffer © Semiconductor Components Industries, LLC, 2017 5 Micro8/MSOP8 CASE 846A Features • • • • • • • • • www.onsemi.com See general marking information in the device marking section on page 2 of this data sheet. ORDERING INFORMATION See detailed ordering and shipping information on page 3 of this data sheet. 1 Publication Order Number: NCS2008/D NCS20081/2/4, NCV20081/2/4 MARKING DIAGRAMS Single Channel Configuration NCS20081, NCV20081 5 XXMG G 1 XXXAYWG G XX MG G 1 TSOP−5/SOT23−5 CASE 483 SC70−5 CASE 419A UDFN6 CASE 517AP Dual Channel Configuration NCS20082, NCV20082 8 8 XXXXXX ALYW G XXXX AYWG G XXX YWW AG 1 1 Micro8]/MSOP8 CASE 846A TSSOP−8 CASE 948S SOIC−8 CASE 751 Quad Channel Configuration NCS20084, NCV20084 14 14 XXXX XXXX ALYWG G XXXXXXXXG AWLYWW 1 1 TSSOP−14 CASE 948G SOIC−14 CASE 751A XXXXX A WL, L Y WW, W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) www.onsemi.com 2 NCS20081/2/4, NCV20081/2/4 Single Channel Configuration NCS20081, NCV20081 OUT 1 5 IN+ VDD 1 5 VDD VSS 1 6 OUT NC 2 5 VDD IN− 3 4 IN+ VSS 2 IN+ 2 3 4 IN− IN− SC70−5, SOT23−5 (TSOP−5) SQ2, SN2 Pinout − − − + VSS 3 4 OUT + + UDFN6 1.6 x 1.6 SC70−5, SOT23−5 (TSOP−5) SQ3, SN3 Pinout Quadruple Channel Configuration NCS20084, NCV20084 Dual Channel Configuration NCS20082, NCV20082 OUT 1 1 IN− 1 2 − 3 + IN+ 1 VSS 4 8 VDD 7 OUT 2 − 6 IN− 2 + 5 IN+ 2 Micro8/MSOP8, SOIC−8, TSSOP−8 OUT 1 1 IN− 1 2 − − 13 IN− 4 IN+ 1 3 + + 12 IN+ 4 VDD 4 IN+ 2 5 + + 10 IN+ 3 IN− 2 6 − − 9 IN− 3 OUT 2 7 8 OUT 3 14 OUT 4 11 VSS TSSOP−14, SOIC−14 Figure 1. Pin Connections ORDERING INFORMATION Device Configuration Marking Package NCS20081SQ2T2G AAX SC70 NCS20081SQ3T2G AAP SC70 AER SOT23−5/TSOP−5 AEU SOT23−5/TSOP−5 AP UDFN6 NCV20081SQ2T2G* AAX SC70 NCV20081SQ3T2G* AAP SC70 AER SOT23−5/TSOP−5 NCV20081SN3T1G* AEU SOT23−5/TSOP−5 NCS20082DMR2G 2K82 Micro8/MSOP8 NCS20081SN2T1G Automotive No NCS20081SN3T1G NCS20081MUTAG Single Yes NCV20081SN2T1G* NCS20082DR2G NCS20082DTBR2G NCV20082DMR2G* No Dual NCV20082DR2G* Yes NCV20082DTBR2G* NCS20084DR2G NCS20084DTBR2G NCV20084DR2G* NCV20084DTBR2G* No Quad Yes NCS20082 SOIC−8 K82 TSSOP−8 2K82 Micro8/MSOP8 NCS20082 SOIC−8 K82 TSSOP−8 20084 SOIC−14 284 TSSOP−14 20084 SOIC−14 284 TSSOP−14 Shipping† Contact local sales office for more information †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 3 NCS20081/2/4, NCV20081/2/4 ABSOLUTE MAXIMUM RATINGS (Note 1) Symbol Rating Limit Unit Supply Voltage (VDD – VSS) (Note 2) VS 6 V Input Voltage VI VSS − 0.5 to VDD + 0.5 V Differential Input Voltage VID ±Vs V Maximum Input Current II ±10 mA Maximum Output Current IO ±100 mA Continuous Total Power Dissipation (Note 2) PD 200 mW Maximum Junction Temperature TJ 150 °C Storage Temperature Range TSTG −65 to 150 °C Mounting Temperature (Infrared or Convection – 20 sec) Tmount 260 °C ESDHBM ESDCDM 2000 2000 V ILU 100 mA MSL Level 1 ESD Capability (Note 3) Human Body Model Charge Device Model Latch−Up Current (Note 4) Moisture Sensitivity Level (Note 5) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS for Safe Operating Area. 2. Continuous short circuit operation to ground at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of the maximum output current rating over the long term may adversely affect reliability. Shorting output to either VDD or VSS will adversely affect reliability. 3. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per JEDEC standard Js−001−2017 (AEC−Q100−002) ESD Charged Device Model tested per JEDEC standard JS−002−2014 (AEC−Q100−011) 4. Latch−up Current tested per JEDEC standard JESD78E (AEC−Q100−004) 5. Moisture Sensitivity Level tested per IPC/JEDEC standard: J-STD-020A THERMAL INFORMATION Parameter Symbol Channels Single Junction to Ambient Thermal Resistance qJA Dual Quad Package Single Layer Board (Note 6) Multi−Layer Board (Note 7) SC−70 491 444 SOT23−5/TSOP−5 310 247 UDFN6 278 239 Micro8/MSOP8 236 167 SOIC−8 190 131 TSSOP−8 253 194 SOIC−14 130 99 TSSOP−14 178 140 Unit °C/W 6. Value based on 1S standard PCB according to JEDEC51−3 with 1.0 oz copper and a 300 mm2 copper area 7. Value based on 1S2P standard PCB according to JEDEC51−7 with 1.0 oz copper and a 100 mm2 copper area OPERATING RANGES Parameter Symbol Min Max Unit VS 1.8 5.5 V VS V VICM VSS – 0.2 VDD + 0.2 V TA −40 125 °C Operating Supply Voltage Differential Input Voltage VID Input Common Mode Range Ambient Temperature Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 4 NCS20081/2/4, NCV20081/2/4 ELECTRICAL CHARACTERISTICS AT VS = 1.8 V TA = 25°C; RL ≥ 10 kW; VCM = VOUT = mid−supply unless otherwise noted. Boldface limits apply over the specified temperature range, TA = −40°C to 125°C. (Note 8) Parameter Symbol Conditions Min Typ Max Unit 0.5 3.5 mV 4 mV INPUT CHARACTERISTICS Input Offset Voltage Offset Voltage Drift Input Bias Current (Note 8) VOS DVOS/DT 1 IIB 1 mV/°C pA 1500 Input Offset Current (Note 8) IOS 1 pA 1100 Channel Separation XTLK f = 1 kHz pA pA 125 dB Differential Input Resistance RID 10 GW Common Mode Input Resistance RIN 10 GW Differential Input Capacitance CID 1 pF Common Mode Input Capacitance CCM 5 pF 73 dB 120 dB mA Common Mode Rejection Ratio CMRR VCM = VSS – 0.2 to VDD + 0.2 48 VCM = VSS + 0.2 to VDD − 0.2 45 OUTPUT CHARACTERISTICS Open Loop Voltage Gain AVOL 86 80 Short Circuit Current ISC Output to positive rail, sinking current 15 Output to negative rail, sourcing current 11 Output Voltage High VOH Voltage output swing from positive rail VOH = VDD − VOUT 3 Output Voltage Low VOL Voltage output swing from negative rail VOL = VOUT − VSS 3 19 mV 20 19 mV 20 AC CHARACTERISTICS Unity Gain Bandwidth UGBW Slew Rate at Unity Gain SR Phase Margin ym Gain Margin Am Settling Time tS Open Loop Output Impedance VIN = 1.2 Vpp, Gain = 1 VIN = 1.2 Vpp, Gain = 1 1.2 MHz 0.4 V/ms 60 ° 19 dB Settling time to 0.1% 5 ms Settling time to 0.01% 6 ZOL See Figure 25 W NOISE CHARACTERISTICS Total Harmonic Distortion plus Noise THD+N VIN = 1.2 Vpp, f = 1 kHz, Av = 1 0.005 % Input Referred Voltage Noise en f = 1 kHz 30 nV/√Hz f = 10 kHz 24 Input Referred Current Noise in f = 1 kHz 300 fA/√Hz PSRR No Load 90 dB SUPPLY CHARACTERISTICS Power Supply Rejection Ratio 67 64 Power Supply Quiescent Current IDD Per channel, no load 8. Performance guaranteed over the indicated operating temperature range by design and/or characterization. www.onsemi.com 5 42 60 mA NCS20081/2/4, NCV20081/2/4 ELECTRICAL CHARACTERISTICS AT VS = 3.3 V TA = 25°C; RL ≥ 10 kW; VCM = VOUT = mid−supply unless otherwise noted. Boldface limits apply over the specified temperature range, TA = −40°C to 125°C. (Note 9) Parameter Symbol Conditions Min Typ Max Unit 0.5 3.5 mV 4 mV INPUT CHARACTERISTICS Input Offset Voltage Offset Voltage Drift Input Bias Current (Note 9) VOS DVOS/DT 1 IIB 1 mV/°C pA 1500 Input Offset Current (Note 9) IOS 1 pA 1100 Channel Separation XTLK f = 1 kHz pA pA 125 dB Differential Input Resistance RID 10 GW Common Mode Input Resistance RIN 10 GW Differential Input Capacitance CID 1 pF Common Mode Input Capacitance CCM 5 pF 76 dB 120 dB mA Common Mode Rejection Ratio CMRR VCM = VSS – 0.2 to VDD + 0.2 53 VCM = VSS + 0.2 to VDD − 0.2 48 OUTPUT CHARACTERISTICS Open Loop Voltage Gain AVOL 90 86 Short Circuit Current ISC Output to positive rail, sinking current 15 Output to negative rail, sourcing current 11 Output Voltage High VOH Voltage output swing from positive rail VOH = VDD − VOUT 3 Output Voltage Low VOL Voltage output swing from negative rail VOL = VOUT − VSS 3 24 mV 25 24 mV 25 AC CHARACTERISTICS Unity Gain Bandwidth UGBW Slew Rate at Unity Gain SR Phase Margin ym Gain Margin Am Settling Time tS Open Loop Output Impedance VIN = 2.5 Vpp, Gain = 1 VIN = 2.5 Vpp, Gain = 1 1.2 MHz 0.4 V/ms 60 ° 18 dB Settling time to 0.1% 5 ms Settling time to 0.01% 6 ZOL See Figure 25 W NOISE CHARACTERISTICS Total Harmonic Distortion plus Noise THD+N VIN = 2.5 Vpp, f = 1 kHz, Av = 1 0.005 % Input Referred Voltage Noise en f = 1 kHz 30 nV/√Hz f = 10 kHz 24 Input Referred Current Noise in f = 1 kHz 300 fA/√Hz PSRR No Load 90 dB SUPPLY CHARACTERISTICS Power Supply Rejection Ratio 67 64 Power Supply Quiescent Current IDD Per channel, no load 9. Performance guaranteed over the indicated operating temperature range by design and/or characterization. www.onsemi.com 6 42 60 mA NCS20081/2/4, NCV20081/2/4 ELECTRICAL CHARACTERISTICS AT VS = 5.5 V TA = 25°C; RL ≥ 10 kW; VCM = VOUT = mid−supply unless otherwise noted. Boldface limits apply over the specified temperature range, TA = −40°C to 125°C. (Note 10) Parameter Symbol Conditions Min Typ Max Unit 0.5 3.5 mV 4 mV INPUT CHARACTERISTICS Input Offset Voltage Offset Voltage Drift Input Bias Current (Note 10) VOS DVOS/DT 1 IIB 1 mV/°C pA 1500 Input Offset Current (Note 10) IOS 1 pA 1100 Channel Separation XTLK f = 1 kHz pA pA 125 dB Differential Input Resistance RID 10 GW Common Mode Input Resistance RIN 10 GW Differential Input Capacitance CID 1 pF Common Mode Input Capacitance Common Mode Rejection Ratio CCM CMRR VCM = VSS – 0.2 to VDD + 0.2 55 VCM = VSS + 0.2 to VDD − 0.2 51 5 pF 79 dB 120 dB mA OUTPUT CHARACTERISTICS Open Loop Voltage Gain AVOL 90 86 Short Circuit Current ISC Output to positive rail, sinking current 15 Output to negative rail, sourcing current 11 Output Voltage High VOH Voltage output swing from positive rail VOH = VDD − VOUT 3 Output Voltage Low VOL Voltage output swing from negative rail VOL = VOUT − VSS 3 24 mV 25 24 mV 25 AC CHARACTERISTICS Unity Gain Bandwidth UGBW MHz 0.4 V/ms SR Phase Margin ym 60 ° Gain Margin Am 17 dB Settling Time tS 5 ms Open Loop Output Impedance VIN = 5 Vpp, Gain = 1 1.2 Slew Rate at Unity Gain VIN = 5 Vpp, Gain = 1 Settling time to 0.1% Settling time to 0.01% 6 ZOL See Figure 25 W NOISE CHARACTERISTICS Total Harmonic Distortion plus Noise THD+N VIN = 5 Vpp, f = 1 kHz, Av = 1 0.005 % Input Referred Voltage Noise en f = 1 kHz 30 nV/√Hz f = 10 kHz 24 Input Referred Current Noise in f = 1 kHz 300 fA/√Hz PSRR No Load 90 dB SUPPLY CHARACTERISTICS Power Supply Rejection Ratio 67 64 Power Supply Quiescent Current IDD Per channel, no load 48 70 mA 10. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 7 NCS20081/2/4, NCV20081/2/4 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, RL ≥ 10 kW, VCM = VOUT = mid−supply unless otherwise specified 60 T = 125°C 50 T = 25°C 40 T = −40°C 30 20 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 10 0 −40 −20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 2. Quiescent Current per Channel vs. Supply Voltage Figure 3. Quiescent Current vs. Temperature 800 600 700 T = −40°C T = 25°C OFFSET VOLTAGE (mV) OFFSET VOLTAGE (mV) 20 SUPPLY VOLTAGE (V) 700 T = 0°C 500 400 T = 125°C T = 85°C 300 200 VS = 5.5 V VS = 3.3 V 600 500 400 VS = 1.8 V 300 200 100 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 3000 0 −40 −20 5.5 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 4. Offset Voltage vs. Supply Voltage Figure 5. Offset Voltage vs. Temperature 140 VS = 5.5 V 20 units 1000 80 GAIN (dB) 100 0 −1000 −3000 −0.7 0 0.7 1.4 2.1 2.8 135 Phase Margin 90 40 0 −1.4 Gain 60 20 −2000 −2.1 180 120 2000 −4000 −2.8 0 SUPPLY VOLTAGE (V) 4000 OFFSET VOLTAGE (mV) VS = 1.8 V 30 5.5 5.0 800 0 40 −20 AV−10 RL = 10 kW CL = 15 pF −22 dBm Input 10 100 45 1k 10k 100k 1M 10M 0 COMMON MODE VOLTAGE (V) FREQUENCY (Hz) Figure 6. Offset Voltage vs. Common Mode Voltage Figure 7. Open−loop Gain and Phase Margin vs. Frequency www.onsemi.com 8 PHASE MARGIN (°) 0 VS = 3.3 V 50 VS = 5.5 V SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 60 NCS20081/2/4, NCV20081/2/4 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, RL ≥ 10 kW, VCM = VOUT = mid−supply unless otherwise specified 60 50 40 30 20 0 100 200 300 400 1 Figure 8. Phase Margin vs. Capacitive Load Figure 9. THD + N vs. Output Voltage 600 VOLTAGE NOISE (nV/√Hz) THD+N (%) 0.1 OUTPUT VOLTAGE (Vrms) VS = 1.8 V 0.1 0.01 VS = 3.3 V VS = 5.5 V 10 100 1k VS = 5.5 V 500 400 300 200 100 0 10k 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 10. THD + N vs. Frequency Figure 11. Input Voltage Noise vs. Frequency 120 900 VS = 5.5 V 800 VS = 5.5 V, PSRR+ 100 700 600 PSRR (dB) CURRENT NOISE (fA/√Hz) 0.01 CAPACITIVE LOAD (pF) A = 1V/V RL = 10 K 1 Vrms 500 400 300 200 VS = 5.5 V, PSRR− 80 VS = 1.8 V, PSRR+ 60 VS = 1.8 V, PSRR− 40 20 100 0 0.1 0.001 500 1 0.001 1 0.01 10 0 VS = 5.5 V fIN = 1 kHz AV = 1 10 THD+N (%) PHASE MARGIN (°) 100 VS = 5.5 V RL = 10 kW T = 25°C 1 10 100 1k 10k 100k 0 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 12. Input Current Noise vs. Frequency Figure 13. PSRR vs. Frequency www.onsemi.com 9 1M NCS20081/2/4, NCV20081/2/4 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, RL ≥ 10 kW, VCM = VOUT = mid−supply unless otherwise specified 120 500 OUTPUT VOLTAGE TO POSITIVE RAIL (mV) AV = 1 VS = 5.5 V 100 CMRR (dB) VS = 3.3 V 80 VS = 1.8 V 60 40 20 OUTPUT VOLTAGE TO NEGATIVE RAIL (mV) 0 10 100 1k 10k 100k 400 300 200 VS = 3.3 V 100 VS = 5.5 V 0 1M VS = 1.8 V 0 2 4 6 8 10 FREQUENCY (Hz) OUTPUT CURRENT (mA) Figure 14. CMRR vs. Frequency Figure 15. Output Voltage High to Rail 500 VS = 1.8 V 400 300 VS = 3.3 V 200 VS = 5.5 V 100 0 0 2.5 5.0 7.5 10.0 12.5 15.0 OUTPUT CURRENT (mA) Figure 16. Output Voltage Low to Rail Figure 17. Non−Inverting Small Signal Transient Response Figure 18. Inverting Small Signal Transient Response Figure 19. Non−Inverting Large Signal Transient Response www.onsemi.com 10 12 NCS20081/2/4, NCV20081/2/4 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, RL ≥ 10 kW, VCM = VOUT = mid−supply unless otherwise specified 600 CURRENT (pA) 500 IIB+ 400 IIB− 300 200 100 IOS 0 −100 −40 −20 0 20 40 80 60 100 120 140 TEMPERATURE (°C) Figure 20. Inverting Large Signal Transient Response Figure 21. Input Bias and Offset Current vs. Temperature 6 VOLTAGE (mV) 4 2 0 −2 −4 −6 0 1 2 3 4 5 6 7 8 9 TIME (s) Figure 22. Input Bias Current vs. Common Mode Voltage Figure 23. 0.1 Hz to 10 Hz Noise CHANNEL SEPARATION (dB) −60 −80 −100 −120 −140 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 24. Channel Separation vs. Frequency Figure 25. Open Loop Output Impedance vs. Frequency www.onsemi.com 11 10 NCS20081/2/4, NCV20081/2/4 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, RL ≥ 10 kW, VCM = VOUT = mid−supply unless otherwise specified SLEW RATE (V/ms) 0.6 0.5 0.4 SR+ SR− 0.3 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 26. Slew Rate vs. Temperature www.onsemi.com 12 140 NCS20081/2/4, NCV20081/2/4 Application Information below VSS or one diode drop above VDD. Very fast ESD events (within the limits specified) trigger the protection structure so the operational amplifier is not damaged. However, in some applications, it can be necessary to prevent excessive voltages from reaching the operational amplifier inputs by adding external clamp diodes. A possible solution is presented in Figure 27, where the four low−drop fast diodes (Shottky preferred) are used in parallel with the internal structure to divert the excessive energy to the supply rails where it can be easily dissipated or absorbed by the supply capacitors. The application designer should also take into account that these external diodes add leakage currents and parasitic capacitance that must be considered when evaluating the end−to−end performance of the amplifier stage. The NCS/NCV20081/2/4 family of operational amplifiers is manufactured using ON Semiconductor’s CMOS process. Products in this class are general purpose, unity−gain stable amplifiers and include single, dual and quad configurations. Rail−to−Rail Input with No Phase Reversal The NCS operational amplifiers are designed to prevent phase reversal or any similar issues when the input pins potential exceed the supply voltages by up to 100 mV. Figure 6 shows the input voltage exceeding the supply limits. The input stage of the NCS/NCV 20081/2/4 family consists of two differential CMOS input stages connected in parallel: the first is constructed using paired PMOS devices and it operates at low common mode input voltages (VCM) ; the second stage is build using paired NMOS devices to operate at high VCM. The transition between the two input stages occurs at a common mode input voltage of approximately VDD–1.3V and it is visible in Figure 6 (Offset vs. VCM). Limiting Input Currents In order to prevent damage/ improper operation of these amplifiers, the application circuit must limit the currents flowing in and out of the input pins. A possible solution is presented in Figure 27 by means of the two added series resistors. The minimum value for R_IN− and R_IN+ should be calculated using Ohm’s Law so they limit the input pin currents to less than the absolute maximum values specified. The application designer should take into account that these resistors also add parasitic inductance that must be considered when evaluating performance. Combining the current limiting resistors with the voltage limiting diodes creates a solid input protection structure, that can be used to insure reliable operation of the amplifier even in the hardest conditions. Limiting Input Voltages In order to prevent damage and/or improper operation of these amplifiers, the application circuit must never expose the input pins to voltages or currents higher than the Absolute Maximum Ratings. The internal ESD structure includes special diodes to protect the input stages while maintaining a low Input Bias (IIB) current. The input protection circuitry clamp the inputs when the signals applied exceed more than one diode drop Figure 27. Typical Protection of the Operational Amplifier Inputs Rail−to−Rail Output While the NCS(V)20081/2/4 family of opamps are capable of driving capacitive loads up to 100 pF, adding a small resistor in series to the output (R_ISO in Figure 28) will increase the feedback loop’s phase margin. This leads to higher stability by making the equivalent load more resistive at high frequencies. The maximum output voltage swing is dependent of the particular output load. According to the specification, the output can reach within 25 mV of either supply rail when load resistance is 10 kW. Figure 15 and Figure 16 shows the load drive capabilities of the part under different conditions. Output current is internally limited to 15 mA typ. Capacitive Loads Driving capacitive loads can create stability problems for voltage feedback opamps, as it is a known possible cause for: • degraded phase margin • lowered bandwidth • gain peaking of the frequency response • overshoot and ringing of the step response. Figure 28. Driving Capacitive Loads www.onsemi.com 13 NCS20081/2/4, NCV20081/2/4 order to achieve a settling time shorter than the multiplexed sampling rate, an RC stage is recommended between the buffer and the ADC input. The R resistor’s value should be low enough to charge the capacitor quickly, but at the same time large enough to isolate the capacitive load from the opamp’s output to preserve phase margin. When transients are generated by the sensor’s output, first the two opamp’s inputs see a high differential voltage between them, then the output settles and brings the inverting input back to the correct voltage. To successfully accommodate for example a 0.1 V to 4 V sensor signal, the opamp’s differential input range of the NCS(V) 20081/2/4 series is close to the supply range VDD−VSS, and the output will match the input. The differential input voltage is limited only by the ESD protection structure and not by back−to−back diodes between inputs. Simulating the application with ON Semiconductor’s SPICE models is a good starting point for selecting the isolation resistor’s value, and then bench testing the frequency and step response can be used to fine−tune the value according to the desired characteristic. Unity Gain Bandwidth Interfacing a high impedance sensor’s output to a relatively low−impedance ADC input usually requires an intermediate stage to avoid unwanted interference of the two devices, and this stage needs to have a high input impedance, a low output impedance and high output current. The unity gain buffer is recommended here (Figure 29).The ADC’s internal sampling capacitor requires a buffer front−end to recharge it faster than the sampling time, and this problem is even worse if more channels are sampled by the same ADC using an internal multiplexer. In Figure 29. Unity Gain Buffer Stage for Sampling with ADC Power Supply Bypassing For AC, the power supply pins (VDD and VSS for split supply, VDD for single supply) should be bypassed locally with a quality capacitor in the range of 100 nF (ceramics are recommended for their low ESR and good high frequency response) as close as possible to the opamp’s supply pins. For DC, a bulk capacitor in the range of 1 mF within inches distance from the opamp can provide the increased currents required to drive higher loads. Figure 30. Unused Operational Amplifiers Unused Operational Amplifiers Occasionally not all the opamps offered in the quad packages are needed for a specific application. They can be connected as “buffering ground” as shown in Figure 30, a solution that does not need any extra parts. Connecting them differently (inputs split to rails, left floating, etc.) can sometimes cause unwanted oscillation, crosstalk, increased current consumption, or add noise to the supply rails. PCB Surface Leakage The Printed Circuit Board’s surface leakage effects should be estimated if the lowest possible input bias current is critical. Dry environment surface current increases further when the board is exposed to humidity, dust or chemical contamination. For harsh environment conditions, protecting the entire board surface (with all the exposed www.onsemi.com 14 NCS20081/2/4, NCV20081/2/4 amplifier parameters and to avoid high frequency interference issues, it is recommended that the PCB layout respects some basic guidelines: • A dedicated layer for the ground plane should be used whenever possible and all supply decoupling capacitors should connect to it by vias. • Copper traces should be as short as possible. • High current paths should not be shared by small signal or low current traces. • If present, switching power supply blocks should be kept away from the analog sensitive areas to avoid potential conducted and radiated noise issues. • When different circuit taxonomies share the same board, it is recommended to keep separated the power areas, the digital areas and the small signal analog areas. Small−signal parts in the signal path should be placed as close as possible to the opamp’s input pins. • Metal shielding the sensitive areas and the “offender” blocks may be required in some cases. metal pins and soldered areas) is advised. Conformal coating or potting the board in resin proves effective in most cases. An alternate solution for reduced leakage is the use of guard rings around sensitive pins and pads. A proper guard ring should have low impedance and be biased to the same voltage as the sensitive pin so no current flows in between. For an inverting amplifier, the non−inverting input is usually connected to supply’s ground (or virtual ground at half the rail voltage in single supply applications) so it can represent a good ring solution. When routing the PCB traces, create a closed perimeter around the inverting input pad (which carries the signal) and connect it to the non−inverting input. For a non−inverting amplifier, use a similarly shaped (rectangle or circle) copper trace around the non−inverting input pad (which carries the signal) and connect it to the inverting input pin, which presents a much lower impedance thanks to the feedback network. PCB Routing Recommendations Even when some operational amplifier is expected to amplify only the useful DC signal, it can also pick some high frequency noise altogether and amplify it accordingly, if the design allows it. In order to reach the specified operational In a sensitive application, a good PCB design can take longer but it will save troubleshooting time. Applications Example Second Order Active Low Pass Filter Using an opamp with a low input bias current allows the use of higher value resistors and smaller capacitors for the same filter application. As a trade−off for the increased impedance and lower consumption obtained, the higher value resistors may also bring higher noise and sensibility to board contamination, and possibly frequency response changes (the increased R*C time constant due to parasitic capacitances can change the gain vs. frequency plot). An example of an active low−pass filter using the NCS2008x operational amplifier can be found in Figure 31. The filter’s 3 dB Bandwidth is approximately 25 KHz, followed by a −40 dB/dec roll−off as in Figure 32. Such filters with flat response in the sampled signal band are recommended as a front−end for ADC’s to avoid aliasing. Figure 32. Filter’s Frequency Response Using the P−SPICE models provided by ON Semiconductor is recommended as a starting point for component selection, and then values can be further fine−tuned during bench testing the application. Figure 31. Second Order Active Low Pass Filter www.onsemi.com 15 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC−88A (SC−70−5/SOT−353) CASE 419A−02 ISSUE L SCALE 2:1 A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. G 5 4 −B− S 1 2 DATE 17 JAN 2013 DIM A B C D G H J K N S 3 D 5 PL 0.2 (0.008) B M M N INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 J GENERIC MARKING DIAGRAM* C K H XXXMG G SOLDER FOOTPRINT 0.50 0.0197 XXX = Specific Device Code M = Date Code G = Pb−Free Package 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. mm Ǔ ǒinches STYLE 1: PIN 1. BASE 2. EMITTER 3. BASE 4. COLLECTOR 5. COLLECTOR STYLE 2: PIN 1. ANODE 2. EMITTER 3. BASE 4. COLLECTOR 5. CATHODE STYLE 3: PIN 1. ANODE 1 2. N/C 3. ANODE 2 4. CATHODE 2 5. CATHODE 1 STYLE 4: PIN 1. SOURCE 1 2. DRAIN 1/2 3. SOURCE 1 4. GATE 1 5. GATE 2 STYLE 6: PIN 1. EMITTER 2 2. BASE 2 3. EMITTER 1 4. COLLECTOR 5. COLLECTOR 2/BASE 1 STYLE 7: PIN 1. BASE 2. EMITTER 3. BASE 4. COLLECTOR 5. COLLECTOR STYLE 8: PIN 1. CATHODE 2. COLLECTOR 3. N/C 4. BASE 5. EMITTER STYLE 9: PIN 1. ANODE 2. CATHODE 3. ANODE 4. ANODE 5. ANODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42984B STYLE 5: PIN 1. CATHODE 2. COMMON ANODE 3. CATHODE 2 4. CATHODE 3 5. CATHODE 4 Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. SC−88A (SC−70−5/SOT−353) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−5 CASE 483 ISSUE N 5 1 SCALE 2:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION A. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. D 5X NOTE 5 2X DATE 12 AUG 2020 0.20 C A B 0.10 T M 2X 0.20 T 5 B 1 4 2 B S 3 K DETAIL Z G A A TOP VIEW DIM A B C D G H J K M S DETAIL Z J C 0.05 H C SIDE VIEW SEATING PLANE END VIEW GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 0.95 0.037 MILLIMETERS MIN MAX 2.85 3.15 1.35 1.65 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 0_ 10 _ 2.50 3.00 1.9 0.074 5 5 XXXAYWG G 1 1 Analog 2.4 0.094 XXX = Specific Device Code A = Assembly Location Y = Year W = Work Week G = Pb−Free Package 1.0 0.039 XXX MG G Discrete/Logic XXX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) 0.7 0.028 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ARB18753C TSOP−5 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN6 1.6x1.6, 0.5P CASE 517AP ISSUE O 6 1 SCALE 4:1 A B D 2X 0.10 C PIN ONE REFERENCE 2X 0.10 C ÉÉ ÉÉ ÉÉ DETAIL A OPTIONAL CONSTRUCTION (A3) DETAIL B A 0.05 C A1 0.05 C SIDE VIEW DETAIL A 6X ÉÉÉ ÉÉÉ EXPOSED Cu TOP VIEW 6X C A1 SEATING PLANE 1 OPTIONAL CONSTRUCTION K 6 A3 DIM A A1 A3 b D E e D2 E2 K L L1 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.20 0.30 1.60 BSC 1.60 BSC 0.50 BSC 1.10 1.30 0.45 0.65 0.20 −−− 0.20 0.40 0.00 0.15 GENERIC MARKING DIAGRAM* 1 XX MG G 3 E2 6X MOLD CMPD DETAIL B D2 L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 E DATE 26 OCT 2007 4 6X XX = Specific Device Code M = Date Code G = Pb−Free Package b e (Note: Microdot may be in either location) 0.10 C A B BOTTOM VIEW 0.05 C *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 SOLDERMASK DEFINED MOUNTING FOOTPRINT* 1.26 6X 0.52 0.61 1.90 1 0.50 PITCH 6X 0.32 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON25711D 6 PIN UDFN, 1.6X1.6, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE L 14 1 SCALE 1:1 D DATE 03 FEB 2016 A B 14 8 A3 E H L 1 0.25 B M DETAIL A 7 13X M b 0.25 M C A S B S 0.10 X 45 _ M A1 e DETAIL A h A C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 6.50 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 14 14X 1.18 XXXXXXXXXG AWLYWW 1 1 1.27 PITCH 14X XXXXX A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 1: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 2: CANCELLED STYLE 3: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 4: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 5: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 6: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 7: PIN 1. ANODE/CATHODE 2. COMMON ANODE 3. COMMON CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. ANODE/CATHODE 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. COMMON CATHODE 12. COMMON ANODE 13. ANODE/CATHODE 14. ANODE/CATHODE STYLE 8: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS Micro8 CASE 846A−02 ISSUE K DATE 16 JUL 2020 SCALE 2:1 GENERIC MARKING DIAGRAM* 8 XXXX AYWG G 1 XXXX A Y W G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB14087C MICRO8 STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. N-SOURCE N-GATE P-SOURCE P-GATE P-DRAIN P-DRAIN N-DRAIN N-DRAIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−14 WB CASE 948G ISSUE C 14 DATE 17 FEB 2016 1 SCALE 2:1 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S DETAIL E K A −V− K1 J J1 ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE H G D DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ GENERIC MARKING DIAGRAM* 14 SOLDERING FOOTPRINT XXXX XXXX ALYWG G 7.06 1 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: 98ASH70246A DESCRIPTION: TSSOP−14 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−8 CASE 948S−01 ISSUE C DATE 20 JUN 2008 SCALE 2:1 K REF 8x 0.20 (0.008) T U 0.10 (0.004) S 2X L/2 8 0.20 (0.008) T U T U B −U− 1 J J1 4 V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ K1 K A −V− S S 5 L PIN 1 IDENT M SECTION N−N −W− C 0.076 (0.003) D −T− SEATING DETAIL E G PLANE 0.25 (0.010) N M DIM A B C D F G J J1 K K1 L M N F MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 --1.10 0.05 0.15 0.50 0.70 0.65 BSC 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.114 0.122 0.169 0.177 --0.043 0.002 0.006 0.020 0.028 0.026 BSC 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* XXX YWW AG G DETAIL E XXX A Y WW G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: STATUS: 98AON00697D ON SEMICONDUCTOR STANDARD NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 − Rev. 0 TSSOP−8 http://onsemi.com 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98AON00697D PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION. 18 APR 2000 A ADDED MARKING DIAGRAM INFORMATION. REQ. BY V. BASS. 13 JAN 2006 B CORRECTED MARKING DIAGRAM PIN 1 LOCATION AND MARKING. REQ. BY C. REBELLO. 13 MAR 2006 C REMOVED EXPOSED PAD VIEW AND DIMENSIONS P AND P1. CORRECTED MARKING INFORMATION. REQ. BY C. REBELLO. 20 JUN 2008 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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