DATA SHEET
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Precision Operational
Amplifier, 10 mV, Zero-Drift,
1.6 V to 5.5 V Supply,
1.5 MHz
NCS21801, NCS21802,
NCS21803, NCS21804
The NCS21801, NCS21802, NCS21803, and NCS21804 are
precision op amps featuring low input offset voltage and low offset
drift over time and temperature. The common mode voltage range
extends 100 mV beyond the supply rails, which makes it suitable for
both high−side and low−side current sensing applications.
The NCS2180x is available in single, dual, and quad channel
configurations. All versions are specified for operation from −40°C to
+125°C. NCV prefix parts are automotive grade 1 qualified and offer
performance over the extended temperature range from −40°C to
+150°C.
Features
•
•
•
•
•
•
•
•
•
•
5
5
1
SC−88A / SC70−5
CASE 419A−02
1
TSOP−5 / SOT23−5
CASE 483
1
1
SC−88 / SC70−6
CASE 419B−02
UDFN8
CASE 517AW
14
1
Micro8
CASE 846A−02
1
TSSOP−14 WB
CASE 948G
DEVICE MARKING INFORMATION
Input Offset Voltage: ±10 mV max
Offset Voltage Drift Over Temperature: ±5 nV/°C Typical
Common Mode Input Voltage Range: VSS – 0.1 V to VDD + 0.1 V
Supply Voltage Range: 1.8 V to 5.5 V
Extended Supply Voltage Range: 1.6 V to 5.5 V for TA = 0°C to 85°C
Unity Gain Bandwidth: 1.5 MHz
Quiescent Consumption: 100 mA Max per Channel
Enable Function Available on NCS21803
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
See general marking information in the device marking
section on page 2 of this data sheet.
PIN CONNECTIONS
See pin connections on page 3 of this data sheet.
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Applications
•
•
•
•
•
•
High−Side Current Sensing
Low−Side Current Sensing
Difference Amplifier
Instrumentation Amplifier
Power Management
Automotive
© Semiconductor Components Industries, LLC, 2020
September, 2021 − Rev. 6
1
Publication Order Number:
NCS21801/D
NCS21801, NCS21802, NCS21803, NCS21804
DEVICE MARKING INFORMATION
6
ACC\A/(YW)G
G
AAU(M)G
G
AAE(M)G
G
1
TSOP−5 / SOT23−5
CASE 483
SC−88A / SC70−5
CASE 419A−02
SC−88 / SC70−6 / SOT−363
CASE 419B−02
14
8
1
802
AYWG
G
AAJ
YM
804
ALYWG
G
1
UDFN8, 2x2, 0.5P
CASE 517AW
1
Micro8
CASE 846A−02
XX
A
Y
W
M
G or G
TSSOP−14 WB
CASE 948G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Channels
Enable
Package
Part Number
Marking
Shipping
SOT23−5 / TSOP−5
NCS21801SN2T1G
ACC
3000 / Tape & Reel
SC70−5 / SC−88−5 / SOT−353−5
NCS21801SQ3T2G
AAU
Yes
SC−88 / SC70−6 / SOT−363
NCS21803SQT2G
AAE
Dual
No
UDFN−8
NCS21802MUTBG
AAJ
3000 / Tape & Reel
Micro8
NCS21802DMR2G
802
4000 / Tape & Reel
Quad
No
TSSOP−14
NCS21804DTBR2G**
804
2500 / Tape & Reel
SOT23−5 / TSOP−5
NCV21801SN2T1G**
ACC
3000 / Tape & Reel
SC70−5 / SC−88−5 / SOT−353−5
NCV21801SQ3T2G
AAU
INDUSTRIAL AND CONSUMER
Single
No
AUTOMOTIVE QUALIFIED
Single
No
Dual
No
Micro8
NCV21802DMR2G
802
4000 / Tape & Reel
Quad
No
TSSOP−14
NCV21804DTBR2G**
804
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
** In development. Contact local sales office for more information.
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2
NCS21801, NCS21802, NCS21803, NCS21804
PIN CONNECTIONS
Single Channel Configuration
NCS21801
OUT
1
VSS
2
IN+
3
5 VDD
4
IN−
SOT23−5 / TSOP−5
IN+
1
VSS
2
IN−
3
Single Channel with Enable Configuration
NCS21803
5 VDD
4 OUT
SC70−5 / SC−88−5 / SOT−353−5
Dual Channel Configuration
NCS21802
OUT 1
1
IN− 1
2
−
IN+ 1
3
+
VSS
4
IN+
1
6 VDD
VSS
2
5 EN
IN−
3
4 OUT
SC88 / SC70−6 / SOT−363
Quad Channel Configuration
NCS21804
OUT 1
1
OUT 2
IN− 1
2
−
−
13 IN− 4
6
IN− 2
IN+ 1
3
+
+
12 IN+ 4
5
IN+ 2
VDD
4
IN+ 2
5
+
+
10 IN+ 3
IN− 2
6
−
−
9 IN− 3
OUT 2
7
8
VDD
7
−
+
UDFN8 / Micro8
14 OUT 4
11 VSS
8 OUT 3
TSSOP−14
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3
NCS21801, NCS21802, NCS21803, NCS21804
MAXIMUM RATINGS (Note 1)
Parameter
Symbol
Supply Voltage (VDD − VSS) (Note 1)
Rating
Unit
VS
−0.3 to 6
V
VIN+,VIN−, VEN
(VSS − 0.3) to (VDD + 0.3)
V
Differential Input Voltage
VIN+,VIN−
± (VDD – VSS + 0.3)
V
Output Voltage (Note 2)
VOUT
(VSS − 0.3) to (VDD + 0.3)
V
Output Short Circuit Current (Note 3)
IOUT
Continuous
Input Voltage (Note 2)
Input Current into Any Pin (Note 2)
IIN
±10
mA
TJ(max)
+150
°C
TSTG
−65 to +150
°C
Human Body Model (Note 4)
HBM
±2000
V
Charged Device Model (Note 4)
CDM
±1000
V
100
mA
Maximum Junction Temperature
Storage Temperature Range
ESD
Latch−up Current (Note 5)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for safe
operating parameters
2. Terminals are diode−clamped to the power−supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be
current limited to ±10 mA or less. Output terminals should not be driven by external sources.
3. Short circuits to either rail can cause an increase in the junction temperature. The total power dissipation must be limited to prevent the
junction temperature from exceeding the 150°C limit.
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC standard JS−001−2017 (AEC−Q100−002)
ESD Charged Device Model tested per JEDEC standard JS−002−2014 (AEC−Q100−011)
5. Latch−up Current tested per JEDEC standard: JESD78E.
THERMAL CHARACTERISTICS (Notes 6, 7)
qJA
YJT
YJB
Junction−to−Ambient
Thermal Resistance
Junction−to−Case Top
Thermal Characteristic
Junction−to−Board
Thermal Characteristic
TSOP−5 / SOT23−5
188
26
38
SC70−5 / SC−88−5 / SOT−353−5
241
46
64
SC−88 / SC70−6 / SOT−363
230
45
60
UDFN8
105
10
51
Micro8 / MSOP−8
105
24
96
TSSOP−14
86
9
53
Package
Unit
°C/W
6. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for safe
operating parameters
7. Mounted on a JESD51−7 thermal board, 2S2P, 1 in2 copper spreader area, 1 oz signal plane thickness
RECOMMENDED OPERATING RANGES
Parameter
Ambient Temperature
Common Mode Input Voltage
Supply Voltage (VDD − VSS)
Symbol
Conditions
Min
Max
Unit
TA
NCS prefix
NCV prefix
−40
125
°C
−40
150 (Note 8)
VCM
VS
Full temperature range
VSS – 0.1
VDD + 0.1
V
TA = 0 to 85°C
1.6
5.5
V
Full temperature range
1.8
5.5
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
8. Operation up to TA = 150°C is permitted, provided the total power dissipation is limited to prevent the junction temperature from exceeding
the 150°C absolute maximum limit.
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NCS21801, NCS21802, NCS21803, NCS21804
ELECTRICAL CHARACTERISTICS At TA = +25°C, Vs = 1.8 V to 5.5 V, and VCM = VOUT = mid−supply, unless otherwise noted.
Boldface limits apply over the specified temperature range, unless otherwise noted, guaranteed by characterization and/or design.
Parameter
Symbol
Conditions
Temp (5C)
Min
Typ
Max
Unit
INPUT
Input Offset Voltage
Input Offset Voltage Drift vs.
Temperature
Common Mode Rejection Ratio
VOS
dVOS/dT
CMRR
VS = 3.3 V
VS = 1.8 V to 5.5 V
VS = 1.8 V,
VCM = VSS − 0.1 V to VDD + 0.1 V
VS = 3.3 V,
VCM = VSS − 0.1 V to VDD + 0.1 V
VS = 5.5 V,
VCM = VSS − 0.1 V to VDD + 0.1 V
Input Bias Current (Note 9)
Input Offset Current
(Note 9)
Input Capacitance
IIB
±2
±10
mV
±5
±75
nV/°C
–40 to 150
±5
±75
25
106
–40 to 125
100
–40 to 150
100
25
113
–40 to 125
110
–40 to 150
110
25
111
–40 to 125
108
–40 to 150
108
25
IOS
CIN
25
–40 to 125
dB
131
134
137
±60
±200
–40 to 125
±600
–40 to 150
±5000
25
±60
±300
–40 to 125
±400
–40 to 150
±2500
Differential
25
5
Common mode
25
5
pA
pA
pF
ENABLE (Note 10)
Input Voltage Low Threshold
VEN−L
Shutdown
–40 to 125
Input Voltage High Threshold
VEN−H
Enabled
–40 to 125
Input Leakage Current
IEN
VSS +
0.5
V
VSS +
1.3
25
V
1
100
nA
OUTPUT CHARACTERISTICS
Open Loop Voltage Gain
AVOL
VS = 1.8 V
VS = 3.3 V, 5.5 V
25
108
–40 to 125
106
–40 to 150
106
25
120
–40 to 125
110
–40 to 150
110
133
dB
143
9. Guaranteed by characterization and/or design.
10. The enable function is available on NCS21803 only. The EN pin must be connected to a logic low or logic high voltage.
11. Shutdown Time (tOFF) and Enable Time (tON) are defined as the time between the 50% point of the signal applied to the EN pin and the
point at which the output voltage reaches within 10% of its final value.
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NCS21801, NCS21802, NCS21803, NCS21804
ELECTRICAL CHARACTERISTICS At TA = +25°C, Vs = 1.8 V to 5.5 V, and VCM = VOUT = mid−supply, unless otherwise noted.
Boldface limits apply over the specified temperature range, unless otherwise noted, guaranteed by characterization and/or design.
Parameter
Symbol
Conditions
Temp (5C)
Min
Typ
Max
Unit
5
mV
OUTPUT CHARACTERISTICS
Output Voltage High,
Referenced from VDD Supply
Rail
VDD −
VOH
IOUT = 30 mA
25
VS = 3.3 V, IOUT = 3 mA
Output Voltage Low,
Referenced to VSS Supply Rail
VOL −
VSS
IOUT = 30 mA
Output Current Sourcing
Capability
IO
10
–40 to 150
10
25
55
100
–40 to 125
125
–40 to 150
125
25
VS = 3.3 V, IOUT = 3 mA
1
–40 to 125
1
5
–40 to 125
10
–40 to 150
10
25
55
mV
100
–40 to 125
125
–40 to 150
125
mA
VS = 1.8 V
25
24
VS = 3.3 V
25
29
VS = 5.5 V
25
32
VS = 1.8 V
25
28
VS = 3.3 V
25
32
VS = 5.5 V
25
38
CL
AV = −1, VIN = 100 mVpp step
AV = 1, VIN = 100 mVpp step
25
400
125
pF
BW
CL = 20 pF
25
1.5
MHz
Gain Margin
AM
CL = 20 pF
25
6
dB
Phase Margin
FM
CL = 20 pF
25
50
°
Slew Rate
SR
25
0.7
V/ms
0.1%, AV = 1
25
20
ms
VIN * GAIN > VS
25
200
ms
NCS21802, NCS21804,
f = 10 kHz
25
90
dB
25
See Fig.
26
dB
Output Current Sinking
Capability
Capacitive Load Capability
IO
DYNAMIC RESPONSE
Unity Gain Bandwidth
Settling Time
Overload Recovery Time
ts
tOR
Channel Separation
EMI Rejection Ratio
EMIRR
NOISE
Voltage Noise Density
Voltage Noise, Peak−to−Peak
Current Noise Density
eN
VS = 3.3, fin = 1 kHz
25
42
nV/√Hz
eP−P
fin = 0.1 Hz to 10 Hz
25
400
nVPP
fin = 1 kHZ
25
445
fA/√Hz
iN
9. Guaranteed by characterization and/or design.
10. The enable function is available on NCS21803 only. The EN pin must be connected to a logic low or logic high voltage.
11. Shutdown Time (tOFF) and Enable Time (tON) are defined as the time between the 50% point of the signal applied to the EN pin and the
point at which the output voltage reaches within 10% of its final value.
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NCS21801, NCS21802, NCS21803, NCS21804
ELECTRICAL CHARACTERISTICS At TA = +25°C, Vs = 1.8 V to 5.5 V, and VCM = VOUT = mid−supply, unless otherwise noted.
Boldface limits apply over the specified temperature range, unless otherwise noted, guaranteed by characterization and/or design.
Parameter
Symbol
Conditions
Temp (5C)
Min
Typ
Max
Unit
75
105
mA
POWER SUPPLY
Quiescent Current
IQ
NCS21801, NCS2803,
no load
NCS21802, NCS21804,
per channel, no load
Quiescent Current in Shutdown
(Notes 9, 10)
Power Supply Rejection Ratio
IQSD
PSRR
Power Up Time
Per channel
25
–40 to 125
130
–40 to 150
200
25
75
–40 to 125
125
–40 to 150
150
25
VS = 1.8 V to 5.5 V
100
5
50
–40 to 85
75
–40 to 125
200
25
115
–40 to 125
110
–40 to 150
110
mA
nA
140
dB
ms
NCS21801, NCS21803
25
50
NCS21802, NCS21804
25
40
Enable Time (Note 10, 11)
tON
25
50
ms
Shutdown Time (Note 10, 11)
tOFF
25
3
ms
9. Guaranteed by characterization and/or design.
10. The enable function is available on NCS21803 only. The EN pin must be connected to a logic low or logic high voltage.
11. Shutdown Time (tOFF) and Enable Time (tON) are defined as the time between the 50% point of the signal applied to the EN pin and the
point at which the output voltage reaches within 10% of its final value.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCS21801, NCS21802, NCS21803, NCS21804
ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = 1.6 V, and VCM = VOUT = mid−supply, unless otherwise noted. Boldface
limits apply over the specified temperature range, TA = 0°C to 85°C, guaranteed by characterization and/or design.
Parameter
Symbol
Conditions
Temp (5C)
Min
Typ
Max
Unit
INPUT
Input Offset Voltage
Input Offset Voltage Drift vs.
Temperature
Common Mode Rejection Ratio
VOS
25
±3
±13
mV
dVOS/dT
0 to 85
±5
±75
nV/°C
CMRR
Input Bias Current
(Note 12)
IIB
Input Offset Current
(Note 12)
IOS
Input Capacitance
CIN
VCM = VSS − 0.1 V to VDD + 0.1 V
25
96
0 to 85
94
25
dB
123
±30
0 to 85
±160
pA
±250
25
±36
0 to 85
±200
pA
±250
Differential
25
5
Common mode
25
5
pF
ENABLE (Note 14)
Input Voltage Low Threshold
VEN−L
Shutdown
0 to 85
Input Voltage High Threshold
VEN−H
Enabled
0 to 85
Input Leakage Current
VSS +
0.5
V
VSS +
1.3
IEN
25
Open Loop Voltage Gain
AVOL
25
106
0 to 85
104
Output Voltage High,
Referenced from VDD
Supply Rail
VDD −
VOH
V
1
100
nA
OUTPUT CHARACTERISTICS
IOUT = 30 mA
25
1
0 to 85
IOUT = 3 mA
25
VOL −
VSS
IOUT = 30 mA
25
85
25
mV
130
150
1
5
75
130
0 to 85
IOUT = 3 mA
5
10
0 to 85
Output Voltage Low,
Referenced to VSS Supply Rail
dB
128
mV
10
0 to 85
150
mA
Output Current Sourcing
Capability
Io
25
15
Output Current Sinking
Capability
Io
25
21
Capacitive Load Capability
CL
AV = −1, VIN = 100 mVpp step
AV = 1, VIN = 100 mVpp step
25
400
125
pF
BW
CL = 20 pF
25
1.4
MHz
Gain Margin
AM
CL = 20 pF
25
6
dB
Phase Margin
FM
CL = 20 pF
25
50
°
Slew Rate
SR
25
0.7
V/ms
DYNAMIC RESPONSE
Unity Gain Bandwidth
12. Guaranteed by design and/or characterization.
13. The enable function is available on NCS21803 only. The EN pin must be connected to a logic low or logic high voltage.
14. Shutdown Time (tOFF) and Enable Time (tON) are defined as the time between the 50% point of the signal applied to the EN pin and the
point at which the output voltage reaches within 10% of its final value.
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NCS21801, NCS21802, NCS21803, NCS21804
ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = 1.6 V, and VCM = VOUT = mid−supply, unless otherwise noted. Boldface
limits apply over the specified temperature range, TA = 0°C to 85°C, guaranteed by characterization and/or design.
Parameter
Symbol
Conditions
Temp (5C)
Min
Typ
Max
Unit
DYNAMIC RESPONSE
Settling Time
Overload Recovery Time
ts
tOR
Channel Separation
EMI Rejection Ratio
0.1%, AV = 1
25
20
ms
VIN * GAIN > VS
25
200
ms
NCS21802, NCS21804,
f = 10 kHz
25
90
dB
25
See Fig.
26
dB
EMIRR
NOISE
Voltage Noise Density
Voltage Noise, Peak−to−Peak
Current Noise Density
eN
fin = 1 kHz
25
53
nV/√Hz
fin = 0.1 Hz to 10 Hz
25
400
nVPP
iN
fin = 1 kHz
25
450
fA/√Hz
IQ
NCS21801, NCS21803,
no load
25
70
eP−P
POWER SUPPLY
Quiescent Current
NCS21802, NCS21804,
per channel, no load
Quiescent Current in
Shutdown (Notes 12, 13)
Power Supply Rejection Ratio
IQSD
Per channel
0 to 85
25
65
0 to 85
Power Up Time
90
105
25
VS = 1.6 V to 5.5 V
mA
110
5
0 to 85
PSRR
95
50
nA
75
25
115
0 to 85
110
135
dB
ms
NCS21801, NCS21803
25
75
NCS21802, NCS21804
25
40
Enable Time (Notes 13, 14)
tON
25
75
ms
Shutdown Time
(Notes 13, 14)
tOFF
25
5
ms
12. Guaranteed by design and/or characterization.
13. The enable function is available on NCS21803 only. The EN pin must be connected to a logic low or logic high voltage.
14. Shutdown Time (tOFF) and Enable Time (tON) are defined as the time between the 50% point of the signal applied to the EN pin and the
point at which the output voltage reaches within 10% of its final value.
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NCS21801, NCS21802, NCS21803, NCS21804
TYPICAL CHARACTERISTICS
Typical Performance at TA = 25°C, VCM = mid−supply, CL = 20 pF, RL = 10 kW to mid−supply, unless otherwise noted
40
40
Sample size = 98
Number of Amplifiers
Number of Amplifiers
30
25
20
15
10
30
25
20
15
10
5
5
0
0
-5
-4
-3
-2 -1
0
1
2
Input Offset Voltage (mV)
Sample size = 101
TA = -40 to 125°C
35
35
3
4
-40
5
Figure 1. Input Offset Voltage Distribution with
3.3 V Supply
40
Figure 2. Input Offset Voltage Drift Distribution
with 3.3 V Supply
25
30
Sample size = 101
TA = -40 to 125°C
Number of Amplifiers
Sample size = 98
Number of Amplifiers
-30 -20 -10
0
10 20 30
Input Offset Voltage Drift (nV/5C)
25
20
15
10
5
20
15
10
5
0
0
-5
-4
-3
-2 -1
0
1
2
Input Offset Voltage (mV)
3
4
-40
5
Figure 3. Input Offset Voltage Distribution with
1.6 V Supply
-30 -20 -10
0
10 20 30
Input Offset Voltage Drift (nV/5C)
40
Figure 4. Input Offset Voltage Drift Distribution
with 1.6 V Supply
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NCS21801, NCS21802, NCS21803, NCS21804
TYPICAL CHARACTERISTICS
Typical Performance at TA = 25°C, VCM = mid−supply, CL = 20 pF, RL = 10 kW to mid−supply, unless otherwise noted
10
10
VS = 5.5 V
5 units
VS = 1.8 V
5 units
8
Input Offset Voltage (μV)
Input Offset Voltage (μV)
8
6
4
2
0
-2
-4
-6
6
4
2
0
-2
-4
-6
-8
-8
-10
-50
-25
0
25
50
75 100
Temperature (°C)
125
-10
150
-50
Figure 5. Input Offset Voltage vs. Temperature
at 5.5 V Supply
25
50
75 100
Temperature (°C)
125
150
10
VS = 5.5 V
5 units
Input Offset Voltage (μV)
Input Offset Voltage (μV)
0
Figure 6. Input Offset Voltage vs. Temperature
at 1.8 V Supply
10
8
-25
6
4
2
0
-2
-4
-6
VS = 1.6 V
5 units
8
6
4
2
0
-2
-4
-6
-8
-8
-10
-10
-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Common Mode Input Voltage (V)
-0.3
Figure 7. Input Offset Voltage vs. Common
Mode Voltage at 5.5 V Supply
0
0.3
0.6
0.9
1.2
1.5
Common Mode Input Voltage (V)
1.8
Figure 8. Input Offset Voltage vs. Common
Mode Voltage at 1.6 V Supply
www.onsemi.com
11
NCS21801, NCS21802, NCS21803, NCS21804
TYPICAL CHARACTERISTICS
Typical Performance at TA = 25°C, VCM = mid−supply, CL = 20 pF, RL = 10 kW to mid−supply, unless otherwise noted
120
30
20
PHASE
10
80
Gain (dB)
Gain (dB) and Phase (°)
100
GAIN
60
40
20
Gain, VS = 1.6 V
Phase, VS = 1.6 V
Gain, VS = 5.5 V
Phase, VS = 5.5 V
0
-20
10
100
1K
10K
100K
Frequency (Hz)
0
-10
-20
VS = 3.3 V
AV = 1 V/V
AV = -1 V/V
AV = 10 V/V
-30
-40
-50
1M
10
10M
200
3000
IIB+
IIBIOS
VS = 5.5 V
100
IIB+, VS = 1.8 V
IIB-, VS = 1.8 V
IOS, VS = 1.8 V
2500
Input Current (pA)
Input Current (pA)
10K
100K
1M
10M
Figure 10. Closed Loop Gain vs. Frequency
50
0
-50
-100
IIB+, VS = 5.5 V
IIB-, VS = 5.5 V
IOS, VS = 5.5 V
2000
1500
1000
500
0
-150
-500
-50
-200
-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Common Mode Input Voltage (V)
Figure 11. Input Bias Current and Input Offset
Current vs. Common Mode Input Voltage
-25
0
25
50
75 100
Temperature (°C)
125
150
Figure 12. Input Bias Current and Input Offset
Current vs. Temperature
Output Voltage Low to VSS (V)
1
Output Voltage Low to VSS (V)
1K
Frequency (Hz)
Figure 9. Open Loop Gain and Phase vs.
Frequency
150
100
0.1
TA = -40°C
TA = 0°C
TA = 25°C
TA = 85°C
1
0.1
TA = 0°C
TA = 25°C
TA = 85°C
0.01
0.01
0
10
20
30
Output Current (mA)
0
40
4
8
12
16
20
Output Current (mA)
Figure 13. Output Voltage Low vs. Output
Current at 5.5 V Supply
Figure 14. Output Voltage Low vs. Output
Current at 1.6 V Supply
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12
24
NCS21801, NCS21802, NCS21803, NCS21804
TYPICAL CHARACTERISTICS
Output Voltage High from VDD (V)
Output Voltage High from VDD (V)
Typical Performance at TA = 25°C, VCM = mid−supply, CL = 20 pF, RL = 10 kW to mid−supply, unless otherwise noted
1
0.1
TA = -40°C
TA = 0°C
TA = 25°C
TA = 85°C
1
0.1
TA = 0°C
TA = 25°C
TA = 85°C
0.01
0.01
0
10
20
30
40
0
4
Output Current (mA)
Figure 15. Output Voltage High vs. Output
Current at 5.5 V Supply
140
VS = 1.6 V
VS = 5.5 V
100
PSRR (dB)
CMRR (dB)
PSRR+
120
80
60
40
20
PSRR+, VS = 1.8 V
PSRR-, VS = 1.8 V
PSRR+, VS = 5.5 V
PSRR-, VS = 5.5 V
80
PSRR-
60
40
20
0
0
-20
-20
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
Figure 17. CMRR vs. Frequency
100
1k
10k 100k
Frequency (Hz)
1M
10M
Figure 18. PSRR vs. Frequency
1000
400
VS = 1.6 V
VS = 5.5 V
300
Noise Density (nV/√Hz)
0.1 Hz to 10 Hz Noise (nV)
20
Figure 16. Output Voltage High vs. Output
Current at 1.6 V Supply
120
100
8
12
16
Output Current (mA)
200
100
0
-100
VS = 1.6 V
VS = 5.5 V
100
-200
-300
-400
10
10
Time (1s/div)
Figure 19. 0.1 Hz to 10 Hz Noise
100
1k
10k
Frequency (Hz)
100k
Figure 20. Voltage Noise Density vs.
Frequency
www.onsemi.com
13
1M
NCS21801, NCS21802, NCS21803, NCS21804
TYPICAL CHARACTERISTICS
600
1
VS = 1.6 V
VS = 5.5 V
AV = 1 V/V
RIN = 100 kΩ
550
500
0.1
450
0.01
400
0.001
350
300
0.0001
10
100
1K
10K
100K
1
10
Frequency (Hz)
Figure 22. THD+n vs. Frequency
80
10K
AV = -1, VS = 1.6 V
AV = -1, VS = 5.5 V
AV = 1, VS = 1.6 V
AV = 1, VS = 5.5 V
60
1K
Overshoot (%)
Impedance (Ω)
70
100
VS = 1.6 V
VS = 3.3 V
VS = 5.5 V
10
1
1K
100
Frequency (Hz)
Figure 21. Current Noise Density vs.
Frequency
50
40
30
20
VIN = 100 mVpp step
Above 40% overshoot
not recommended
10
0
10
100
1K
10K 100K 1M
Frequency (Hz)
10M 100M
0
Figure 23. Open Loop Output Impedance vs.
Frequency
50
100 150 200 250 300
Load Capacitance (pF)
350
400
Figure 24. Small Signal Overshoot vs. Load
Capacitance
120
140
VS = 1.6 V
VS = 1.6 V
VS = 5.5 V
120
VS = 5.5 V
100
100
EMIRR (dB)
Channel Separation (dB)
VS = 1.6 V, AV = 1
VS = 1.6 V, AV = -1
VS = 5.5 V, AV = 1
VS = 5.5 V, AV = -1
VIN = 0.5 Vrms
THD+n (%)
Current Noise Denisty (fA/√Hz)
Typical Performance at TA = 25°C, VCM = mid−supply, CL = 20 pF, RL = 10 kW to mid−supply, unless otherwise noted
80
60
80
60
40
40
20
20
0
0
10
100
1K
10K
100K
1M
10M
10M
Frequency (Hz)
Figure 25. Channel Separation vs. Frequency
100M
1B
Frequency (Hz)
Figure 26. EMIRR vs. Frequency
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14
10B
NCS21801, NCS21802, NCS21803, NCS21804
TYPICAL CHARACTERISTICS
Typical Performance at TA = 25°C, VCM = mid−supply, CL = 20 pF, RL = 10 kW to mid−supply, unless otherwise noted
160
VS = 1.6 V
VS = 1.8 V
VS = 3.3 V
VS = 5.5 V
100
Supply Current (μA)
Supply Current (μA)
120
80
60
140
120
100
80
40
60
20
40
-50
0
50
100
Temperature (°C)
1.5
150
0.08
0.08
0.06
0.06
0.04
0.04
0.02
Input
Output
-0.02
-0.06
-0.08
Time (2 ms/div)
2
2
1.5
1.5
1
1
Output
-0.5
Output
Time (2 ms/div)
0.5
0
-0.5
-1
-1
-1.5
-1.5
-2
5.5
Figure 30. Non−Inverting Small Signal Step
Response with VS = 3.3 V (Split Supplies)
Voltage (V)
Voltage (V)
Figure 29. Inverting Small Signal Step
Response with VS = 3.3 V (Split Supplies)
0
5
-0.02
-0.06
Input
3 3.5 4 4.5
Supply Voltage (V)
Input
0
-0.04
0.5
2.5
0.02
-0.04
-0.08
2
Figure 28. Quiescent Current Per Channel vs.
Supply Voltage
Input (V)
Input (V)
Figure 27. Quiescent Current Per Channel vs.
Temperature
0
TA = -40°C
TA = 0°C
TA = 25°C
TA = 125°C
TA = 150°C
-2
Time (5 ms/div)
Figure 31. Inverting Large Signal Step
Response with VS = 3.3 V (Split Supply)
Input
Output
Time (5 ms/div)
Figure 32. Non−Inverting Large Signal Step
Response with VS =3.3 V (Split Supply)
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15
NCS21801, NCS21802, NCS21803, NCS21804
TYPICAL CHARACTERISTICS
4
80
2
40
0
0
-2
-40
Supply Voltage
-4
Δ Output from
Final Value
-6
Time (10 μs/div)
-80
-120
2
40
1.5
30
1
20
0.5
10
0
0
-0.5
NCS21802, NCS21804
-10
-1
Supply Voltage
-20
-1.5
Δ Output from
Final Value
-30
-2
-40
Time (10 μs/div)
Figure 33. Power Up Time with 5.5 V Supply
Figure 34. Power Up Time with 1.6 V Supply
0.5
2.5
Δ Output from Final Value (mV)
120
Supply Voltage (V)
6
Δ Output from Final Value (mV)
Supply Voltage (V)
Typical Performance at TA = 25°C, VCM = mid−supply, CL = 20 pF, RL = 10 kW to mid−supply, unless otherwise noted
2.5
5
2
0
2
Output
-1
Input (V)
Input
1
Output (V)
Input (V)
1.5
-1.5
0.5
-2
0
2
0.5
1
0
0
-0.5
-1
-1
-2
-1.5
-3
AV = -1
-2.5
-2.5
Time (50 μs/div)
-0.5
-2
AV = -10
3
1
-0.5
1.5
4
ΔOutput from
Final Value
ΔOutput from Final Value (mV)
Input
-4
-5
Time (20 μs/div)
Figure 36. Settling Time with VS = 3.3 V (Split
Supply)
Figure 35. Output Overload Recovery with VS
= 3.3 V (Split Supply)
5
2
VS = 3.3 V
Unity Gain Bandiwdth (MHz)
0
Gain (dB)
-5
-10
-15
AV = 1
VS = 3.3 V
VIN = 2 Vpp
-20
100
1.6
1.4
1.2
1
-25
10
1.8
1K
10K
100K
1M
0
10M
0.5
1
1.5
2
2.5
3
Frequency (Hz)
Input Common Mode Voltage (V)
Figure 37. Large Signal Gain vs. Frequency
Figure 38. Unity Gain Bandwidth vs. Input Common
Mode Voltage
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16
NCS21801, NCS21802, NCS21803, NCS21804
TYPICAL CHARACTERISTICS
Typical Performance at TA = 25°C, VCM = mid−supply, CL = 20 pF, RL = 10 kW to mid−supply, unless otherwise noted
600
NCS21803
Shutdown Current (nA)
500
400
300
200
100
0
-50
0
50
100
150
Temperature (°C)
Figure 39. Shutdown Current vs. Temperature
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17
NCS21801, NCS21802, NCS21803, NCS21804
TYPICAL CHARACTERISTICS
Typical Performance at TA = 25°C, VCM = mid−supply, CL = 20 pF, RL = 10 kW to mid−supply, unless otherwise noted
1
3
VS = 5.5 V
RL = 10 kΩ to VSS
NCS21803
1.8
0.6
0.4
Enable
Output
0.6
Voltage (V)
Voltage (V)
1.2
0
-0.6
Enable
Output
0.2
0
-0.2
-1.2
-0.4
-1.8
-0.6
-2.4
-0.8
-3
VS = 1.6 V
RL = 10 kΩ to VSS
0.8
-1
Time (5 μs/div)
Time (5 μs/div)
Figure 41. Shutdown Time with VS = 1.6 V
(Split Supply)
60
2
40
1
20
0
0
-1
-2
VS = 5.5 V
NCS21803
Enable
Output
-20
-40
Enable Voltage (V)
3
Δ Output from Final Value (mV)
Enable Voltage (V)
Figure 40. Shutdown Time with VS = 5.5 V
(Split Supply)
50
0.8
40
0.6
30
0.4
20
0.2
10
0
0
-10
-0.2
-0.4
-0.6
VS = 1.6 V
NCS21803
Enable
Output
-0.8
-60
-3
1
-1
Time (30 μs/div)
Figure 42. Enable Time with VS = 5.5 V
(Split Supply)
Time (30 μs/div)
Figure 43. Enable Time with VS = 1.6 V
(Split Supply)
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18
-20
-30
-40
-50
Δ Output from Final Value (mV)
2.4
NCS21801, NCS21802, NCS21803, NCS21804
APPLICATIONS INFORMATION
Architecture
The NCS21801, NCS21802, NCS21803, and NCS21804
precision amplifiers feature low input offset voltage and
zero−drift over temperature. The input common mode
voltage range extends 100 mV beyond the rails, allowing for
measurements at ground or the supply voltage. These
characteristics make the NCS21801 series well−suited for
applications such as current sensing and sensor interface.
The NCS21803 additionally features an enable pin that
allows the amplifier to enter shutdown mode to reduce
current consumption in low power applications.
The low input offset voltage and zero−drift characteristics
of amplifiers in the NCS21801 series is achieved through the
chopper−stabilized architecture. Unlike the classical
chopper architecture, the chopper−stabilized architecture
has two signal paths to take advantage of both precision and
speed.
NCS21801
Main amp
High frequency path
IN+
+
IN−
− +
−
OUT
Low frequency path
Chopper
+
−
−
+
Nulling amp
Chopper
RC notch filter
RC notch filter
Figure 44. Simplified Schematic of the Chopper−stabilized Amplifier Architecture
where the signal is low frequency and the differential
voltage is relatively small.
Both internal amplifiers have specialized circuitry to
maintain nearly constant bandwidth, noise, and slew rate
over the entire common mode voltage range. This also
improves the overall input offset voltage, PSRR, and CMRR
performance, while significantly reducing the THD+noise
level. These characteristics are very useful in signal
processing.
In Figure 44, the lower signal path is where the chopper
samples the input offset voltage, which is then used to
correct the offset at the output. The offset correction occurs
at a frequency of 100 kHz. Due to this periodic sampling, the
chopper−stabilized architecture is optimized for best
performance at frequencies up to the related Nyquist
frequency (1/2 of the offset correction frequency). As the
signal frequency exceeds the Nyquist frequency, 50 kHz,
aliasing may occur at the output. This is an inherent
limitation of all chopper and chopper−stabilized
architectures. Nevertheless, the NCS2180x is designed to
minimize aliasing beyond the Nyquist frequency.
ON Semiconductor’s patented approach utilizes two
cascaded, symmetrical, RC notch filters tuned to the
chopper frequency and its fifth harmonic to reduce aliasing
effects.
The feed−forward path, which is shown as the upper
signal path of the block diagram in Figure 44, is the high
speed signal path that extends the gain bandwidth to 1.5
MHz. Not only does this help retain high frequency
components of the input signal, but it also improves the loop
gain at low frequencies. This is especially useful for
low−side current sensing and sensor interface applications
Input Offset Voltage
Input offset voltage is an intrinsic op amp characteristic
that arises from mismatches in the IN+ and IN− paths. Since
the NCS2180x series amplifiers have such low input offset
voltage to begin with, external factors can have a non−trivial
contribution to the effective input offset voltage. Conditions
created by the physical environment can create package
stress, thereby influencing the input offset voltage. These
factors include air flow and PCB construction. Taking these
factors into consideration, the input offset voltage
performance should be validated in the application
environment.
www.onsemi.com
19
NCS21801, NCS21802, NCS21803, NCS21804
EMIRR
battery−powered applications. The output becomes high
impedance. Setting the EN pin to logic high enables the
output again, with the output reaching the final value (±1%)
according the specified enable time. A floating EN pin
results in an indeterminate output state.
The NCS21801 series has built−in input filters to reduce
high frequency EMI frequency signals before they enter the
amplifier. Under normal circumstances, P−N junctions
within the silicon can rectify these high frequency signals,
and the effect can be seen as a DC offset at the output. Since
this added offset can have a noticeable effect on high
precision measurements, EMI rejection ratio (EMIRR) can
be used to quantify the robustness of an amplifier to these
signals.
Layout Recommendations
Bypass capacitors of 0.1 mF to ground should be placed as
close as possible to the supply pins.
The UDFN8 package has an exposed leadframe die pad on
the underside of the package. This pad should be soldered to
the PCB, as shown in the recommended soldering footprint
in the Package Dimensions section of this datasheet. The
center pad can be electrically connected to VSS or it may be
left floating. When connected to VSS, the center pad acts as
a heat sink, improving the thermal resistance of the part.
Enable Function
The enable pin on NCS21803 allows the user to put the
amplifier into shutdown mode when it is not is use. Setting
EN to the logic low level reduces the current consumption
down to less than 300 nA, which is useful for portable and
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20
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
SCALE 2:1
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DATE 17 JAN 2013
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
B
M
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
J
GENERIC MARKING
DIAGRAM*
C
K
H
XXXMG
G
SOLDER FOOTPRINT
0.50
0.0197
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
mm Ǔ
ǒinches
STYLE 1:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 2:
PIN 1. ANODE
2. EMITTER
3. BASE
4. COLLECTOR
5. CATHODE
STYLE 3:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
STYLE 4:
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
5. GATE 2
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
3. EMITTER 1
4. COLLECTOR
5. COLLECTOR 2/BASE 1
STYLE 7:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 8:
PIN 1. CATHODE
2. COLLECTOR
3. N/C
4. BASE
5. EMITTER
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42984B
STYLE 5:
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
4. CATHODE 3
5. CATHODE 4
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SC−88A (SC−70−5/SOT−353)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
1
SCALE 2:1
DATE 11 DEC 2012
2X
aaa H D
D
H
A
D
6
5
GAGE
PLANE
4
1
2
L
L2
E1
E
DETAIL A
3
aaa C
2X
bbb H D
2X 3 TIPS
e
B
6X
b
ddd
TOP VIEW
C A-B D
M
A2
DETAIL A
A
6X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
ccc C
A1
SIDE VIEW
C
SEATING
PLANE
END VIEW
c
RECOMMENDED
SOLDERING FOOTPRINT*
6X
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
GENERIC
MARKING DIAGRAM*
6
XXXMG
G
6X
0.30
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
0.66
1
2.50
0.65
PITCH
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*Date Code orientation and/or position may
vary depending upon manufacturing location.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
6. ANODE
STYLE 5:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
6. CATHODE 2
STYLE 7:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
4. SOURCE 1
5. DRAIN 1
6. GATE 2
STYLE 8:
CANCELLED
STYLE 9:
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
5. BASE 2
6. COLLECTOR 2
STYLE 10:
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
4. DRAIN 1
5. DRAIN 2
6. GATE 2
STYLE 11:
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
STYLE 12:
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
STYLE 13:
PIN 1. ANODE
2. N/C
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 14:
PIN 1. VREF
2. GND
3. GND
4. IOUT
5. VEN
6. VCC
STYLE 15:
PIN 1. ANODE 1
2. ANODE 2
3. ANODE 3
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
STYLE 16:
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
5. EMITTER 1
6. COLLECTOR 1
STYLE 17:
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
5. EMITTER 2
6. COLLECTOR 1
STYLE 18:
PIN 1. VIN1
2. VCC
3. VOUT2
4. VIN2
5. GND
6. VOUT1
STYLE 19:
PIN 1. I OUT
2. GND
3. GND
4. V CC
5. V EN
6. V REF
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 21:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. N/C
6. CATHODE 1
STYLE 22:
PIN 1. D1 (i)
2. GND
3. D2 (i)
4. D2 (c)
5. VBUS
6. D1 (c)
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
4. N/C
5. CH2
6. N/C
STYLE 24:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 25:
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
5. EMITTER
6. COLLECTOR 1
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 29:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
STYLE 30:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN8, 2x2
CASE 517AW
ISSUE A
1
SCALE 2:1
ÇÇ
ÇÇ
E
DETAIL A
ALTERNATE
CONSTRUCTIONS
0.10 C
2X
L
L
L1
PIN ONE
REFERENCE
2X
B
A
D
DATE 13 NOV 2015
0.10 C
TOP VIEW
DETAIL B
A
0.10 C
A3
A1
0.08 C
A1
SIDE VIEW
NOTE 4
C
D2
DETAIL A
1
8X
4
SEATING
PLANE
5
e
e/2
A3
ALTERNATE
CONSTRUCTION
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.18
0.30
2.00 BSC
1.50
1.70
2.00 BSC
0.80
1.00
0.50 BSC
0.20
0.45
−−−
0.15
GENERIC
MARKING DIAGRAM*
8X
1
b
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
1.73
PACKAGE
OUTLINE
DETAIL B
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
L
E2
8
ÇÇ
ÇÇ
ÉÉ
MOLD CMPD
EXPOSED Cu
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINALS AND IS MEASURED BETWEEN 0.15
AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
8X
0.50
XX MG
G
XX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
2.30
1.00
1
8X
0.50
PITCH
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34462E
UDFN8, 2X2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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