NCS325SN2T1G

DATA SHEET www.onsemi.com Operational Amplifier, Precision, Zero-Drift, 50 mV Offset, 0.25 mV/5C, 35 mA NCS325, NCS2325, NCS4325 1 Features Low Offset Voltage: 14 mV typ, 50 mV max at 25°C for NCS325 Zero Drift: 0.25 mV/°C max Low Noise: 1 mVpp, 0.1 Hz to 10 Hz Quiescent Current: 21 mA typ, 35 mA max at 25°C Supply Voltage: 1.8 V to 5.5 V Rail−to−Rail Input and Output Internal EMI Filtering These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • • • • • • 5 TSOP−5 (SOT23−5) SN SUFFIX CASE 483 32A AYWG G 1 8 The NCS325, NCS2325 and NCS4325 are CMOS operational amplifiers providing precision performance. The Zero−Drift architecture allows for continuous auto−calibration, which provides very low offset, near−zero drift over time and temperature, and near flat 1/f noise at only 35 mA (max) quiescent current. These benefits make these devices ideal for precision DC applications. These op amps provide rail−to−rail input and output performance and are optimized for low voltage operation as low as 1.8 V and up to 5.5 V. The single channel NCS325 is available in the space−saving SOT23−5 package. The dual channel NCS2325 is available in Micro8 and SOIC−8. The quad channel NCS4325 is available in SOIC−14. • • • • • • • • MARKING DIAGRAMS 1 SOIC−8 D SUFFIX CASE 751 N2325 AYWW G 1 8 1 MSOP−8 DM SUFFIX CASE 846A 2325 AYWG G 1 14 1 SOIC−14 D SUFFIX CASE 751A NCS4325G AWLYWW 1 A = Assembly Location Y = Year WL = Wafer Lot W or WW = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Battery Powered Instruments Temperature Measurements Transducer Applications Electronic Scales Medical Instrumentation Current Sensing © Semiconductor Components Industries, LLC, 2017 February, 2022 − Rev. 6 1 Publication Order Number: NCS325/D NCS325, NCS2325, NCS4325 PIN CONNECTIONS Dual Channel Single Channel NCS325 OUT 1 5 VDD OUT 1 1 IN− 1 2 − IN+ 1 3 + − 2 + VSS IN+ 3 4 Quad Channel NCS4325 NCS2325 IN− SOT23 VSS 4 8 VDD 7 OUT 2 IN− 1 2 − − 13 IN− 4 − 6 IN− 2 IN+ 1 3 + + 12 IN+ 4 + 5 IN+ 2 VDD 4 IN+ 2 5 + + 10 IN+ 3 IN− 2 6 − − 9 IN− 3 8 OUT 3 SOIC−8, MSOP−8 OUT 1 1 14 OUT 4 11 OUT 2 7 VSS SOIC14 ORDERING INFORMATION Configuration Device Package Shipping† Single NCS325SN2T1G SOT23−5 / TSOP−5 3000 / Tape & Reel Dual Quad NCS2325DR2G SOIC−8 3000 / Tape & Reel NCS2325DMR2G Micro8 / MSOP−8 4000 / Tape & Reel NCS4325DR2G SOIC−14 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 2 NCS325, NCS2325, NCS4325 ABSOLUTE MAXIMUM RATINGS Over operating free−air temperature, unless otherwise stated. Parameter Supply Voltage Rating Unit 6 V INPUT AND OUTPUT PINS Input Voltage (Note 1) (VSS) − 0.3 to (VDD) + 0.3 V Input Current (Note 1) ±10 mA Output Short Circuit Current (Note 2) Continuous TEMPERATURE Operating Temperature −40 to +150 °C Storage Temperature −65 to +150 °C Junction Temperature +150 °C Human Body Model (HBM) 4000 V Machine Model (MM) 200 V 100 mA ESD RATINGS (Note 3) OTHER RATINGS Latch−up Current (Note 4) MSL Level 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Input terminals are diode−clamped to the power−supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be current limited to 10 mA or less 2. Short−circuit to ground. 3. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (JEDEC standard: JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (JEDEC standard: JESD22−A115) 4. Latch−up Current tested per JEDEC standard: JESD78. THERMAL INFORMATION Thermal Metric Symbol Package Value Unit qJA SOT23−5 / TSOP−5 235 °C/W Micro8 / MSOP−8 298 SOIC−8 250 SOIC−14 216 Junction to Ambient (Note 5) 5. As mounted on an 80x80x1.5 mm FR4 PCB with 650 51.1, 51.2, 51.3 test guidelines mm2 and 2 oz (0.034 mm) thick copper heat spreader. Following JEDEC JESD/EIA OPERATING CONDITIONS Parameter Symbol Range Unit Supply Voltage (VDD − VSS) VS 1.8 to 5.5 V Specified Operating Range TA −40 to 125 °C VICMR VSS−0.1 to VDD+0.1 V Input Common Mode Voltage Range Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 3 NCS325, NCS2325, NCS4325 ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. Boldface limits apply over the specified temperature range, TA = −40°C to 125°C, guaranteed by characterization and/or design. Parameter Symbol Conditions Min Typ Max Unit mV INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift vs Temp VOS NCS325 VS = +5V 14 50 NCS2325, NCS4325 VS = +5V 14 75 0.02 0.25 TA = −40°C to 125°C DVOS/DT mV/°C Input Bias Current IIB ±50 pA Input Offset Current IOS ±100 pA dB Common Mode Rejection Ratio CMRR NCS325 NCS2325, NCS4325 Input Resistance RIN Input Capacitance CIN VSS+0.3 < VCM < VDD − 0.3, VS = 1.8 V 85 108 VSS+0.3 < VCM < VDD − 0.3, VS = 5.5 V 90 110 VSS+0.3 < VCM < VDD − 0.3, VS = 5 V 90 110 VSS−0.1 < VCM < VDD + 0.1, VS = 1.8 V 80 VSS−0.1 < VCM < VDD + 0.1, VS = 5.5 V 92 NCS325 NCS2325, NCS4325 15 GW Differential 1.8 pF Common Mode 3.5 pF Differential 4.1 pF Common Mode 8.0 pF OUTPUT CHARACTERISTICS Output Voltage High VOH Output swing within VDD 12 100 mV Output Voltage Low VOL Output swing within VSS 8 100 mV ±5 mA f = 350 kHz, IO = 0 mA, VS = 1.8 V 1.4 kW Short Circuit Current Open Loop Output Impedance ISC Zout−OL f = 350 kHz, IO = 0 mA, VS = 5.5 V Capacitive Load Drive 2.7 CL See Figure NOISE PERFORMANCE Voltage Noise Density eN fIN = 1 kHz 100 nV / √Hz eP−P fIN = 0.01 Hz to 1 Hz 0.3 mVPP fIN = 0.1 Hz to 10 Hz 1 mVPP iN fIN = 10 Hz 0.3 pA / √Hz Open Loop Voltage Gain AVOL RL = 10 kW, VS = 5.5 V 114 dB Gain Bandwidth Product GBWP kHz Voltage Noise Current Noise Density DYNAMIC PERFORMANCE NCS325 CL = 100 pF, RL = 10 kW 350 NCS2325, NCS4325 CL = 100 pF, RL = 10 kW 270 Phase Margin fM CL = 100 pF 60 ° Gain Margin AM CL = 100 pF 20 dB Slew Rate SR G = +1, CL = 100 pF, Vs = 1.8 V 0.10 V/ms G = +1, CL = 100 pF, Vs = 5.5 V 0.16 POWER SUPPLY Power Supply Rejection Ratio PSRR 100 TA = −40°C to 125°C dB 107 95 Turn−on Time tON VS = 5 V 100 Quiescent Current IQ No load 21 ms 35 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 4 NCS325, NCS2325, NCS4325 TYPICAL CHARACTERISTICS 10 8 60 GAIN 40 6 4 2 0 3 6 9 12 15 18 21 24 0 −30 0 −60 PHASE −20 −90 −40 −120 −60 −150 27 30 10 100 1000 10k 100k OFFSET VOLTAGE (mV) FREQUENCY (Hz) Figure 2. Gain and Phase vs. Frequency 100 TA = 25°C VS = 5 V RL = 10 kW TA = 25°C 90 80 80 70 70 PSRR (dB) 60 50 40 30 −180 1M Figure 1. Offset Voltage Distribution 90 60 50 40 30 20 20 VS = 1.8 V VS = 5 V 10 0 10 100 10 1000 FREQUENCY (Hz) 0 10 100k 10k 3 VOH, VS = 5 V 500 TA = 25°C 400 INPUT BIAS CURRENT (pA) VOH, VS = 1.8 V 0 VOL, VS = 1.8 V −1 −2 VOL, VS = 5 V 0 1 2 3 4 5 6 100 1000 10k 100k 1M Figure 4. PSRR vs. Frequency 2 1 VSS VDD FREQUENCY (Hz) Figure 3. CMRR vs. Frequency OUTPUT SWING (V) 30 20 100 −3 60 −80 0 CMRR (dB) 90 Gain, VS = 1.8 V Gain, VS = 5.5 V Phase, VS = 1.8 V Phase, VS = 5.5 V 80 GAIN (dB) FREQUENCY 100 VS = 5 V VCM = midsupply TA = 25°C Sample size = 31 PHASE (°C) 12 7 8 9 300 200 VS = 1.8 V TA = 25°C IIB+ IIB− 100 0 −100 −200 −300 −400 −500 −1 −0.8 −0.6 −0.4 −0.2 10 0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (mA) COMMON MODE VOLTAGE (V) Figure 5. Output Voltage Swing vs. Output Current Figure 6. Input Bias Current vs. Common Mode Voltage, VS = 1.8 V www.onsemi.com 5 1 NCS325, NCS2325, NCS4325 TYPICAL CHARACTERISTICS (Continued) INPUT BIAS CURRENT (pA) 400 300 200 500 VS = 5.5 V TA = 25°C IIB+ IIB− 100 0 −100 −200 −300 300 200 100 0 −100 −200 −300 −400 −400 −500 −3 −2.5 −2 −1.5 −1 0 0.5 1 1.5 2 2.5 3 −500 −50 3.5 100 125 150 3 TA = 25°C IIB+ IIB− VS = 5.0 V RL = 10 kW CL = 10 pF Av = 1 V/V 2 −0.25 −0.5 1 0 −1 −2 −0.75 −0.75 −0.5 −0.25 0 0.25 0.5 DIFFERENTIAL VOLTAGE (V) 0.75 −3 −200 1 0.2 VOLTAGE (V) 200 300 300 400 500 400 Input Output 1 0 −1 −2 100 200 2 −0.1 0 100 3 0 −100 0 Figure 10. Large Signal Step Response VS = 5.0 V RL = 10 kW CL = 10 pF Av = 1 V/V 0.1 −100 TIME (ms) Figure 9. Input Bias Current vs. Input Differential Voltage OUTPUT VOLTAGE (V) 70 TEMPERATURE (°C) 0 −0.2 −200 50 Figure 8. Input Bias Current vs. Temperature 0.25 −1 −1 25 0 COMMON MODE VOLTAGE (V) OUTPUT VOLTAGE (V) INPUT BIAS CURRENT (pA) 0.5 −25 Figure 7. Input Bias Current vs. Common Mode Voltage, VS = 5.5 V 1.0 0.75 VS = 5.5 V IIB+ IIB− 400 INPUT BIAS CURRENT (pA) 500 −3 −100 500 VS = 5.0 V RL = 10 kW CL = 10 pF Av = −10 V/V −50 0 50 100 150 TIME (ms) TIME (ms) Figure 11. Small Signal Step Response Figure 12. Positive Over Voltage Recovery www.onsemi.com 6 200 NCS325, NCS2325, NCS4325 TYPICAL CHARACTERISTICS (Continued) 3 700 Input Output 600 1 0 −1 VS = 5.0 V RL = 10 kW CL = 10 pF Av = −10 V/V −2 −3 −100 60 −50 0 50 100 300 200 150 0 1 200 10 100 TIME (ms) GAIN (dB) Figure 13. Negative Over Voltage Recovery Figure 14. Setting Time vs. Closed Loop Gain VS = 1.8 V VS = 5.5 V 40 30 20 10 RL = 10 kW Input = 50 mV 0 10 100 1000 LOAD CAPACITANCE (pF) TIME (1 s/div) Figure 15. Small Signal Overshoot vs. Load Capacitance Figure 16. 0.1 Hz to 10 Hz Noise 1000 1000 CURRENT NOISE (PA/√Hz) VOLTAGE NOISE (nV/√Hz) 400 100 50 100 10 1 10 500 VOLTAGE (500 nV/div) 70 OVERSHOOT (%) SETTING TIME (ms) VOLTAGE (V) 2 VS = 5.0 V RL = 10 kW Output = 4 V Step VS = 1.8 V VS = 5.5 V 100 VS = 1.8 V VS = 5.5 V 100 10 1 0.1 0.01 0.1 1000 1 10 100 1000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 17. Voltage Noise Spectral Density vs. Frequency Figure 18. Current Noise Spectral Density vs. Frequency www.onsemi.com 7 10k NCS325, NCS2325, NCS4325 TYPICAL CHARACTERISTICS (Continued) 0.2 VS = 5.0 V VIN = 5 VPP SR+ 0.16 0.12 RL = 10 kW CL = 100 pF Av = −10 V/V VS = 1.8 V VIN = 1.5 V SR+ 0.1 SR− 0.08 0.06 −40 −20 0 20 40 60 80 100 20 VS = 1.8 V 15 10 5 0 −40 120 140 −20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) TEMPERATURE (°C) Figure 19. Slew Rate vs. Temperature Figure 20. Quiescent Current vs. Temperature 6 VDD Pulse 5 4 3 Output 2 1 0 −1 −20 0 20 40 60 5 4.99 4.98 4.97 4.96 4.95 4.94 4.93 4.92 4.90 4.89 4.88 RL = 10 kW 4.87 TA = 25°C 4.86 80 100 120 TIME (ms) Figure 21. Turn−on Response www.onsemi.com 8 OUTPUT VOLTAGE (V) 0.14 VS = 5.5 V 25 QUIESCENT CURRENT (mA) SR− VDD VOLTAGE (V) SLEW RATE (V/ms) 0.18 30 NCS325, NCS2325, NCS4325 APPLICATIONS INFORMATION INPUT VOLTAGE EMI SUSCEPTIBILITY AND INPUT FILTERING The NCS325, NCS2325 and NCS4325 have rail−to−rail common mode input voltage range. Diodes between the inputs and the supply rails keep the input voltage from exceeding the rails. Op amps have varying amounts of EMI susceptibility. Semiconductor junctions can pick up and rectify EMI signals, creating an EMI−induced voltage offset at the output, adding another component to the total error. Input pins are the most sensitive to EMI. The NCS325, NCS2325 and NCS4325 integrate a low−pass filter to decrease its sensitivity to EMI. VDD 10 kΩ IN+ APPLICATION CIRCUITS + Low−Side Current Sensing The goal of low−side current sensing is to detect over−current conditions or as a method of feedback control. A sense resistor is placed in series with the load to ground. Typically, the value of the sense resistor is less than 100 mW to reduce power loss across the resistor. The op amp amplifies the voltage drop across the sense resistor with a gain set by external resistors R1, R2, R3, and R4 (where R1 = R2, R3 = R4). Precision resistors are required for high accuracy, and the gain is set to utilize the full scale of the ADC for the highest resolution. − IN− 10 kΩ VSS Figure 22. Equivalent Input Circuit R3 VLOAD VDD VDD Load R1 VDD Microcontroller + ADC RSENSE control − R2 R4 Figure 23. Low−Side Current Sensing www.onsemi.com 9 NCS325, NCS2325, NCS4325 Differential Amplifier for Bridged Circuits produced is relatively small and needs to be amplified before going into an ADC. Precision amplifiers are recommended in these types of applications due to their high gain, low noise, and low offset voltage. Sensors to measure strain, pressure, and temperature are often configured in a Wheatstone bridge circuit as shown in Figure 24. In the measurement, the voltage change that is VDD VDD − + Figure 24. Bridge Circuit Amplification GENERAL LAYOUT GUIDELINES the device pins. These techniques will reduce susceptibility to electromagnetic interference (EMI). Thermoelectric effects can create an additional temperature dependent offset voltage at the input pins. To reduce these effects, use metals with low thermoelectric−coefficients and prevent temperature gradients from heat sources or cooling fans. To ensure optimum device performance, it is important to follow good PCB design practices. Place 0.1 mF decoupling capacitors as close as possible to the supply pins. Keep traces short, utilize a ground plane, choose surface−mount components, and place components as close as possible to www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−5 CASE 483 ISSUE N 5 1 SCALE 2:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION A. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. D 5X NOTE 5 2X DATE 12 AUG 2020 0.20 C A B 0.10 T M 2X 0.20 T 5 B 1 4 2 B S 3 K DETAIL Z G A A TOP VIEW DIM A B C D G H J K M S DETAIL Z J C 0.05 H C SIDE VIEW SEATING PLANE END VIEW GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 0.95 0.037 MILLIMETERS MIN MAX 2.85 3.15 1.35 1.65 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 0_ 10 _ 2.50 3.00 1.9 0.074 5 5 XXXAYWG G 1 1 Analog 2.4 0.094 XXX = Specific Device Code A = Assembly Location Y = Year W = Work Week G = Pb−Free Package 1.0 0.039 XXX MG G Discrete/Logic XXX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) 0.7 0.028 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ARB18753C TSOP−5 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE L 14 1 SCALE 1:1 D DATE 03 FEB 2016 A B 14 8 A3 E H L 1 0.25 B M DETAIL A 7 13X M b 0.25 M C A S B S 0.10 X 45 _ M A1 e DETAIL A h A C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 6.50 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 14 14X 1.18 XXXXXXXXXG AWLYWW 1 1 1.27 PITCH XXXXX A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 1: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 2: CANCELLED STYLE 3: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 4: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 5: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 6: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 7: PIN 1. ANODE/CATHODE 2. COMMON ANODE 3. COMMON CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. ANODE/CATHODE 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. COMMON CATHODE 12. COMMON ANODE 13. ANODE/CATHODE 14. ANODE/CATHODE STYLE 8: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS Micro8 CASE 846A−02 ISSUE K DATE 16 JUL 2020 SCALE 2:1 GENERIC MARKING DIAGRAM* 8 XXXX AYWG G 1 XXXX A Y W G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB14087C MICRO8 STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. N-SOURCE N-GATE P-SOURCE P-GATE P-DRAIN P-DRAIN N-DRAIN N-DRAIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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