NCS37010DBG

DATA SHEET www.onsemi.com Self Test With Lockout Ground Fault Circuit Interrupter (GFCI) MARKING DIAGRAMS QFN16 CASE 485FQ NCS37010 • • • • • PIN CONNECTIONS MLD CTresGN CTbias CTstim LO LED[0] • • • Series Impedance) −40 to 85°C Very low power consumption: < 15 mW @ 6 V 16 Pin QFN or 20 Pin TSSOP Package Single Current Transformer (CT) Detection of Both Differential and Grounded−Neutral Faults Full Self Test and Trip Indicator Monitoring. Self Test on Power Up Enables Lockout Functionality Self Syncing Internal Oscillator Adjusts to AC Mains Frequency to Guarantee Full Resolution on 50 and 60 Hz Distribution Systems Optimized Solenoid Deployment (Coil is Not Energized Near the AC Mains Zero Crossings) Randomized Testing Sequence to Minimize Noise and Potential Interactions on the AC Mains >5 mA SCR Driver for Use with High Igt SCR’s for Improved Noise Immunity Superior Immunity to Nuisance Loads/Noise (up to 10 A) Without Loss of Detection Capability or CT Saturation These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) 1 GND LObar PTT TE SCRtstEN GFtst GnEN • 6.0 − 12 V Operation (120 − 480 V AC Mains with the Appropriate 1 TSSOP−20 DB SUFFIX CASE 948E Supply SCRdrv Features 3701 0DBG ALYWG G 20 CTresD IDF The NCS37010 is a fully UL943 compliant signal processor for GFCI applications with self test and lockout. The device integrates a flexible power supply (including both shunt and LDO regulators), differential fault, and grounded−neutral detection circuits. Proprietary impedance measurement and signal processing techniques are used to minimize the number of external components and improve performance. The device also includes a specialized DSP controller that offers best in class immunity to nuisance loads without the need for external analog filters. At power up the NCS37010 performs a self test at 60ms and removes the lockout if the test passes. This self test consists of a differential, ground−neutral and solenoid test. • • • • NCS 37010 ALYWG G 1 (Top View) ORDERING INFORMATION See detailed ordering and shipping information on page 10 of this data sheet. Typical Applications • Load Panel GFCI Breakers • GFCI Receptacles • In−line GFCI Circuits (Power Cords) © Semiconductor Components Industries, LLC, 2014 July, 2022 − Rev. 2 1 Publication Order Number: NCP37010/D Supply NCS37010 Brown Out − HV Bandgap + AVDD / DVDD − + POR CTresGN Grounded Neutral Detection IDF Digital Filter Low Pass Filter Differential Current Detection SCRdrv Mixer Self Trimmed RC Osc CTresD LO CONTROL LOGIC LED(0) GROUND FAULT GN DETECTION Offset Correction GnEN GN Randomizer Ground GFtst TE SELF TEST SCRtstEN Vbias CTbias Driver CTstim Waveform Generator PTT GFCI ASIC Figure 1. Simplified Block Diagram www.onsemi.com 2 Mains Level Detector / Lockout Detector MLD LObar NCS37010 QFN PIN DESCRIPTION Pin # Name 0 Ground Pad Description 1 MLD 2 CtresGN 3 Ctbias Direct connection to the CT 4 Ctstim Direct connection to the CT 5 CTresD Determines IV converter gain for detection threshold / matched to CT turns ratio (Differential Current) 6 IDF 7 GFtst Output to induce external differential current. 8 GnEN Ground−Neutral fault detection enable pin. 9 SCRtstEN 10 TE QFN center slug Mains Level Detect (Zero Cross) Determines IV converter gain for detection threshold / matched to CT turns ratio (Ground−Neutral) Front end noise filter capacitor SCR/solenoid self test enable pin. Tie to Ground or leave floating. 11 PTT Push to test input. 12 LObar Load monitor input. 13 LED[0] LED[0] output driver. 14 LO 15 SCRdrv Used to trigger the solenoid at a fault detection 16 Supply Power supply Lockout SCR output driver. TSSOP PIN DESCRIPTION Pin # Name Pad Description 1 CTstim Differential and ground to neutral stimulus point for the current transformer. 2 Ground Ground connection for IC. 3 CTresD Determines IV converter gain for detection threshold / matched to CT turns ratio (Differential Current). 4 IDF Determines corner frequency of the differential current path filter. 5 GFtst Output to induce external differential current. 6 GnEN Ground−Neutral fault detection enable pin. 7 SCRtstEN 8 TE 9 PTT Push to test input. 10 LObar Load monitor input. SCR/solenoid self test enable pin. Tie to Ground or leave floating. 11 Ground Ground connection for IC. 12 LED[0] LED[0] output driver. 13 LO 14 SCRdrv 15 DVDD Internal digital 5 V regulated supply. 16 AVDD Internal analog 5 V regulated supply. 17 Supply 12V shunt regulated power supply. 18 MLD 19 CtresGN 20 CTbias Lockout SCR output driver. Used to trigger the solenoid at a fault detection. Mains Level Detect (Zero Cross) and AM slope detect (for oscillator sync/trim and AM init) Determines IV converter gain for detection threshold / matched to CT turns ratio (Ground−Neutral). External 2 V bias for the current transformer. www.onsemi.com 3 NCS37010 ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Supply Voltage Range Rating Vs 6.0 to 12 V Input Voltage Range (Note 1) Vin −0.3 to 6.0 V Output Voltage Range Vout −0.3 to 6.0 V or (Vin + 0.3), whichever is lower V TJ(max) 140 °C TSTG −65 to 150 °C ESD Capability, Human Body Model (Note 2) ESDHBM 2 kV ESD Capability, Machine Model (Note 2) ESDMM 200 V TSLD 260 °C Maximum Junction Temperature Storage Temperature Range Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free Versions (Note 3) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Latchup Current Maximum Rating: v150 mA per JEDEC standard: JESD78 3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D THERMAL CHARACTERISTICS Symbol Value Unit Thermal Characteristics, QFN16, 3x3.3 mm (Note 4) Thermal Resistance, Junction−to−Air (Note 5) Rating RθJA 64 °C/W Thermal Characteristics, TSSOP−20 (Note 4) Thermal Resistance, Junction−to−Air (Note 5) RθJA See note above. °C/W 4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 5. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. OPERATING RANGES (Note 6) Parameter Conditions Operating Temperature Min Typ −40 IDD in typical power state Unit 85 C 2 Stimulus Generator Frequency mA Tri−tone 3.1 3.4 kHz 8 mA With 5 V supply 4.5 5.5 V Programmable with CTresD 4.6 5 mA SCR Trigger Current SCR Trigger output voltage Fault Current Sensitivity Max 4.8 Ground Fault Response Time 5 − 20 mA 150 ms Ground Fault Response Time 20 − 40 mA 75 ms Ground Fault Response Time >40 mA 25 ms Saturation Fault Response Time >300 mA CT Turns Ratio Ground − Neutral Detection Threshold Total series impedance (Rn and Rg) Internal Oscillator Frequency 1.4 ms 200 300 3 6 2 CT Stimulus Current Internally limited CT Driver Closed Loop BW W MHz 1 mA 500 KHz Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. www.onsemi.com 4 NCS37010 NEUTRAL LOAD LINE APPLICATIONS INFORMATION BI−METAL DB FUSE S3 S2 ResMAIN S1 ResPTT CapSup LED CapSCR L E D drv LO Supply SCRdrv ResLED ResLOB ResMLD MLD LObar TEST ResGFTST CTresGN PTT CTbias TE CapGN CapBias ResGN CT CapCT CTstim LINE PHASE NEUTRAL CapIDF ResD Figure 2. Self Test GFCI Breaker with Lockout www.onsemi.com 5 GnEN ID F TVS G Ftest SCRtstEN C Tres D ResCT LINE PHASE NEUTRAL NCS37010 TVS RESET DB S1 ResMain D1 CapSCR L1 Q2 CapSup LE D [0 ] LO ResMLD SCRdrv Supply ResLED MLD ResLOB LObar TEST CTresGN PTT CapGN CapBias ResGN CTbias TE CTstim SCRtstEN CapCT ResCT PHASE NEUTRAL LOAD ResGFTST GnEN ID F C T re sD D3 GFtst D2 CapIDF ResD ResNPN Q1 Figure 3. Self Test GFCI Receptacle with Lockout on Power Up www.onsemi.com 6 NCS37010 PHASE NEUTRAL LINE S2 TVS SW3 DB S1 RESET ResMain D1 Q2 CapSCR L1 Q3 ResPTT CapSup LED[0] ResMLD LO Supply SCRdrv ResLED MLD LObar TEST CTresGN PTT CTbias NC CTstim SCRtstEN CapGN CapBias ResGN CT CapCT ResCT ResGFTST SW2 SW1 ResD RESET GnEN GFtest D3 IDF CTresD D2 CapIDF ResNPN PHASE NEUTRAL Q1 LOAD ResLOB Figure 4. Self Test GFCI Receptacle with Lockout (SCR Test Enabled) www.onsemi.com 7 LINE PHASE NEUTRAL NCS37010 TVS RESET DB S1 ResMain L1 Q2 ResPTT CapSup ResLED LED[0 ] LO SCRdrv Supply ResMLD ResLOB MLD LObar TEST CTresGN PTT CTbias TE CTstim SCRtstEN CapBias CT CapCT ResCT PHASE NEUTRAL LOAD ResGFTST ResD CapIDF ResNPN Q1 Figure 5. Self Test GFCI Plug (Differential Only) www.onsemi.com 8 GNen GFtst D3 IDF C Tre sD D2 NCS37010 RECOMMENDED EXTERNAL COMPONENTS: Component Type Instance Value SCR Q2−Q3 − ON−MCR08 Note Diode Dx − ON−1N4007 NPN Q1 − ON−MMBT6517LT1G NMOS M1 LED L1 − Capacitor CapSUP 1 − 4.7 mF For a full bridge rectifier Capacitor CapGN 1 − 10 nF Matched to current transformer Capacitor CapIDF 220 nF Sets the differential corner frequency at 1 kHz Capacitor CapBias 10 nF Filtering component for CTbias voltage. Capacitor CapCT 2.2 − 10 nF Filtering and resonant capacitor for CT. Capacitor CapSCR − ON−NTK3043K LED pins drive opposite polarities Filtering component. Resistor ResD 40 − 80k Matched to current transformer. Resistor ResGN 100 − 400k Matched to current transformer. Resistor ResMLD 400 − 800k Limiting resistor for the Mains Level Detector (MLD) input. Resistor ResTI 400 − 800k Limiting resistor for the Trip Indicator(TI) input. Resistor ResMAIN 8 − 45k Resistor ResGFTST 1.3 − 30k Resistor ResLED 1 − 5k Resistor ResPTT 400 − 800k Resistor ResNPN 10k TVS T1 − Full bridge rectifier power supply. Sets the external differential test current (8 mA). Sets the brightness of the LEDs. Needed for the SCR/Solenoid test. Bias resistor for NPN gate. ~250 − 400 V LED FUNCTIONS Device Function Normal Abnormal Device State Status Indicator (Breaker) No Power/ Line Load Reversed OFF Power Up Blink once within 3 sec (Red) Reset (Entered through PTT) OFF Tripped OFF Self−Test Fails (Tripped) OFF Self−Test Fails (Reset) Blink (Red) No Trip on Fault Blink (Red) Self−Test Fails to remove Lockout Blink (Red) www.onsemi.com 9 NCS37010 Filtering Differential ground fault test − tests the CT and the internal differential detection signal path by asserting the GFtest output high for 1 half cycle. The test will pass if a 6 − 8 mA differential current is enabled during this half wave. Greater than 20 mA current during this test will cause a fault to be detected. Ground neutral fault test − tests the internal ground neutral stimulus and detection paths by enabling an internal 50k resistor between the CTstim and CTbias pins. If the resistor and capacitor on CTresGN are connected this will pass the GN self test. Solenoid test − Asserts the SCRdrv output when the voltage on MLD is approximately 4 V. The PTT pin is coupled through a resistor to the output of the bridge rectifier. If the voltage at PTT drops below 2V when the SCRdrv pin is asserted then the test will pass. The SCRdrv output will be de−asserted when the test passes or when it reaches the zero crossing of the MLD pin. The Solenoid/SCR test can be disabled by tying the SCRtstEN pin to electronics ground. The analog signal capture portion of the IC includes a single pole filter that can be set externally with Cidf. This provides an additional layer of protection against false tripping under steady state noise conditions. High frequency steady state noise is common with pumps, motors or other cyclic noise generators. Cidf + 220 nF + 1 kHz low pass. For additional filtering suggestions please contact ON Semiconductor. Setting Trip Sensitivity The CTresD resistor sets the threshold for the differential current fault levels. Increasing CTresD causes the fault levels to trip at lower differential currents. CT efficiency at 60 Hz must be considered. CTresD + 200 * #Turns * Subject CT efficiency at 60 Hz The CTresGN resistor sets the threshold for ground to neutral fault detection. The Rt parameter is the desired ground to neutral resistance trip level. Higher CTresGN values will cause the part to trip at higher ground to neutral impedances. CtresGN = #Turns2 * Rt / 2 − Subject to CT efficiency from 3 kHz to 4 kHz Lockout On power−up the NCS37010 will determine connection state of the load by monitoring the LObar input pin. If the load is connected it will continue performing self test every 17 minutes and monitor for differential and GN faults. If the load is not connected a self test will be performed at 60ms after power−up. If self test passes the connection to the load will be enabled through the LO output which will be asserted for 16 ms. Setting Grounded-Neutral response time Cgn is used to define the response time of the grounded−neutral detection circuit. The analog portion converts the impedance into a DC voltage and a high frequency (aliased) component. The capacitor is used to remove the high frequency component leaving just the DC representation of the impedance. PTT When the PTT input pin is de−asserted for greater than 80 ms a self test will be performed. If this test is successful the SCR will be fired which will trip the GFCI unit. If the test is unsuccessful the LED[0] pin will flash indicating a failure. CTcapGN + 1.8E −4ńCTresGN Self Test GnEN Automatic self test will occur every 17 minutes. If a failure is observed it will be retested every second until it passes. If it fails 3 successive tests then the GFCI will indicate that it has failed self test and will trip. See the LED functions table to see the different self test indicators. The GnEN pin if left floating will enable GN fault detection which will allow for a full UL943 GFCI. If it is tied low then GN detection will be disabled. This setting is ideal for in−line GFCI plugs and breakers that are targeted for differential detection only. ORDERING INFORMATION Package Shipping† NCS37010MNTWG QFN16 (Pb−Free) 3000 / Tape & Reel NCS37010DBRG TSSOP−20 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485FQ ISSUE B GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G DOCUMENT NUMBER: DESCRIPTION: XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) 98AON84763G QFN16 3x3, 0.5P DATE 12 JUL 2022 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−20 WB CASE 948E ISSUE D DATE 17 FEB 2016 SCALE 2:1 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 XXXX XXXX ALYWG G 1 0.65 PITCH 16X 0.36 16X 1.26 DOCUMENT NUMBER: 98ASH70169A DESCRIPTION: TSSOP−20 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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