NCS8353MNTXG

NCS8353 Stereo 20W/Ch Class D Audio Power Amplifier with Programmable Power Limit and Selectable Gain The NCS8353 is a stereo Class D audio power amplifier capable of delivering a continuous power of up to 20 W/ch into an 8 W bridge tied load (BTL). It can be powered from the existing 24 V rail in Flat Panel Television (FPTV) systems. The high efficiency of the NCS8353, 86%, reduces the requirement of an external heat sink when driving high power. The digital power limit feature can program the output power limit at 10 W, 12 W, 15 W, or 20 W/ch, allowing the NCS8353 to be a single system solution in FPTV audio applications. The NCS8353 includes a digital power limit feature. The digital power limiter quickly reduces the internal gain of the amplifier when high amplitude signals would cause excessive clipping on the output. The NCS8353 minimizes pop and click artifacts in the audio system by reducing voltage and current transients during power supply cycling, entering or recovering from shutdown, and mute. The shutdown feature reduces the quiescent current draw of the amplifier to 100 mA typical. The mute feature ensures that audio is not present at the output during audio source switching. The gain of the NCS8353 is programmed via two gain pins, G0 and G1, allowing four selectable ranges: 20 dB, 26 dB, 32 dB, and 36 dB. Auto recovery short circuit and over temperature protection circuitry are incorporated to ensure device functionality after short circuit and high temperature events occur. Features • Powered from 8 V to 26 V to include FPTV Backlight Supply (24 V • • • • • • • • http://onsemi.com 1 QFN32 MN SUFFIX CASE 488AM 32 MARKING DIAGRAMS 1 NCS8353 AWLYYWWG G A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† ±5%) NCS8353MNTXG QFN32 2500 / Tape & Reel Digital Power Limiter Controlled by Two External bits: 10 W, 12 W, (Pb−Free) 15 W, or 20 W per Channel †For information on tape and reel specifications, ♦ Allows for Maximum System Flexibility including part orientation and tape sizes, please ♦ Reduces Distortion with Excessive Inputs refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Pop and Click Suppression Selectable Gain: 20 dB, 26 dB, 32 dB, 36 dB High Efficiency Eliminates the Need for External Heat • Fully Differential Architecture Sink • This is a Pb−Free Device Low Supply Current: IQ = 100 mA Typical During Typical Applications Shutdown at 12 V • Flat Panel Television (FPTV) Mute Function • Powered Speakers Auto−recovery Short−Circuit Protection Over Temperature Protection © Semiconductor Components Industries, LLC, 2011 March, 2011 − Rev. 3 1 Publication Order Number: NCS8353/D NCS8353 VCLAMPR BSRP PVDDR ROUTP RINN PGNDR Modulator BSRN PVDDR RINP ROUTN PGNDR MUTE MUTE CONTROL TO OUTPUTS EN Ramp Oscillator ENABLE CIRCUITRY VCLAMPL BSLP PVDDL LOUTP LINP PGNDL BSLN Modulator PVDDL LINN LOUTN PGNDL G0 G1 P0 Gain and Power Limit Select AVREG SHORT CIRCUIT PROTECTION P1 FROM OUTPUTS AVREG AVDD FAULT OVER TEMPERATURE PROTECTION AGND THERMAL PAD Figure 1. NCS8353 Basic Connections http://onsemi.com 2 PVDDR VCLAMPR 25 PVDDR 26 BSRN 27 28 ROUTN PGNDR 29 ROUTP 30 BSRP 31 32 PVDDR NCS8353 1 24 ENABLE RINN 2 23 AVDD RINP 3 22 MUTE G0 4 21 AVREG NCS8353 18 PL1 PVDDL 8 17 FAULT http://onsemi.com 3 VCLAMPL PVDDL PGNDL BSLP PVDDL LOUTP Figure 2. Package Options 16 7 15 LINN 14 PL0 BSLN 19 13 6 LOUTN LINP 12 AGND 11 20 10 5 9 G1 NCS8353 1 mF 1 mF 220mF 1 mF 22mH 22mH 220pF 10W 0.1 mF 220pF 10W 1 mF 0.22 mF 1 mF 0.22 mF 0.1 mF VCLAMPR PVDDR BSRN ROUTN PGNDR ROUTP BSRP PVDDR PVDDR EN 10W 1 mF NCS8353 RINN AVDD 1 mF MUTE 1 mF RINP AVREG G0 1 mF G1 AGND LINP PL0 1 mF PL1 LINN 1 mF FAULT 0.22 mF 1 mF VCLAMPL PVDDL BSLN LOUTN PGNDL LOUTP BSLP PVDDL PVDDL 0.22 mF 1 mF 0.1 mF 220pF 10W 10W 22mH 220pF 22mH 0.1 mF 1 mF 220mF 1 mF 1 mF Figure 3. Typical Application Connection for 8 W Speaker http://onsemi.com 4 NCS8353 PIN FUNCTION AND DESCRIPTION Pin# Name Input/output 1 PVDDR Power 2 RINN Input Right Input − Negative. 3 RINP Input Right Input − Positive. 4 G0 Input LSB Gain Setting. 5 G1 Input MSB Gain Setting. 6 LINP Input Left Input Positive. 7 LINN Input Left Input Negative. 8 PVDDL Power Power supply for left channel. 9 PVDDL Power Power supply for left channel. 10 BSLP − 11 LOUTP Output Positive Left Speaker Output. 12 PGNDL Ground Power ground for left channel. 13 LOUTN Output Negative Left Speaker Output. 14 BSLN − 15 PVDDL Power 16 VCLAMPL − 17 FAULT Output 18 PL1 Input MSB − Power Limit. 19 PL0 Input LSB − Power Limit. 20 AGND Ground Analog ground reference. 21 AVREG Output Regulator output voltage. 22 MUTE Input 23 AVDD Power 24 ENABLE Input 25 VCLAMPR − 26 PVDDR Power 27 BSRN − 28 ROUTN Output Negative right speaker output. 29 PGNDR Ground Power ground for right channel. 30 ROUTP Output Positive right speaker output. 31 BSRP − 32 PVDDR Power Description Power supply for right channel. Bootstrap for positive left speaker output. Bootstrap for negative left speaker output. Power supply for left channel. Internal voltage supply for left channel bootstrap capacitor. TTL compatible output. Asserts HIGH during thermal shutdown or short circuit conditions. TTL compatible input. Mutes the device when a logic HIGH is present. Analog high voltage supply. TTL compatible input. Enable for right and left channels when logic HIGH is present. Internal voltage supply for right channel bootstrap capacitor. Power supply for right channel. Bootstrap for right negative output. Bootstrap for right positive output. Power supply for right channel. http://onsemi.com 5 NCS8353 MAXIMUM RATINGS TABLE Symbol Rating Unit Power Supply Voltage (PVDDR, PVDDL) Parameter PVDD 30 V Analog Supply Voltage (AVDD) AVDD 30 V Input voltage (ENABLE, G0, G1, RINN, RINP, LINN, LINP) Vin −0.3 V to AVreg V Input voltage Mute function (MUTE) Vin −0.3 V to 3.6 V V Output Current (ROUTP, ROUTN, LOUTP LOUTN) IO 4.7 A Maximum Junction Temperature TJ 150 °C Operating Ambient Temperature TA −40 to +85 °C Storage Temperature TSTG 160 °C Junction−to−Air Thermal Resistance QFN−32 (Note 1) RqJA 31.4 °C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Board size: 5” x 4”, 4−layer, 2 oz copper. RECOMMENDED OPERATING CONDITIONS, TA = 25°C unless otherwise noted Symbol Min Operating Supply Voltage Range PVDD Analog Supply Voltage range AVDD 2 Specification Name Conditions High−level input voltage G0, G1, PL0, PL1, ENABLE, MUTE VIH Low−level input voltage G0, G1, PL0, PL1, ENABLE, MUTE VIL High Level Output Voltage Fault, IOH = +1 mA VOH Low Level Output Voltage Fault, IOL = −1 mA VOL Internal Oscillator Frequency fOSC http://onsemi.com 6 Typ Max Unit 8 26 V 8 26 V 3.6 V 0.8 V 3.3 AVREG − 0.4 V AGND + 0.4 315 V kHz NCS8353 DC ELECTRICAL CHARACTERISTICS, AVDD = PVDDR = PVDDL = 12 V, RL = 8 W, TA = 25°C unless otherwise noted Specification Name Differential Output Offset Voltage 5.0 V Internal Regulator Voltage input common mode range Quiescent Current Shutdown Quiescent Current On Resistance Drain to Source Gain Gain Matching Conditions Symbol Inputs AC GND, CIN = 1 mF, AV = 20 dB, Measured differentially VOSDIFF Min No load, Creg = 1 mF AVREG 4.5 Inputs AC coupled, CIN = 1 mF, Vbias = 2.15 V VICR AGND + 0.35 No load, No filter IQ No load, No filter, ENABLE ≤ 0.8 V Typ Max Unit 15 50 mV 5 5.5 V AVREG − 1.35 V 28 42 mA IQSHDN 100 200 mA Io = 500 mA RDSon 360 G0 = G1 ≤ 0.8 V AV mW 19 20 21 G0 ≤ 0.8 V, G1 ≥ 2 V 25 26 27 G0 ≥ 2 V, G1 ≤ 0.8 V 31 32 33 G0 = G1 ≥ 2 V 35 36 37 ROUTN / ROUTP, LOUTN / LOUTP dB 0.5 dB Turn on time ENABLE ≥ 2 V tON 250 ms Turn off time ENABLE ≤ 0.8 V tOFF 60 ms DC ELECTRICAL CHARACTERISTICS, AVDD = PVDDR = PVDDL = 24 V, RL = 8 W, TA = 25°C unless otherwise noted Specification Name Conditions Symbol Inputs AC GND, CIN = 1 mF, AV = 20 dB, Measured differentially VOSDIFF No load, Creg = 1 mF AVREG 4.5 Voltage input common mode range Inputs AC coupled, CIN = 1 mF, Vbias = 2.15 V VICR AGND + 0.35 Quiescent Current PVDD = 24 V, No load, No filter IQ Shutdown Quiescent Current PVDD = 24 V, No load, No filter, ENABLE ≤ 0.8 V IQSHDN IO = 500 mA rDS(on) G0 = G1≤ 0.8 V AV Differential Output Offset Voltage 5.0V Internal Regulator On Resistance Drain to Source Gain Gain Matching Min Typ Max Unit 15 50 mV 5 5.5 V AVREG − 1.35 V 33 45 mA 100 200 mA 360 mW 19 20 21 G0 ≤ 0.8 V, G1 ≥ 2 V 25 26 27 G0 ≥ 2 V, G1 ≤ 0.8 V 31 32 33 G0 = G1 ≥ 2 V 35 36 37 ROUTN / ROUTP, LOUTN / LOUTP dB 0.5 dB Turn on time ENABLE ≥ 2 V tON 250 ms Turn off time ENABLE ≤ 0.8 V tOFF 60 ms http://onsemi.com 7 NCS8353 AC ELECTRICAL CHARACTERISTICS, AVDD = PVDDR = PVDDL = 12 V, RL = 8 W, TA = 25°C unless otherwise noted Specification Name Conditions Symbol No supply bypass, 200 mVpp ripple, fin = 1 kHz, AV = 36 dB PSRRAC −69 dB Inputs shorted together, VIN = 32 mVpp, fin = 1 kHz, Av = 36 dB CMRRIEC −55 dB AV = 36 dB, THD+N = 1% Pout 7.5 W Total Harmonic Distortion + Noise AV = 36 dB, POUT = 1 W, fin = 1 kHz THD+N 0.05 % Efficiency THD+N = 0.03%, POUT = 5 W n 85 % Voltage noise (RTI) Inputs AC GND thru 100 nF, AV = 20 dB, A−weighting Ven 100 mVrms Crosstalk Po = 1 W, fin = 1 kHz, AV = 36 dB XTALK −85 dB VIN = 100 mVpp, Av = 20 dB SNR 90 dB Thermal Shutdown TSD 160 °C THS 30 °C AC Power Supply Rejection Ratio Common Mode Rejection Ratio IEC Output Power Signal to Noise Ratio Thermal trip point Thermal hysteresis Min Typ Max Unit AC ELECTRICAL CHARACTERISTICS, AVDD = PVDDR = PVDDL = 24 V, RL = 8 W, TA = 25 °C unless otherwise noted Specification Name Conditions Symbol No supply bypass, 200 mVpp ripple, fin = 1 kHz, AV = 36 dB PSRRAC −69 dB VIN = 32 mVpp, fin = 1 kHz, Av = 36 dB CMRRIEC −55 dB Output Power AV = 36 dB, THD+N = 1% Pout 20 W Total Harmonic Distortion + Noise AV = 20 dB, POUT = 10 W (Max value from 20 Hz to 20 kHz) THD+N 0.03 % 83 % AC Power Supply Rejection Ratio Common Mode Rejection Ratio (IEC) Efficiency THD+N = 1%, POUT = 20 W Min Typ Max Unit Voltage noise (RTI) Inputs AC GND thru 100 nF, AV = 32 dB, A−Weighting Ven 100 mVrms Crosstalk Po = 1 W, fin = 1 kHz, Av = 36 dB XTALK −85 dB Signal to Noise Ratio VIN =100 mVpp, fin = 1 kHz, Av = 36 dB SNR 90 dB Thermal Shutdown TSD 160 °C THS 30 °C Thermal trip point Thermal hysteresis http://onsemi.com 8 NCS8353 TYPICAL CHARACTERISTICS 1 1 VDD = 12 V AV = 36 dB RL = 8 W 5W 0.01 0.001 1 100 10 THD+N (%) THD+N (%) 1W 10 100 1000 10000 10 VDD = 12 V AV = 36 dB RL = 8 W Power Limit 1000 10000 0.1 1 0.1 1 kHz 20 Hz 20 kHz 10 20 kHz 0.001 0.01 100 0.1 1 10 OUTPUT POWER (W) OUTPUT POWER (W) Figure 6. THD+N vs. POUT Figure 7. THD+N vs. POUT 0 VDD = 12 V AV = 36 dB RL = 8 W PO = 1 W −40 L−R R−L −100 100 VDD = 24 V AV = 36 dB RL = 8 W PO = 1 W −20 −80 100000 Power Limit 0.01 XTALK (dB) XTALK (dB) 100 VDD = 24 V AV = 36 dB RL = 8 W 1 1 kHz −60 −120 1 10 FREQUENCY (Hz) 20 Hz −40 20 W Figure 5. THD+N vs. Frequency (BTL) 0.01 −20 10 W 0.01 FREQUENCY (Hz) 0.1 0 1W Figure 4. THD+N vs. Frequency (BTL) 1 0.001 0.01 0.1 0.001 1 100000 THD+N (%) THD+N (%) 0.1 VDD = 24 V AV = 36 dB RL = 8 W −60 L−R −80 R−L −100 10 100 1000 10000 100000 −120 1 10 100 1000 10000 100000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 8. Crosstalk L to R and R to L (20 Hz to 20 kHz) Figure 9. Crosstalk L to R and R to L (20 Hz to 20 kHz) http://onsemi.com 9 NCS8353 TYPICAL CHARACTERISTICS 0 −10 −20 100 AV = 36 dB RL = 8 W Vripple = 200 mVPP fripple = 1 kHz 90 EFFICENCY PSRR (dB) −40 −50 12 V −90 1 100 1000 10000 FREQUENCY (Hz) 50 40 20 24 V 10 60 30 −70 −80 24 V 70 −30 −60 12 V 80 AV = 20 dB RL = 8 W 10 0 0 100000 Figure 10. PSRR vs. Frequency 5 10 15 POWER (W) 20 Figure 11. Efficiency vs. Pout 250 ms 60 ms Figure 12. Turn−off Time − Mute Figure 13. Turn−on Time − Unmute 60 ms 250 ms Figure 14. Turn−on Time − Enable Figure 15. Turn−off Time − Disable http://onsemi.com 10 25 NCS8353 APPLICATIONS INFORMATION Digital Power Limiter The DPL reduces the internal gain of the NCS8353 thus reduces the output voltage to ensure the programmed power limit is not exceeded. Figure 17 illustrates the output voltage waveform after the DPL is activated. The NCS8353 utilizes a Digital Power Limiter (DPL) feature that limits the output power to 10 W, 12 W, 15 W, or 20 W per channel. This is achieved by the two external power limit pins, PL0 and PL1, which are TTL level compatible. If a change in power limit is desired, the NCS8353 must first be disabled followed by setting a new power limit. Finally, when the NCS8353 is re−enabled, the new power limit will be active. Table 1 illustrates the power limit per channel of the NCS8353 depending on the logic level of the power limit pins and is based on an 8 W speaker load. VDD Power Limit Table 1. PL1 PL0 Power Limit 0 0 10 W 0 1 12 W GND 1 0 15 W Figure 17. DPL Activated 1 1 20 W The DPL monitors the input referred voltage level and is dependent on the programmed gain of the NCS8353. Table 2, page 12, is a quick reference for the system designer to verify when the DPL will activate assuming an 8 W load. If the input voltage exceeds the input reference levels illustrated in Table 2, the DPL will activate. Figure 18 highlights the output power vs. input voltage for programmed power limits. Figure 16 shows a typical output waveform and a desired output power for an application. If the output waveform produces a higher output power than required; e.g., due to high input amplitudes, the DPL feature of the NCS8353 activates. VDD 25 20 Pout (W) Required Power 15 10 VCC = 24 V RL = 8 W AV = 36 dB PL = 20 W PL = 15 W PL = 12 W PL = 10 W 5 GND 0 0.05 Figure 16. Before DPL Operation 0.1 0.15 0.2 Vin, INPUT VOLTAGE (V) Figure 18. Power Limiter vs. Vin http://onsemi.com 11 0.25 NCS8353 Table 2. ALL POWER LIMITS AND VOLTAGES REFERENCED TO 8 W LOAD Plimit AV 20 W 15 W 12 W 10 W 20 dB 1.789 Vin(p) 1.549 Vin(p) 1.386 Vin(p) 1.265 Vin(p) 26 dB 894 mVin(p) 775 mVin(p) 693 mVin(p) 632 mVin(p) 32 dB 447 mVin(p) 387 mVin(p) 346 mVin(p) 316 mVin(p) 36 dB 284 mVin(p) 246 mVin(p) 220 mVin(p) 201 mVin(p) Programmable Gain Control stage re-enables and operates normally; however, if the short is still present the cycle begins again. Internal heat dissipation is kept to a minimum as current will only flow during the reset time of the protection circuitry. The hiccup mode is continuous until the short is removed. The NCS8353’s 2-bit gain control can be programmed either by digital control or by bootstrapping the gain control pins, G0, G1, to logic HIGH or LOW and are TTL compatible inputs for soft programming needs. Reference the electrical characteristics table for minimum and maximum levels. The logic table shown in Table 3 highlights the amplifier gain settings in dB based on gain setting. Over Temperature Protection The thermal protection circuitry of the NCS8353 monitors the maximum junction temperature of the die. When the temperature increases to 150°C, the specified maximum junction temperature, the internal gain of the device is reduced until the junction temperature is approximately 130°C. If the gain reduction is unable to limit the temperature rise of the junction then the thermal protection circuitry will completely disable the output stage once the junction temperature rises above 160°C. The NCS8353 will re-enable the output stage when the junction temperature falls to 130°C. This provides 30° of thermal hysteresis. Table 3. G1 G0 AMPLIFIER GAIN (dB) (Typ) 0 0 20 0 1 26 1 0 32 1 1 36 Similar to the DPL, if a change in gain is desired the NCS8353 must be disabled. The gain may then be programmed to the new desired level and then re-enabled for the new gain setting to latch. Enable The NCS8353 incorporates a single ENABLE control for right and left audio channels. When ENABLE is asserted logic LOW, the internal circuitry completely disables each channel to reduce quiescent current draw from the power supply. Typical shutdown current for the NCS8353 will be 100 mA typical per channel and start−up time from shutdown is typically ≤250 ms. See the electrical specification table for conditions. The ENABLE function also serves to latch new values for gain and the DPL. When new levels are desired the NCS8353 must be disabled, the new values must be programmed, and then re-enabled for the new values to latch. See Tables 1 and 3 for power limit and gain values. Fault Detection The NCS8353 incorporates fault detection circuitry. If a short circuit occurs the FAULT pin asserts logic HIGH providing the system designer an error flag for monitoring. The FAULT flag also asserts HIGH when the NCS8353 enters thermal shutdown. When the NCS8353 cools to 130°C or once the short circuit condition is removed the FAULT flag returns LOW. Short−Circuit Protection A short can occur to VDD, VSS, or across the load. The short circuit protection circuitry will disable the output stage from delivering current to the load when a short is present. With the short circuit protection circuitry active the internal power dissipation will be minimized. The NCS8353’s short circuit protection is analogous to a power supply’s hiccup mode current limiting operation. When a short is detected the NCS8353 will disable the output stage and will attempt to re-enable the output stage after 180 ms. If the short has been removed then the output Mute Function The MUTE function will ensure any audio signal present at the input is inaudible at the speaker load. The right and left channels are not in shutdown during this time. During the MUTE state, the outputs will continue to switch at 50% duty cycle; however, a modulated audio signal will not be present. The MUTE function is activated with a logic HIGH signal and deactivated with a logic LOW signal. http://onsemi.com 12 NCS8353 Pop and Click Suppression it causes the diaphragm to move thus causing a popping and clicking sound. The NCS8353 includes pop and click suppression circuitry that creates a slow ramp to bias the amplifier during the previously mentioned power sequences. In order to eliminate “pop and click” noises during transition, the output power in the load must not be established or cutoff suddenly. When logic high is applied to the shutdown pin, the internal biasing voltage rises quickly and once the output DC level is around the common mode voltage, the gain is established slowly. This method to turn on the device is optimized in terms of rejection of “pop and click” noises. The device has the same behavior when it is turned-off by a logic low on the enable pin. No power is delivered to the load 60 ms after a falling edge on the enable pin. Due to the fast turn on and off times, the shutdown signal can be used as a mute signal as well. Pop and click is often a function of charge difference from input coupling and bypass capacitors, momentary differential offset voltages across the speaker, or state changes of the input source (codec) that cause an abrupt change in current to flow through the loudspeaker. In all cases these pop and click phenomena occur during the following power sequences: • Power supply power-up or power down (codec or amp). • Entering or releasing from shutdown/mute (codec or amp). • State changes in the audio codec; e.g., switching between audio sources. Due to the voltage changes in the audio signal chain a momentary current will flow through the loudspeaker. When current flows through the voice coil of a loudspeaker http://onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A 1 32 SCALE 2:1 A D PIN ONE LOCATION ÉÉ ÉÉ NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L B DATE 23 OCT 2013 L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C EXPOSED Cu A DETAIL B 0.10 C (A3) A1 0.08 C DETAIL A 9 32X L ALTERNATE CONSTRUCTION GENERIC MARKING DIAGRAM* K D2 1 XXXXXXXX XXXXXXXX AWLYYWWG G 17 8 MOLD CMPD DETAIL B SEATING PLANE C SIDE VIEW NOTE 4 ÉÉ ÉÉ ÇÇ TOP VIEW MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.18 0.30 5.00 BSC 2.95 3.25 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 E2 1 32 25 e e/2 32X b 0.10 M C A B 0.05 M C BOTTOM VIEW XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 5.30 32X 0.63 3.35 3.35 5.30 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON20032D QFN32 5x5 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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