MC1455, MC1455B,
NCV1455B
Timers
The MC1455 monolithic timing circuit is a highly stable controller
capable of producing accurate time delays or oscillation. Additional
terminals are provided for triggering or resetting if desired. In the time
delay mode, time is precisely controlled by one external resistor and
capacitor. For astable operation as an oscillator, the free−running
frequency and the duty cycle are both accurately controlled with two
external resistors and one capacitor. The circuit may be triggered and
reset on falling waveforms, and the output structure can source or sink
up to 200 mA or drive TTL circuits.
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MARKING
DIAGRAMS
8
Features
8
Direct Replacement for NE555 Timers
Timing from Microseconds through Hours
Operates in Both Astable and Monostable Modes
Adjustable Duty Cycle
High Current Output Can Source or Sink 200 mA
Output Can Drive TTL
Temperature Stability of 0.005% per °C
Normally ON or Normally OFF Output
Pb−Free Packages are Available
1.0 k
3
4
2
0.1 mF
8
6
MC1455
5
0.01 mF
R
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
3.5 k
250 V
10 mF
+
+
0.01 mF
VCC
8
Threshold
+
Comp
A
-
Control Voltage
7
Q
Trigger
+
Comp
-B
Output
Discharge
Flip
R Flop
5k
2
Control
Voltage
3
5k
5
Reset
5
S Inhibit/
Reset
3
Output
5k
1
4
GND
Reset
Figure 2. Representative Block Diagram
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 10
VO
ISink
ISource
VCC
ICC
VR
Figure 1. 22 Second Solid State Time Delay Relay Circuit
6
= B or V
= BP1 or P1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
1N4003
-10 V
1N4740
1
x
yyy
A
L
Y, YY
W, WW
G or G
C
t = 1.1; R and C = 22 sec
Time delay (t) is variable by
changing R and C (see Figure 16).
MC1455yyy
AWL
YYWWG
PDIP−8
P1 SUFFIX
CASE 626
8
7
1.0 mF
1
8
MT1
G
20M
1455x
ALYW
G
1
Load
MT2
10 k
1
117 Vac/60 Hz
•
•
•
•
•
•
•
•
•
SOIC−8
D SUFFIX
CASE 751
4
8
VCC
700
7
Discharge
MC1455
Threshold
6
Ith
2.0 k
VS
GND
Trigger
1
2
Test circuit for measuring DC parameters (to set output and measure
parameters):
a) When VS w 2/3 VCC, VO is low.
b) When VS v 1/3 VCC, VO is high.
c) When VO is low, Pin 7 sinks current. To test for Reset, set VO
c) high, apply Reset voltage, and test for current flowing into Pin 7.
c) When Reset is not in use, it should be tied to VCC.
Figure 3. General Test Circuit
1
Publication Order Number:
MC1455/D
MC1455, MC1455B, NCV1455B
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)
Rating
Power Supply Voltage
Discharge Current (Pin 7)
Power Dissipation (Package Limitation)
P1 Suffix, Plastic Package
Derate above TA = +25°C
D Suffix, Plastic Package
Derate above TA = +25°C
Symbol
Value
Unit
VCC
+18
Vdc
I7
200
mA
PD
625
5.0
625
160
mW
mW/°C
mW
°C/W
PD
Operating Temperature Range (Ambient)
MC1455B
MC1455
NCV1455B
TA
Maximum Operating Die Junction Temperature
TJ
+150
°C
Storage Temperature Range
Tstg
−65 to +150
°C
°C
−40 to +85
0 to +70
−40 to +125
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = +5.0 V to +15 V, unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
Operating Supply Voltage Range
VCC
4.5
−
16
V
Supply Current
VCC = 5.0 V, RL = R
VCC = 15 V, RL = R, Low State (Note 1)
ICC
−
−
3.0
10
6.0
15
−
−
−
1.0
50
0.1
−
−
−
−
2/3
−
−
−
5.0
1.67
−
−
Timing Error (R = 1.0 kW to 100 kW) (Note 2)
Initial Accuracy C = 0.1 mF
Drift with Temperature
Drift with Supply Voltage
Threshold Voltage/Supply Voltage
Vth/VCC
mA
%
PPM/°C
%/V
Trigger Voltage
VCC = 15 V
VCC = 5.0 V
VT
Trigger Current
IT
−
0.5
−
Reset Voltage
VR
0.4
0.7
1.0
V
Reset Current
IR
−
0.1
−
mA
Threshold Current (Note 3)
Ith
−
0.1
0.25
mA
Idischg
−
−
100
nA
9.0
2.6
10
3.33
11
4.0
−
−
−
−
−
−
0.1
0.4
2.0
2.5
−
0.25
0.25
0.75
2.5
−
−
0.35
−
12.75
2.75
12.5
13.3
3.3
−
−
−
Discharge Leakage Current (Pin 7)
Control Voltage Level
VCC = 15 V
VCC = 5.0 V
VCL
Output Voltage Low
ISink = 10 mA (VCC = 15 V)
ISink = 50 mA (VCC = 15 V)
ISink = 100 mA (VCC = 15 V)
ISink = 200 mA (VCC = 15 V)
ISink = 8.0 mA (VCC = 5.0 V)
ISink = 5.0 mA (VCC = 5.0 V)
VOL
Output Voltage High
VCC = 15 V (ISource = 200 mA)
VCC = 15 V (ISource = 100 mA)
VCC = 5.0 V (ISource = 100 mA)
VOH
V
mA
V
V
V
Rise Time Differential Output
tr
−
100
−
ns
Fall Time Differential Output
tf
−
100
−
ns
1.
2.
3.
4.
‘Supply current when output is high is typically 1.0 mA less.
Tested at VCC = 5.0 V and VCC = 15 V Monostable mode.
This will determine the maximum value of RA + RB for 15 V operation. The maximum total R = 20 MW .
Tlow = 0°C for MC1455, Tlow = −40°C for MC1455B, NCV1455B
Thigh = +70°C for MC1455, Thigh = +85°C for MC1455B, Thigh = +125°C for NCV1455B
5. NCV prefix is for Automotive and other applications requiring site and change control.
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2
MC1455, MC1455B, NCV1455B
10
125
ICC , SUPPLY CURRENT (mA)
PW, PULSE WIDTH (ns min)
150
100
75
0°C
50
25°C
70°C
25
0.1
0.2
0.3
0.4
15
Figure 5. Supply Current
10
VOL, LOW OUTPUT VOLTAGE (Vdc)
VCC -VOH (Vdc)
10
Figure 4. Trigger Pulse Width
1.6
1.4
25°C
1.2
1.0
0.8
0.6
0.4
5.0 V ≤ VCC ≤ 15 V
2.0
5.0
10
20
50
25°C
1.0
0.1
0.01
1.0
100
2.0
5.0
10
20
ISource (mA)
ISink (mA)
Figure 6. High Output Voltage
Figure 7. Low Output Voltage
@ VCC = 5.0 Vdc
10
50
100
10
VOL, LOW OUTPUT VOLTAGE (Vdc)
VOL, LOW OUTPUT VOLTAGE (Vdc)
2.0
VCC, SUPPLY VOLTAGE (Vdc)
1.8
25°C
1.0
0.1
0.01
1.0
4.0
VT(min), MINIMUM TRIGGER VOLTAGE (x VCC = Vdc)
2.0
0.2
0
1.0
6.0
0
5.0
0
0
25°C
8.0
2.0
5.0
10
20
50
1.0
0.01
1.0
100
25°C
0.1
2.0
5.0
10
20
50
ISink (mA)
ISink (mA)
Figure 8. Low Output Voltage
@ VCC = 10 Vdc
Figure 9. Low Output Voltage
@ VCC = 15 Vdc
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3
100
MC1455, MC1455B, NCV1455B
t d, DELAY TIME NORMALIZED
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0
5.0
10
15
1.010
1.005
1.000
0.995
0.990
0.985
- 75
20
- 50
- 25
0
25
50
75
100
VCC, SUPPLY VOLTAGE (Vdc)
TA, AMBIENT TEMPERATURE (°C)
Figure 10. Delay Time versus Supply Voltage
Figure 11. Delay Time versus Temperature
300
t pd , PROPAGATION DELAY TIME (ns)
t d, DELAY TIME NORMALIZED
1.015
250
200
150
0°C
100
70°C
25°C
50
0
0
0.1
0.2
0.3
VT(min), MINIMUM TRIGGER VOLTAGE (x VCC = Vdc)
Figure 12. Propagation Delay
versus Trigger Voltage
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4
0.4
125
MC1455, MC1455B, NCV1455B
Control Voltage
Threshold
Comparator
Trigger
Comparator
Flip-Flop
Output
VCC
4.7 k
830
4.7k
6.8 k
1.0 k
5.0 k
Threshold
7.0 k
3.9 k
10 k
Output
cb
e
5.0 k
c
b
4.7 k
Trigger
220
Reset
Reset
Discharge
GND
100 k
4.7 k
5.0 k
Discharge
100
Figure 13. Representative Circuit Schematic
GENERAL OPERATION
The MC1455 is a monolithic timing circuit which uses an
external resistor − capacitor network as its timing element. It
can be used in both the monostable (one−shot) and astable
modes with frequency and duty cycle controlled by the
capacitor and resistor values. While the timing is dependent
upon the external passive components, the monolithic circuit
provides the starting circuit, voltage comparison and other
functions needed for a complete timing circuit. Internal to the
integrated circuit are two comparators, one for the input
signal and the other for capacitor voltage; also a flip−flop and
digital output are included. The comparator reference
voltages are always a fixed ratio of the supply voltage thus
providing output timing independent of supply voltage.
has been triggered by an input signal, it cannot be retriggered
until the present timing period has been completed. The time
that the output is high is given by the equation t = 1.1 RA C.
Various combinations of R and C and their associated times
are shown in Figure 16. The trigger pulse width must be less
than the timing period.
A reset pin is provided to discharge the capacitor, thus
interrupting the timing cycle. As long as the reset pin is low,
the capacitor discharge transistor is turned “on” and prevents
the capacitor from charging. While the reset voltage is applied
the digital output will remain the same. The reset pin should
be tied to the supply voltage when not in use.
+VCC (5.0 V to 15 V)
Monostable Mode
In the monostable mode, a capacitor and a single resistor
are used for the timing network. Both the threshold terminal
and the discharge transistor terminal are connected together
in this mode (refer to circuit in Figure 14). When the input
voltage to the trigger comparator falls below 1/3 VCC, the
comparator output triggers the flip−flop so that its output sets
low. This turns the capacitor discharge transistor “off” and
drives the digital output to the high state. This condition
allows the capacitor to charge at an exponential rate which is
set by the RC time constant. When the capacitor voltage
reaches 2/3 VCC, the threshold comparator resets the
flip−flop. This action discharges the timing capacitor and
returns the digital output to the low state. Once the flip−flop
Reset
4
RL
VCC
8
Output
3
RL
MC1455
RA
Discharge
7
6
Threshold
5
2
Trigger
1
Control
Voltage
Figure 14. Monostable Circuit
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5
C
0.01 mF
MC1455, MC1455B, NCV1455B
100
C, CAPACITANCE ( μ F)
10
1.0
0.1
0.01
0.001
10 ms
t = 50 ms/cm
(RA = 10 kW, C = 0.01 mF, RL = 1.0 kW, VCC = 15 V)
100 ms 1.0 ms
Figure 15. Monostable Waveforms
10 ms 100 ms
td, TIME DELAY (s)
1.0
10
100
Figure 16. Time Delay
+VCC (5.0 V to 15 V)
Reset
4
RL
RA
VCC
8
Output
3
7Discharge
6Threshold
MC1455
Trigger
Control
Voltage
2
RL
RB
5
1
C
t = 20 ms/cm
(RA = 5.1 kW, C = 0.01 mF, RL = 1.0 kW; RB = 3.9 kW, VCC = 15 V)
Figure 17. Astable Circuit
Figure 18. Astable Waveforms
Astable Mode
In the astable mode the timer is connected so that it will
retrigger itself and cause the capacitor voltage to oscillate
between 1/3 VCC and 2/3 VCC. See Figure 17.
The external capacitor changes to 2/3 VCC through RA and
RB and discharges to 1/3 VCC through RB. By varying the
ratio of these resistors the duty cycle can be varied. The
charge and discharge times are independent of the supply
voltage.
The charge time (output high) is given by:
To obtain the maximum duty cycle RA must be as small as
possible; but it must also be large enough to limit the
discharge current (Pin 7 current) within the maximum rating
of the discharge transistor (200 mA).
The minimum value of RA is given by:
RA w
VCC(Vdc)
I7 (A)
w
VCC(Vdc)
0.2
100
t1 + 0.695 (RA ) RB) C
C, CAPACITANCE ( μ F)
The discharge time (output low) is given by:
t2 + 0.695 (RB) C
Thus the total period is given by:
T + t1 ) t2 + 0.695 (RA ) 2RB) C
The frequency of oscillation is then:
f+
1
1.44
+
1
(RA ) 2RB)C
DC +
1.0
0.1
0.01
(RA + 2 RB)
and may be easily found as shown in Figure 19.
The duty cycle is given by:
10
0.001
0.1
RB
RA ) 2RB
1.0
10
100
1.0 k
10 k
f, FREE RUNNING FREQUENCY (Hz)
Figure 19. Free Running Frequency
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6
100
MC1455, MC1455B, NCV1455B
APPLICATIONS INFORMATION
Linear Voltage Ramp
Missing Pulse Detector
In the monostable mode, the resistor can be replaced by a
constant current source to provide a linear ramp voltage. The
capacitor still charges from 0 VCC to 2/3 VCC. The linear
ramp time is given by:
The timer can be used to produce an output when an input
pulse fails to occur within the delay of the timer. To
accomplish this, set the time delay to be slightly longer than
the time between successive input pulses. The timing cycle
is then continuously reset by the input pulse train until a
change in frequency or a missing pulse allows completion of
the timing cycle, causing a change in the output level.
t=
2 VCC
, where I =
3
1
VCC − VB − VBE
RE
If VB is much larger than VBE, then t can be made
independent of VCC.
+VCC (5.0 V to 15 V)
VCC
Reset
4
8
VCC
RE
Digital 3
Output
7
MC1455
Trigger
VE
6
2
5
1
0.01 mF
Sweep
Output
Discharge
Output
MC1455
VB
I
Input
2
7
Threshold
6 Control
5 Voltage
Trigger
R2
C
0.01 mF
1
C
RA
8
3
R1
2N4403
or Equiv
VCC
Reset
4
RL
2N4403
or Equiv
Control
Voltage
Figure 20. Linear Voltage Sweep Circuit
Figure 21. Missing Pulse Detector
t = 100 ms/cm
t = 500 ms/cm
(RE = 10 kW, R2 = 100 kW, R1 = 39 kW, C = 0.01 mF, VCC = 15 V)
(RA = 2.0 kW, RL = 1.0 kW, C = 0.01 mF, VCC = 15 V)
Figure 22. Linear Voltage Ramp Waveforms
Figure 23. Missing Pulse Detector Waveforms
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7
MC1455, MC1455B, NCV1455B
Pulse Width Modulation
If the timer is triggered with a continuous pulse train in the
monostable mode of operation, the charge time of the
capacitor can be varied by changing the control voltage at
Pin 5. In this manner, the output pulse width can be
modulated by applying a modulating signal that controls the
threshold voltage.
+VCC (5.0 V to 15 V)
RA
RL
4
8
t = 0.5 ms/cm
(RA = 10 kW, C = 0.02 mF, VCC = 15 V)
7
3
Figure 25. Pulse Width Modulation Waveforms
C
Output
6
MC1455
2
Test Sequences
5
Clock
Input
Several timers can be connected to drive each other for
sequential timing. An example is shown in Figure 26 where
the sequence is started by triggering the first timer which
runs for 10 ms. The output then switches low momentarily
and starts the second timer which runs for 50 ms and so forth.
Modulation
Input
1
Figure 24. Pulse Width Modulator
VCC (5.0 V to 15 V)
9.1 k
27 k
8
8
4
5 0.01 mF
6
7
3
1.0 mF
1
5.0 mF
4
5 0.01 mF
6
7
MC1455
0.001 mF
2
8
5 0.01 mF
2
3
18.2 k
4
6
MC1455
7
27 k
9.1 k
MC1455
3
2
0.001 mF
5.0 mF
1
Load
Load
Figure 26. Sequential Timer
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8
1
Load
MC1455, MC1455B, NCV1455B
ORDERING INFORMATION
Device
Operating Temperature Range
MC1455P1
MC1455P1G
MC1455D
MC1455DG
TA = 0°C to +70°C
MC1455DR2
MC1455DR2G
MC1455BD
MC1455BDG
MC1455BDR2
MC1455BDR2G
TA = −40°C to +85°C
MC1455BP1
MC1455BP1G
NCV1455BDR2*
NCV1455BDR2G*
TA = −40°C to +125°C
Package
Shipping†
PDIP−8
50 Units / Rail
PDIP−8
(Pb−Free)
50 Units / Rail
SOIC−8
98 Units / Rail
SOIC−8
(Pb−Free)
98 Units / Rail
SOIC−8
2500 Units / Tape & Reel
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
SOIC−8
98 Units / Rail
SOIC−8
(Pb−Free)
98 Units / Rail
SOIC−8
2500 Units / Tape & Reel
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
PDIP−8
50 Units / Rail
PDIP−8
(Pb−Free)
50 Units / Rail
SOIC−8
2500 Units / Tape & Reel
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV prefix is for automotive and other applications requiring site and control changes.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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