NCV303150MTW

Integrated Driver and MOSFET with Integrated Current Monitor NCV303150 Description www.onsemi.com The NCV303150 integrates a MOSFET driver, high−side MOSFET and low−side MOSFET into a single package. The driver and MOSFETs have been optimized for high−current DC−DC buck power conversion applications. The NCV303150 integrated solution greatly reduces package parasitics and board space compared to a discrete component solution. WQFNW39 MTW SUFFIX CASE 512AM Features • Capable of Average Currents up to 50 A • 30 V / 30 V Breakdown Voltage MOSFETs for Higher Long Term Reliability • High−Performance, Universal Footprint, Copper−Clip 5 mm x 6 mm • • • • • • • • WQFNW Package in Wettable Flank Capable of Switching at Frequencies up to 1 MHz Compatible with 3.3 V or 5 V PWM Input Responds Properly to 3−level PWM Inputs Precise Current Monitoring Option for Zero Cross Detection with 3−level PWM Internal Bootstrap Diode Catastrophic Fault Detection ♦ Thermal Flag (OTP) for Over−Temperature Condition ♦ Over−Current Protection FAULT (OCP) ♦ Under−Voltage Lockout (UVLO) on VCC and PVCC ♦ Under−Voltage Protection FAULT on Boot−SW NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable Desktop & Notebook Microprocessors Graphic Cards Routers and Switches Automotive−qualified Systems © Semiconductor Components Industries, LLC, 2020 April, 2021 − Rev. 0 NCV 303150 AWLYYWWG G NCV303150 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Applications • • • • MARKING DIAGRAM NCV303150MTW Package Shipping† WQFNW39 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 Publication Order Number: NCV303150/D NCV303150 DIAGRAMS RVCC V 5V C PVCC CVCC PVCC PWM PWM from controller DRVON from controller VCC RBOOT VIN BOOT PHASE TMON/FLT ZCD_EN IIN C BOOT DISB# TMON/FLT V IN C VIN IOUT SW COUT ZCD_EN Current sense RefIN Voltage VOUT L OUT IMON REFIN AGND PGND Figure 1. Application Schematic PVCC 3.3 V BOOT flag on FAULT THERMAL WARNING TMON/ FLT FAULT LATCH EN_PWM IMON VIN IMON FAULT LOGIC REFIN PHASE 1 V / 2.4 V EN_POR LEVEL SHIFT STARTUP (POR) EN/UVLO EN_PWM EN_POR PWM CONTROL LOGIC VCC EN_IC REN_DOWN EN_POR DISB# HDRV SW VCC LDRV RPWM_UP PWM INPUT STAGE PWM VCC GL RPWM_DOWN EN_POR ZCD_EN ZCD CONTROL AGND Figure 2. Block Diagram www.onsemi.com 2 PGND NCV303150 PINOUT DIAGRAM 1 AGND 2 VCC 3 PVCC 4 PGND 5 GL 6 6.0 mm N/C REFIN IMON ZCD_EN TMON/ FLT DISB# PWM BOOT PHASE N/C VIN 5.0 mm 39 38 37 36 35 34 33 32 31 30 29 28 VIN 40 27 25 VIN 21 PGND 10 11 12 13 14 15 16 17 18 19 SW SW SW SW SW 20 PGND SW 9 SW PGND 22 PGND SW 8 23 PGND SW PGND 24 PGND SW 7 VIN 26 VIN GL 41 PGND VIN Figure 3. Top View Table 1. PIN LIST AND DESCRIPTIONS Pin No. Symbol Description 1 NC 2 AGND 3 VCC 4 PVCC Power Supply input for LS Gate Driver and Boot Diode. 5, 40 PGND Reserved for PVCC de−coupling capacitor return. 6, 41 GL 7−9, 20−24 PGND 10−19 SW Switching node junction between high−and low−side MOSFETs 25−30 VIN Input Voltage to Power Stage. 31 NC No connect. 32 PHASE Return Connection for BOOT capacitor. 33 BOOT Supply for high−side MOSFET gate driver. A capacitor from BOOT to PHASE supplies the charge to turn on the n−channel high side MOSFET. During the freewheeling interval (LS MOSFET on) the high side capacitor is recharged by an internal diode. 34 PWM PWM input to gate driver IC. 35 DISB# DISB# = LOW disables most blocks inside IC. DISB# = HIGH enables all blocks inside IC. 36 TMON/FLT 37 ZCD_EN 38 IMON Current Monitor Output (output is referenced to REFIN) − 5 mA/A 39 REFIN Referenced voltage used for IMON feature. DC input voltage supplied by external source (not generated on SPS driver IC) No connect. Analog Ground for the analog portions of the IC and for substrate. Power Supply input for all analog control functions Low−Side Gate Monitor. Power ground connection for Power Stage high current path. Temperature and FAULT Reporting Pin. Pin sources a (PTAT) voltage of 0.6 V at 0°C with an 8 mV/°C slope when no module FAULT is present. In the event of a module FAULT, this pin pulls HIGH to an internal driver IC rail = 3.0 V typical. Zero Current Detection Function Enable www.onsemi.com 3 NCV303150 Table 2. ABSOLUTE MAXIMUM RATINGS (Electrical Information − all signals referenced to PGND unless noted otherwise) Parameter Pin Name VCC Min Max Unit Supply Voltage Referenced to AGND −0.3 6 V PVCC Drive Voltage Referenced to AGND −0.3 6 V VDISB# Enable / Disable Referenced to AGND −0.3 VCC+0.3 V VPWM PWM Signal Input Referenced to AGND −0.3 VCC+0.3 V ZCD Mode Input Referenced to AGND −0.3 VCC+0.3 V Low Gate Test Pin Referenced to AGND −0.3 VCC+0.3 V VIMON Current Monitor Output Referenced to AGND −0.3 VCC+0.3 V VREFIN Referenced Voltage input Referenced to AGND −0.3 VCC+0.3 V Thermal Monitor Referenced to AGND −0.3 VCC+0.3 V VIn Power Input Referenced to PGND, AGND −0.3 30 V VVin − Phase Vin − PHASE Referenced to PGND, AGND (DC Only) −0.3 30 V Referenced to PGND, AC < 5 ns −5 36 Referenced to PGND, AGND (DC Only) −0.3 30 Referenced to PGND, AC < 5 ns −15 30 Referenced to PGND, AGND (DC Only) −0.3 30 Referenced to PGND, AC < 5 ns −7 36 Referenced to AGND −0.3 32 V DC Only −0.3 7 V 150 °C 10.2 mJ VZCD_EN VGL VTMON/FLT Vphase VSW VBOOT Phase Switch Node Input Bootstrap Supply VBOOT−PHASE Boot to PHASE Voltage TJ Maximum Junction Temperature UIS Unclamped Inductive Switching SinglePulse Avalanche Energy, Highside FET (TJ = 25°C, VCC & VGS = 5 V, L = 1.65 mH, IL = 84 APk) ESD Electrostatic Discharge Protection Human Body Model, − 2000 V V V ANSI/ESDA/JEDEC JS−001−2012 Charged Device Model, JESD22−C101 1000 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 4 NCV303150 Table 3. THERMAL INFORMATION Rating Symbol Value Unit qJ−Lead (Note 2) 0.8 °C/W qJ−CaseTop 13.1 °C/W qJ−Ambient 16 °C/W Operating Ambient Temperature Range TA −40 to +125 °C Maximum Storage Temperature Range TSTG −55 to +150 °C MSL 1 Thermal Resistance (Note 1) Moisture Sensitivity Level 1. Mounted on 2S2P test board with 0 LFM at TA = 25°C 2. Measured at PGND Pad (Pins 20 – 24) Table 4. RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Range Conversion Voltage Continuous Output Current Peak Output Current Pin Name Conditions Min Typ Max Unit VCC, PVCC 4.5 5.0 5.5 V VIN 4.5 19 20 V FSW = 1 MHz, VIN = 19 V, VOUT = 1.0 V, TA = 25°C − − 45 A FSW = 300 kHz, VIN = 19 V, VOUT = 1.0 V, TA = 25°C − − 50 A FSW = 500 kHz, VIN = 19 V, VOUT = 1.0 V, Duration = 10 ms, Period = 1 s, TA = 25°C − − 80 A −40 − 125 °C Junction Temperature Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 5 NCV303150 Table 5. ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VIN = 19 V, VDISB# = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit BASIC OPERATION No switching DISB# = 5 V, PWM = 0 V − 8 − mA Disabled DISB# = 0 V, SW = 0 V − 120 − mA 3.8 4.1 4.2 V − 0.17 − V − − 125 ms − 130 − kW 2.7 − − V UVLO Threshold VUVLO UVLO Hysteresis UVLO_Hyst POR Delay to Enable IC TD_POR VCC rising VCC UVLO rising to internal PWM enable DISB# INPUT Pull−Down Resistance High−Level Input Voltage VUPPER Low−Level Input Voltage VLOWER − − 0.65 V Enable Propagation Delay PWM=GND, Delay Between EN from LOW to HIGH to GL from LOW to HIGH – Slow EN Setting 16 26 32 ms Disable Propagation Delay PWM=GND, Delay Between EN from HIGH to LOW to GL from HIGH to LOW – Fast EN setting − 43 109 ns VPWM_HI 2.3 2.45 2.55 V Mid−State Voltage Upper Threshold VTRI_HI 2.05 2.2 2.3 V Mid−State Voltage Lower Threshold VTRI_LO 0.9 1.0 1.1 V Input Low Voltage VPWM_LO 0.65 0.75 0.85 V Pull−Up Impedance RUP_PWM − 21 − kW Pull−Down Impedance RDOWN_PWM − 10 − kW 3−State Open Voltage VPWM_HIZ 1.4 1.65 1.85 V Non−overlap Delay, Leading Edge TDEADON GL 1.2 V, PWM Transition 0→1 − 7 − ns Non−overlap Delay, Trailing Edge TDEADOFF SW =0.5 V, PWM Transition 1→0 − 6 − ns PWM Propagation Delay, Rising TPD_PHGLL PWM Going HIGH to GL Going LOW, VIH_PWM to 90% GL − 17 20 ns PWM Propagation Delay, Falling TPD_PLGHL PWM Going LOW to GH Going LOW, VIL_PWM to 90% GH − 26 30 ns Exiting PWM Mid−state Propagation Delay, Mid−to−Low TPWM_EXIT_L PWM (from Tri−State) going LOW to GL going HIGH, VIL_PWM to 10% GL − 20 30 ns Exiting PWM Mid−state Propagation Delay, Mid−to−High TPWM_EXIT_H PWM (from Tri−State) going HIGH to SW going HIGH, VIH_PWM to 10% SW − 27 30 ns PWM High to 3−State hold Off Time TD_HOLDOFF1 PWM Going High to HS Going Off 20 43 50 ns PWM Low to 3−State hold Off Time TD_HOLDOFF2 PWM Going Low to LS Going Off 20 36 50 ns HS minimal turn on time TON_MIN_HS SW gate rising 10% to falling 10% − 37 − ns LS minimal turn on time TON_MIN_LS LS gate rising 10% to falling 10% − 33 − ns HS minimal turn off time TOFF_MIN_HS SW gate falling 10% to rising 10% − 31 − ns LS minimal turn off time TOFF_MIN_LS LS gate falling 10% to rising 10% − 51 − ns PWM INPUT (TA = 25°C, VCC / PVCC = 5 V, fSW = 1 MHz, IOUT = 10 A) Input High Voltage www.onsemi.com 6 NCV303150 Table 5. ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VIN = 19 V, VDISB# = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit FAULT FLAG OUTPUT VOLTAGE/CURRENT FAULT Report Output Voltage VFAULT 2.7 − − V Fault Report Delay time TDFAULT − 100 − ns IMON HS off to LS On Blanking Stop Time TBLANK_HSOFF IMON Blanking Time for PWM transition 1³0 − 90 − ns HS on to LS Off Blanking Stop Time TBLANK_HSON IMON Blanking Time for PWM transition 0³1 − 70 − ns IMON Amplifier Gain BW BWIMON L = 150 nH, VIN = 19 V, VOUT = 1.0 V, fSW = 800 kHz − 5 − MHz IMON Propagation Delay Time TDELAY L = 150 nH, VIN = 19 V, VOUT = 1.0 V, fSW = 800 kHz, IMON to IL − 60 − ns 0.6 − 2.3 V IOUT = −10 A to 40 A 4.75 5.00 5.25 mA/A IOUT = 10 A, Voltage is Referenced to REFIN Pin 46.5 50 53.5 mV IOUT = 20 A, Voltage is Referenced to REFIN Pin 95 100 105 mV IOUT = 30 A, Voltage is Referenced to REFIN Pin 142.5 150 157.5 mV IOUT = 40 A, Voltage is Referenced to REFIN Pin 190 200 210 mV − 350 − mV 30 − − V Source Current = 100 mA − 0.96 − W Sink Current = 100 mA − 0.29 − W − 0.800 − V − 1.600 − V − 8 − mV/°C − 850 − mA 5 VCC, 25°C − 40 − mA Over−Temperature Warning Accuracy Driver IC Temperature − 140 − °C OTW Hysteresis Driver IC Temperature − 15 − °C tD_ILimit−COMP Input Signal = 380 mV, dv/dt = 0.2 mV/nsec. − 60 − ns 74 80 86 A IMON OPERATING RANGE ( TA = TJ = −405C to 1255C, VCC = 4.5 V to 5.5 V, VIN = 4.5 − 20 V) VIMON Dynamic range at IMON pin IMON ACCURACY (TA = 255C to 1255C, VCC/PVCC = 5 V, VIN = 19 V) (Note 3) IMON_SLOPE VIMON_10A VIMON_20A VIMON_30A IMON_SLOPE RIMON = 1 kW resistor placed from IMON to REFIN. Current Monitor Voltage (VIMON−REFIN) VIMON_40A BOOTSTRAP DIODE Forward Voltage VF Breakdown Voltage VR Forward Bias Current = 10 mA LOW−SIDE DRIVER Output Impedance, Sourcing Output Impedance, Sinking RSOURCE_GL RSINK_GH THERMAL MONITOR VOLTAGE VTMON_25C VTMON_125C Thermal TA = TJ = 25°C Monitor Voltage TA = TJ = 125°C VTMON_SLOPE ISOURCE_TMON ISINK_TMON TMON Source 5 VCC, 25°C Current TMON Sink Current OVER−TEMPERATURE WARNING FAULT HS CYCLE−BY−CYCLE POSITIVE I−LIMIT I−limit comparator input−output propagation delay. Over−Current Limit ILIM www.onsemi.com 7 NCV303150 Table 5. ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VIN = 19 V, VDISB# = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit − 8 − A INOCP_LOW − −50 − A RUP_PWM − 21 − kW Pull−Down Impedance RDOWN_PWM − 10 − kW 3−State Open Voltage VPWM_HIZ 1.4 1.65 1.85 V VZCD_HI − − 2.55 V ZCD_EN input Voltage Mid−state VZCD_MID 1.4 − 2.0 V ZCD_EN input Voltage Low VZCD_LO 0.6 − − V HS CYCLE−BY−CYCLE POSITIVE I−LIMIT OCP Hysteresis ILIM_HYS NEGATIVE OVER−CURRENT (NOCP) FAULT NOCP Trip LOW Level ZCD_EN INPUT Pull−Up Impedance ZCD_EN input Voltage High Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Imon performance is guaranteed by independent ATE testing of High−side and Low−side slope and offset. www.onsemi.com 8 NCV303150 MOSFET TYPICAL CHARACTERISTICS (Tests at TA = 25°C, unless otherwise specified) High Side Low Side TJ = 25°C 10 TJ = 125°C 1 0.001 1000 ID, DRAIN CURRENT (A) IAS AVALANCHE CURRENT (A) 100 0.01 1 0.1 10 TJ = 25°C 10 TJ = 125°C 1 0.001 100 0.01 1 0.1 10 100 300 tAV, TIME IN AVALANCHE (ms) tAV, TIME IN AVALANCHE (ms) Figure 4. Highside FET Unclamped Inductive Switching Capability Figure 5. Lowside FET Unclamped Inductive Switching Capability 1000 This area is limited by RDS(on) 10 ms 100 10 100 ms 1 ms 10 ms 100 ms 1s 10 s DC 1 Single Pulse 0.1 T = Max Rated J RqJA = 117°C/W T = 25°C 0.01 A 0.01 0.1 Curve bent to measured data 1 10 ID, DRAIN CURRENT (A) IAS AVALANCHE CURRENT (A) 100 100 This area is limited by RDS(on) 10 ms 100 100 ms 10 1 ms 10 ms 100 ms 1 Single Pulse 0.1 T = Max rated J RqJA = 155°C/W T = 25°C 0.01 A 0.01 0.1 1s 10 s DC Curve bent to measured data 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 6. Highside FET Forward Biased Safe Operating Area Figure 7. Lowside FET Forward Biased Safe Operating Area www.onsemi.com 9 100 NCV303150 TYPICAL CHARACTERISTICS (Tests at TA = 25°C, VCC = 5 V, VIN = 19 V, and VO = 1 V unless otherwise specified) Figure 8. Power Loss vs. Output Current Figure 9. Power Loss vs. Switching Frequency Figure 10. Power Loss vs. Input Voltage Figure 11. Power Loss vs. Driver Voltage Figure 12. Efficiency vs. Output Load Figure 13. Driver Supply Current vs. Switching Frequency www.onsemi.com 10 NCV303150 TYPICAL CHARACTERISTICS (Tests at TA = 25°C, VCC = 5 V, VIN = 19 V, and VO = 1 V unless otherwise specified) Figure 14. Driver Current vs. Driver Voltage Figure 15. Driver Current vs. Output Current Figure 16. UVLO Threshold vs. Temperature Figure 17. PWM Threshold vs. Driver Voltage Figure 18. PWM Threshold vs. Temperature Figure 19. Quiescent Current vs. Driver Voltage www.onsemi.com 11 NCV303150 TYPICAL CHARACTERISTICS (Tests at TA = 25°C, VCC = 5 V, VIN = 19 V, and VO = 1 V unless otherwise specified) Figure 20. Quiescent Current vs. Temperature Figure 21. EN Threshold vs. Driver Voltage Figure 22. EN Threshold vs. Temperature Figure 23. IMON Accuracy vs. Temperature Figure 24. IMON Accuracy vs. Switching Frequency Figure 25. IMON Accuracy vs. Input Voltage www.onsemi.com 12 NCV303150 TYPICAL CHARACTERISTICS (Tests at TA = 25°C, VCC = 5 V, VIN = 19 V, and VO = 1 V unless otherwise specified) Figure 26. IMON Accuracy vs. Driver Voltage Figure 27. Continuous Current Derating www.onsemi.com 13 NCV303150 FUNCTIONAL DESCRIPTION With ZCD_EN set high, if PWM falls to less than VPWM_HI, but stays above VPWM_LO, GL will go high after the non−overlap delay, and stay high for the duration of the ZCD Blanking time. Once this timer has elapsed, VSW will be monitored for zero current, and GL will be pulled low when zero current is detected. With ZCD_EN set mid (open), if the PWM goes to low, GL will go high after the non−overlap delay, and stay high for the duration of the ZCD Blanking time. Once this timer has elapsed, VSW will be monitored for zero current, and GL will be pulled low when zero current is detected. The SPS NCV303150 is a driver plus MOSFET module optimized for the synchronous buck converter topology. A PWM input signal is required to properly drive the high−side and the low−side MOSFETs. The part is capable of driving speed up to 1 MHz. DISB# and UVLO The SPS NCV303150 is enabled by both DISB# pin input signal and VCC UVLO. Table 6 summarizes the enable and disable logics. With DISB# low and VCC UVLO, SPS is fully shut down. If VCC is ready but DISB# is low, SPS goes into sleep mode with very low Quiescent current, where only critical circuitry are alive. The part should also read fuses/program itself during this state. PWM The PWM Input pin is a tri−state input used to control the HS MOSFET ON/OFF state. It also determines the state of the LS MOSFET. See Table 7 for logic operation with ZCD_EN. There is a minimum PWM pulse width, typical at 37 ns (SW gate rising 10% to falling 10%), if the PWM input pulse width is shorter than that, the driver will extend the pulse width to 37 ns. If the PWM input is shorter than 5 ns, the driver will ignore it. Table 6. UVLO AND DRIVER STATE VCC UVLO DISB# Driver State 0 X Full driver shutdown (GH, GL=0), requires 40 ms for start−up 1 0 Partial driver shutdown (GH, GL=0), requires 30 ms for startup 1 1 Enabled (GH/GL follow PWM) X Open/0 Table 7. LOGIC TABLE Disabled (GH, GL=0) INPUT TRUTH TABLE NCV303150 needs 40 ms time to go from fully shutdown mode to power ready mode. The time is 30 ms to go from partial shutdown mode to power ready mode. Before power is ready, FAULT pin is strongly pulled low with a 50 W resistor. As a result, FAULT pin can also be used as a power ready indicator. Zero Current Detect Enable Input (ZCD_EN) The ZCD_EN pin is a logic input pin with an internal voltage divider connected to VCC. When ZCD_EN is set low, the NCV303150 will operate in synchronous rectifier (PWM) mode. This means that negative current can flow in the LS MOSFET if the load current is less than 1/2 delta current in the inductor. When ZCD_EN is set high, Zero Current Detect PWM (ZCD_PWM) mode will be enabled. DISB# ZCD_EN PWM GH GL L X X L L H H H H L H H L L H H H MID L ZCD H L H H L H L L L H H L MID L L H MID H H L H MID L L ZCD H MID MID L L www.onsemi.com 14 NCV303150 VIH_PWM VIL_PWM PWM GL GH−PHASE 90% 90% 10% 10% 90% 90% 10% 10% BOOT−GND PV CC −V F_DBOOT −1V 90% SW t PD_PHGLL tD_DEADON t RISE _GH t FALL _GL t PD_PLGHL tD_DEADOFF t FALL _GH tRISE _GL tPD_PHGLL = PWM HI to GL LO , V IH_PWM to 90% GL tPD _PLGLH tFALL_GL = 90% GL to 10% GL tD_DEADON = LS Off to HS On Dead Time , 10% GL to V BOOT−GND DISB# HIGH: Typical 5 VDC −> VIN On: Typical 19 VDC −> PWM Signaling: 3.3 V HIGH/ 0 V LOW The VIN pins are tied to the system main DC power rail. The DISB# pin can be tied to the VCC rail with an external pull−up resistor and it will maintain HIGH once the VCC rail turns on. Or the DISB# pin can be directly tied to the PWM controller for other purposes. The driver IC design ensures minimum MOSFET dead times, while eliminating potential shoot−through (cross−conduction) currents. To ensure optimal module efficiency, body diode conduction times must be reduced to the low nano−second range during CCM and DCM operation. Delay circuitry is added to prevent gate overlap during both the low−side MOSFET off to high−side MOSFET on transition and the high−side MOSFET off to low−side MOSFET on transition. Boot Capacitor Refresh NCV303150 monitors the low Boot−SW voltage. If DISB# and VCC are ready, but the voltage across the boot capacitor voltage is lower than 3.1 V, NCV303150 ignores the PWM input signal and starts the boot refresh circuit. The boot refresh circuit turns on the low side MOSFET with a 100 ns~200 ns narrow pulse in every 7~14 ms until Boot−SW voltage is above 3.6 V. High−Side Driver The high−side driver (HDRV) is designed to drive a floating N−channel MOSFET (Q1). The bias voltage for the high−side driver is developed by a bootstrap supply circuit, consisting of the internal Schottky diode and external bootstrap capacitor (CBOOT). During startup, the SW node is held at PGND, allowing CBOOT to charge to VCC through the internal bootstrap diode. When the PWM input goes HIGH, HDRV begins to charge the gate of the high−side MOSFET (internal GH pin). During this transition, the charge is removed from the CBOOT and delivered to the gate of Q1. As Q1 turns on, SW rises to VIN, forcing the BOOT pin to VIN + VBOOT, which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling HDRV to SW. CBOOT is then recharged to VCC when the SW falls to PGND. HDRV output is in phase with the PWM input. The high−side gate is held LOW when the driver is disabled or the PWM signal is held within the 3−state window for longer than the 3−state hold−off time, tD_HOLD−OFF. Current Monitor (IMON) The SPS current monitor accurately senses high−side and low−side MOSFET currents. The currents are summed together to replicate the output filter inductor current. The signal is reported from the SPS module in the form of a 5 mA/A current signal (IIMON−REFIN). The IMON signal will be referenced to an externally supplied signal (REFIN) and differentially sensed by an external analog/ digital PWM controller. The motivation for the IMON feature is to replace the industry standard output filter DCR sensing, or output current sense using an external precision resistor. Both techniques are lossy and lead to reduced system efficiency. Inductor DCR sensing is also notoriously inaccurate for low value DCR inductors. Figure 32 shows a comparison between conventional inductor DCR sensing and the unique IMON feature. The accuracy on IMON signal is ±5% from 10 A to 40 A output current. For the SPS module, parameters that can affect IMON accuracy are tightly controlled and trimmed at the MOSFET/IC production stage. The user can easily incorporate the IMON feature and accuracy replacing the traditional current sensing methods in multi−phase applications. Low−Side Driver The low−side driver (LDRV) is designed to drive the gate−source of a ground referenced low RDS(ON) N−channel MOSFET (Q2). The bias for LDRV is internally connected between VCC and PGND. When the driver is enabled, the driver’s output is 180° out of phase with the PWM input. When the driver is disabled, LDRV is held LOW. www.onsemi.com 18 NCV303150 Figure 32. DrMOS with Inductor DCR Sensing vs. SPS with IMON Fault Flag (FAULT) temperature. Driver still responds to PWM commands. Once the IC falls below 125°C, fault flag is cleared internally by driver IC. The TMON / FAULT pin on NCV303150 is a thermal monitor output in normal operation. Before power is ready, TMON pin is strongly pulled low with a 50 ohm resistor. As a result, it can be used as a power ready indicator. Also, this pin is used as a module FAULT flag pin if there is OCP boot UBLO or OTP. The TMON pin output is a Proportional to Absolute Temperature (PTAT) voltage sourced signal referenced to AGND when no module FAULT is present. It will typically output 0.6 V at 0°C and 1.8 V at 150°C with 8 mV / °C typical slope. TMON pins from multiple SPS modules (used in multi−phase topologies) can be tied together to share a common thermal bus. Operating with this configuration will force the thermal bus signal to report the highest voltage output TMON signal to the controller (highest temperature). The TMON output has a low output impedance when sourcing current and a high output impedance when sinking current. The TMON signal reported from the module pin is a buffered version of an internal TMON signal. Configuring the SPS module to share a common thermal bus will still permit each module to safely monitor its own temperature since the internal TMON signal is unaffected by the common thermal bus configuration. An over temperature event is considered catastrophic in nature. OTW raises fault flag HIGH once it exceeds 140°C Over−Current Protection (OCP) The NCV303150 has cycle−by−cycle over−current protection. If current exceeds the OCP threshold, HS FET is gated off regardless of PWM command. HS FET cannot be gated on again until the current is less than the OCP threshold with a hysteresis. Fault flag will be pulled HIGH after ten consecutive cycle−by−cycle OCPs are detected. Fault flag will clear once OCP is NOT detected. Module never shuts down nor does it disable HDRV/LDRV (but driver will still truncate HS on time when PWM=HIGH and ILIM is detected). Negative−OCP The NCV303150 can detect large negative inductor current and protect the low side MOSFET. Once this Negative current threshold is detected the driver module takes control and truncates LS on−time pulse (LS FET is gated off regardless of PWM command). The driver will stay in this state till one of two things happen 1) 200 ns expires in which case if the PWM pin is commanding the driver to turn on LS, the driver will respond and NOCP will again be monitored 2) PWM commands HS on in which case the driver will immediately turn on HS regardless of the 200 ns Timer. www.onsemi.com 19 NCV303150 APPLICATION INFORMATION Decoupling Capacitor for VCC be sized properly to not generate excessive heating due to high power dissipation. Decoupling capacitor on VCC and BOOT capacitor should be placed as close as possible to the VCC ~ AGND and BOOT ~ PHASE pin pairs to ensure clean and stable power supply. Their routing traces should be wide and short to minimize parasitic PCB resistance and inductance. The board layout should include a placeholder for small−value series boot resistor on BOOT ~ PHASE. The boot−loop size, including series RBOOT and CBOOT, should be as small as possible. A boot resistor may be required and it is effective to control the high−side MOSFET turn−on slew rate and SW voltage overshoot. RBOOT can improve noise operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative VSW ringing. Inserting a boot resistance lowers the SPS module efficiency. Efficiency versus switching noise must be considered. RBOOT values from 0.5 W to 6.0 W are typically effective in reducing VSW overshoot. The VIN and PGND pins handle large current transients with frequency components greater than 100 MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is not recommended since this adds extra parasitic inductance to the power path. This added inductance in series with either the VIN or PGND pin degrades system noise immunity by increasing positive and negative VSW ringing. PGND pad and pins should be connected to the GND copper plane with multiple vias for stable grounding. Poor grounding can create a noisy and transient offset voltage level between PGND and AGND. This could lead to faulty operation of gate driver and MOSFETs. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add any additional capacitors between BOOT to PGND. This may lead to excess current flow through the BOOT diode, causing high power dissipation. Put multiple vias on the VIN and VOUT copper areas to interconnect top, inner, and bottom layers to evenly distribute current flow and heat conduction. Do not put too many vias on the SW copper to avoid extra parasitic inductance and noise on the switching waveform. As long as efficiency and thermal performance are acceptable, place only one SW node copper on the top layer and put no vias on the SW copper to minimize switch node parasitic noise. Vias should be relatively large and of reasonably low inductance. Critical high−frequency components; such as RBOOT, CBOOT, RC snubber, and bypass capacitors; should be located as close to the respective SPS module pins as possible on the top layer of the PCB. If this is not feasible, they can be placed on the board bottom side and their pins connected from bottom to top through a network of low−inductance vias. For the supply input (VCC pin), local decoupling capacitor is required to supply the peak driving current and to reduce noise during switching operation. Use at least 0.68 ~ 2.2 mF/ 0402 ~ 0603/ X5R ~ X7R multi−layer ceramic capacitor for the power rail. Keep this capacitor close to the VCC pin and AGND copper planes. If it needs to be located on the bottom side of board, put through−hole vias on each pad of the decoupling capacitor to connect the capacitor pad on bottom with VCC pin on top. The supply voltage range on VCC is 4.5 V ~ 5.5 V, typically 5 V for normal applications. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBOOT). A bootstrap capacitor of 0.1 ~ 0.22 mF/ 0402 ~ 0603/ X5R ~ X7R is usually appropriate for most switching applications. A series bootstrap resistor may be needed for specific applications to lower high−side MOSFET switching speed. The boot resistor is required when the SPS is switching above 15 V VIN; when it is effective at controlling VSW overshoot. RBOOT value from 2.2 to 6 W is typically recommended to reduce excessive voltage spike and ringing on the SW node. A higher RBOOT value can cause lower efficiency due to high switching loss of high−side MOSFET. Do not add a capacitor or resistor between the BOOT pin and GND. It is recommended to add a PCB place holder for a small size 1 nF ~ 1 mF capacitor close to the REFIN pin and AGND to reduce switching noise injection. It is also recommended to add a small 10 ~ 47 pF capacitor in parallel with the IMON resistor from IMON to REFIN. This capacitor can help reduce switching noise coupling onto the IMON signal. The place of the IMON resistor and cap should be close to the controller, not the SPS to improve the sensing accuracy. PCB Layout Guideline All of the high−current paths; such as VIN, SW, VOUT, and GND coppers; should be short and wide for low parasitic inductance and resistance. This helps achieve a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. Input ceramic bypass capacitors must be close to the VIN and PGND pins. This reduces the high−current power loop inductance and the input current ripple induced by the power MOSFET switching operation. An output inductor should be located close to the NCV303150 to minimize the power loss due to the SW copper trace. Care should also be taken so the inductor dissipation does not heat the SPS. PowerTrench® MOSFETs are used in the output stage and are effective at minimizing ringing due to fast switching. In most cases, no RC snubber on SW node is required. If a snubber is used, it should be placed close to the SW and PGND pins. The resistor and capacitor of the snubber must www.onsemi.com 20 NCV303150 PCB Layout Guideline (Continued) Figure 33. Layout Example – Top View Figure 34. Layout Example – Bottom Layer www.onsemi.com 21 NCV303150 Evaluation Board Information The NCV303150 evaluation board (EVB) is 70 mm x 70 mm with 6 total layers. All layers have a 2−oz. copper finish. Figure 35. EVB Top Layer Figure 36. EVB Inner Layer 1 Figure 37. EVB Inner Layer 2 Figure 38. EVB Inner Layer 3 www.onsemi.com 22 NCV303150 Evaluation Board Information The NCV303150 evaluation board (EVB) is 70 mm x 70 mm with 6 total layers. All layers have a 2−oz. copper finish. Figure 39. EVB Inner Layer 4 Figure 40. EVB Bottom Layer Figure 41. EVB Silkscreen Top Figure 42. EVB Bottom Layer POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC. Intel is a registered trademark of Intel Corporation. www.onsemi.com 23 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WQFNW39 5x6, 0.45P CASE 512AM ISSUE A DATE 06 APR 2021 A B 10 19 10 20 9 GENERIC MARKING DIAGRAM* XXXXXXXX XXXXXXXX AWLYYWWG G DOCUMENT NUMBER: DESCRIPTION: 29 1 39 30 39 20 9 29 1 19 XXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) 98AON16878H WQFNW39 5x6, 0.45P 30 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WQFNW39 5x6, 0.45P CASE 512AM ISSUE A DATE 06 APR 2021 EXPOSED COPPER DOCUMENT NUMBER: DESCRIPTION: 98AON16878H WQFNW39 5x6, 0.45P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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