Voltage Regulator Adjustable Output, Positive
100 mA
LM317L, NCV317L
The LM317L is an adjustable 3−terminal positive voltage regulator
capable of supplying in excess of 100 mA over an output voltage range
of 1.2 V to 37 V. This voltage regulator is exceptionally easy to use
and requires only two external resistors to set the output voltage.
Further, it employs internal current limiting, thermal shutdown and
safe area compensation, making them essentially blow−out proof.
The LM317L serves a wide variety of applications including local,
on card regulation. This device can also be used to make a
programmable output regulator, or by connecting a fixed resistor
between the adjustment and output, the LM317L can be used as a
precision current regulator.
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LOW CURRENT
THREE−TERMINAL
ADJUSTABLE POSITIVE
VOLTAGE REGULATOR
Features
•
•
•
•
•
•
•
•
•
•
Output Current in Excess of 100 mA
Output Adjustable Between 1.2 V and 37 V
Internal Thermal Overload Protection
Internal Short Circuit Current Limiting
Output Transistor Safe−Area Compensation
Floating Operation for High Voltage Applications
Standard 3−Lead Transistor Package
Eliminates Stocking Many Fixed Voltages
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
Simplified Application
Vin
Pin 1.
2.
3.
4.
5.
6.
7.
8.
8
1
SOIC−8
D SUFFIX
CASE 751
12
3
STRAIGHT LEAD
1
Vin
Vout
Vout
Adjust
N.C.
Vout
Vout
N.C.
2
3
BENT LEAD
Vout
LM317L
TO−92
Z SUFFIX
CASE 29−10
R1
240
Pin 1. Adjust
2. Vout
3. Vin
IAdj
Adjust
Cin*
0.1mF
+ C **
O
1.0mF
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
R2
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 9 of this data sheet.
* Cin is required if regulator is located an appreciable
** distance from power supply filter.
** CO is not needed for stability, however,
** it does improve transient response.
ǒ
Ǔ
R
Vout + 1.25V 1 ) 2 ) IAdjR2
R1
Since IAdj is controlled to less than 100 mA, the error
associated with this term is negligible in most applications.
© Semiconductor Components Industries, LLC, 2013
April, 2021 − Rev. 14
1
Publication Order Number:
LM317L/D
LM317L, NCV317L
MAXIMUM RATINGS
Symbol
Value
Unit
Input−Output Voltage Differential
Rating
VI−VO
40
Vdc
Power Dissipation
Case 29 (TO−92)
TA = 25°C
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
PD
RqJA
RqJC
Internally Limited
160
83
W
°C/W
°C/W
Case 751 (SOIC−8) (Note 1)
TA = 25°C
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
PD
RqJA
RqJC
Internally Limited
180
45
W
°C/W
°C/W
TJMAX
+150
°C
Tstg
−65 to +150
°C
Maximum Junction Temperature
Storage Temperature Range
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. SOIC−8 Junction−to−Ambient Thermal Resistance is for minimum recommended pad size. Refer to Figure 24 for Thermal Resistance
variation versus pad size.
2. This device series contains ESD protection and exceeds the following tests:
Human Body Model, 2000 V per MIL STD 883, Method 3015.
Machine Model Method, 200 V.
Vin
300
300
300
3.0k
70
300
6.8V
6.8V
350
18k
8.67k
500
130
400
5.1k
200k
6.3V
180 180
2.0k
6.0k
60
10
p 10
F p
F
Vout
2.4k
12.8k
Figure 1. Representative Schematic Diagram
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2
2.5
50
Adjust
LM317L, NCV317L
ELECTRICAL CHARACTERISTICS
(VI−VO = 5.0 V; IO = 40 mA; TJ = Tlow to Thigh (Note 3); Imax and Pmax (Note 4); unless otherwise noted.)
LM317L, LB, NCV317LB
Characteristics
Figure
Symbol
Min
Typ
Max
Unit
Line Regulation (Note 5)
TA = 25°C, 3.0 V ≤ VI − VO ≤ 40 V
1
Regline
−
0.01
0.04
%/V
Load Regulation (Note 5), TA = 25°C
10 mA ≤ IO ≤ Imax − LM317L
VO ≤ 5.0 V
VO ≥ 5.0 V
2
Regload
−
−
5.0
0.1
25
0.5
mV
% VO
Adjustment Pin Current
3
IAdj
−
50
100
mA
Adjustment Pin Current Change
2.5 V ≤ VI − VO ≤ 40 V, PD ≤ Pmax
10 mA ≤ IO ≤ Imax − LM317L
1, 2
DIAdj
−
0.2
5.0
mA
Reference Voltage
3.0 V ≤ VI − VO ≤ 40 V, PD ≤ Pmax
10 mA ≤ IO ≤ Imax − LM317L
3
Vref
1.20
1.25
1.30
V
Line Regulation (Note 5), 3.0 V ≤ VI − VO ≤ 40 V
1
Regline
−
0.02
0.07
%/V
Load Regulation (Note 5)
10 mA ≤ IO ≤ Imax − LM317L
VO ≤ 5.0 V
VO ≥ 5.0 V
2
Regload
−
−
20
0.3
70
1.5
mV
% VO
Temperature Stability (Tlow ≤ TJ ≤ Thigh)
3
TS
−
0.7
−
% VO
Minimum Load Current to Maintain Regulation (VI − VO = 40 V)
3
ILmin
−
3.5
10
mA
Maximum Output Current
VI − VO ≤ 6.25 V, PD ≤ Pmax, Z Package
VI − VO ≤ 40 V, PD ≤ Pmax, TA = 25°C, Z Package
3
Imax
100
−
200
20
−
−
RMS Noise, % of VO
TA = 25°C, 10 Hz ≤ f ≤ 10 kHz
−
N
−
0.003
−
Ripple Rejection (Note 6)
VO = 1.2 V, f = 120 Hz
CAdj = 10 mF, VO = 10.0 V
4
RR
60
−
80
80
−
−
Thermal Shutdown (Note 7)
−
−
−
180
−
°C
Long Term Stability, TJ = Thigh (Note 8)
TA = 25°C for Endpoint Measurements
3
S
−
0.3
1.0
%/1.0 k
Hrs.
3.
4.
5.
mA
% VO
dB
Tlow to Thigh = 0° to +125°C for LM317L
−40° to +125°C for LM317LB, NCV317LB
Pmax = 625 mW
Imax = 100 mA
Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account
separately. Pulse testing with low duty cycle is used.
6. CAdj, when used, is connected between the adjustment pin and ground.
7. Thermal characteristics are not subject to production test.
8. Since Long−Term Stability cannot be measured on each device before shipment, this specification is an engineering estimate of average
stability from lot to lot.
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3
LM317L, NCV317L
VCC
VOH - VOL
VOL
Line Regulation (%/V) =
*
x 100
VIH
VIL
VOH
VOL
Vout
Vin
LM317L
Adjust
Cin
0.1mF
240
1%
R1
RL
+
CO
IAdj
1mF
R2
1
%
*Pulse Testing Required:
1% Duty Cycle is suggested.
Figure 2. Line Regulation and DIAdj/Line Test Circuit
Load Regulation (mV) = VO (min Load) -VO (max Load)
VO (min Load) - VO (max Load)
Load Regulation (% VO) =
VO (min Load)
Vin*
Vin
LM317L
Vout
Adjust
X
100
IL
R1
RL
(max Load)
240
1%
*
+
Cin
0.1mF
VO (min Load)
VO (max Load)
CO
IAdj
RL
(min Load)
1.0mF
R2
1%
*Pulse Testing Required:
1% Duty Cycle is suggested.
Figure 3. Load Regulation and DIAdj/Load Test Circuit
Vin
Vout
Adjust
R1
IAdj
VI
Cin
IL
LM317L
240
1%
Vref
CO
0.1mF
ISET
Pulse Testing Required:
1% Duty Cycle is suggested.
RL
+
To Calculate R2:
Vout = ISET R2 + 1.250 V
Assume ISET = 5.25 mA
R2
1%
Figure 4. Standard Test Circuit
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4
1mF
VO
LM317L, NCV317L
14.30V
Vout
Vin
4.30V
f = 120 Hz
Vout = 1.25 V
LM317L
Adjust
Cin
D1 *
1N4002
240
1%
R1
RL
+
CO
0.1mF
R2
VO
1mF
+
1.65K
1%
10mF
**
*D1 Discharges CAdj if Output is Shorted to Ground.
**CAdj provides an AC ground to the adjust pin.
0.4
Vin = 45 V
Vout = 5.0 V
IL = 5.0 mA to 40 mA
0.2
RR, RIPPLE REJECTION (dB)
Δ V out, OUTPUT VOLTAGE CHANGE (%)
Figure 5. Ripple Rejection Test Circuit
0
-0.2
Vin = 10 V
Vout = 5.0 V
IL = 5.0 mA to 100 mA
-0.4
-0.6
-0.8
80
70
IL = 40 mA
f = 120 Hz
Vout = 10 V
Vin = 14 V to 24 V
60
50
-1.0
-50
-25
0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (°C)
-50
150
-25
Figure 6. Load Regulation
V in -Vout , INPUT-OUTPUT VOLTAGE
DIFFERENTIAL (V)
2.5
TJ = 25°C
IO, OUTPUT CURRENT (A)
150
Figure 7. Ripple Rejection
0.50
0.40
0.30
0.20
TJ = 150°C
0.10
0
0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (°C)
0
10
20
30
40
Vin-Vout, INPUT-OUTPUT VOLTAGE DIFFERENTIAL (V)
2.0
IL = 100 mA
1.5
IL = 5.0 mA
1.0
0.5
50
Figure 8. Current Limit
-50
-25
0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Dropout Voltage
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5
150
LM317L, NCV317L
100
4.5
90
RR, RIPPLE REJECTION (dB)
IB , QUIESCENT CURRENT (mA)
5.0
TJ = 55°C
TJ = 25°C
TJ = 150°C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
IL = 40 mA
Vin = 5.0 V ± 1.0 VPP
Vout = 1.25 V
80
70
60
50
40
30
20
10
0
10
10
20
30
40
Vin-Vout, INPUT-OUTPUT VOLTAGE DIFFERENTIAL (V)
Figure 10. Minimum Operating Current
IAdj, ADJUSTMENT PIN CURRENT ( μA)
V ref , REFERENCE VOLTAGE (V)
10 k
100 k 1.0 M
f, FREQUENCY (Hz)
80
1.250
1.240
Vin = 4.2 V
Vout = Vref
IL = 5.0 mA
1.230
-50
-25
0
25
50
75 100 125
TJ, JUNCTION TEMPERATURE (°C)
65
60
55
50
45
40
35
150
Vin = 6.25 V
Vout = Vref
IL = 10 mA
IL = 100 mA
70
-50
Figure 12. Temperature Stability
0.4
Vin = 4.25 V to 41.25 V
Vout = Vref
IL = 5 mA
0.2
-25
0
25
50
75 100 125
TJ, JUNCTION TEMPERATURE (°C)
150
Figure 13. Adjustment Pin Current
NOISE VOLTAGE ( μV)
Δ Vout , OUTPUT VOLTAGE CHANGE (%)
1.0 k
Figure 11. Ripple Rejection versus Frequency
1.260
1.220
100
0
-0.2
-0.4
-0.6
Bandwidth 100 Hz to 10 kHz
10
8.0
6.0
-0.8
-1.0
4.0
-50
-25
0
25
50
75 100 125
TJ, JUNCTION TEMPERATURE (°C)
150
-50
Figure 14. Line Regulation
-25
0
25
50
75 100 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. Output Noise
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6
150
Δ Vout , OUTPUT VOLTAGE
DEVIATION (V)
1.5
1.0
CL = 1.0 mF;
CAdj = 10 mF
0.5
0
-0.5
Vout = 10 V
IL = 50 mA
TJ = 25°C
ΔV in , INPUT
VOTLAGE CHANGE (V)
-1.0
-1.5
1.0
Vin
0.5
0
0.3
0.2
CL = 1 mF; CAdj = 10 mF
0.1
Vin = 15 V
Vout = 10 V
INL = 50 mA
TJ = 25°C
0
-0.1
CL = 0.3 mF; CAdj = 10 mF
-0.2
CL = 0;
Without CAdj
I L , LOAD
CURRENT (mA)
ΔVout , OUTPUT
VOLTAGE DEVIATION (V)
LM317L, NCV317L
-0.3
100
IL
50
0
t, TIME (ms)
20
t, TIME (ms)
Figure 16. Line Transient Response
Figure 17. Load Transient Response
0
10
20
30
40
0
10
30
40
APPLICATIONS INFORMATION
Basic Circuit Operation
Load Regulation
The LM317L is a 3−terminal floating regulator. In
operation, the LM317L develops and maintains a nominal
1.25 V reference (Vref) between its output and adjustment
terminals. This reference voltage is converted to a
programming current (IPROG) by R1 (see Figure 13), and this
constant current flows through R2 to ground. The regulated
output voltage is given by:
The LM317L is capable of providing extremely good load
regulation, but a few precautions are needed to obtain
maximum performance. For best performance, the
programming resistor (R1) should be connected as close to
the regulator as possible to minimize line drops which
effectively appear in series with the reference, thereby
degrading regulation. The ground end of R2 can be returned
near the load ground to provide remote ground sensing and
improve load regulation.
Vout = Vref (1 +
R2
) + IAdj R2
R1
Since the current from the adjustment terminal (IAdj)
represents an error term in the equation, the LM317L was
designed to control IAdj to less than 100 mA and keep it
constant. To do this, all quiescent operating current is
returned to the output terminal. This imposes the
requirement for a minimum load current. If the load current
is less than this minimum, the output voltage will rise.
Since the LM317L is a floating regulator, it is only the
voltage differential across the circuit which is important to
performance, and operation at high voltages with respect to
ground is possible.
Vin
External Capacitors
A 0.1 mF disc or 1.0 mF tantalum input bypass capacitor
(Cin) is recommended to reduce the sensitivity to input line
impedance.
The adjustment terminal may be bypassed to ground to
improve ripple rejection. This capacitor (CAdj) prevents
ripple from being amplified as the output voltage is
increased. A 10 mF capacitor should improve ripple
rejection about 15 dB at 120 Hz in a 10 V application.
Although the LM317L is stable with no output
capacitance, like any feedback circuit, certain values of
external capacitance can cause excessive ringing. An output
capacitance (CO) in the form of a 1.0 mF tantalum or 25 mF
aluminum electrolytic capacitor on the output swamps this
effect and insures stability.
Vout
LM317L
+
R1
Vref
Adjust
IPROG
Vout
IAdj
R2
Vref = 1.25 V Typical
Figure 18. Basic Circuit Configuration
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7
LM317L, NCV317L
Protection Diodes
D1
When external capacitors are used with any IC regulator
it is sometimes necessary to add protection diodes to prevent
the capacitors from discharging through low current points
into the regulator.
Figure 14 shows the LM317L with the recommended
protection diodes for output voltages in excess of 25 V or
high capacitance values (CO > 10 mF, CAdj > 5.0 mF). Diode
D1 prevents CO from discharging thru the IC during an input
short circuit. Diode D2 protects against capacitor CAdj
discharging through the IC during an output short circuit.
The combination of diodes D1 and D2 prevents CAdj from
discharging through the IC during an input short circuit.
1N4002
Vin
Vout
LM317L
+
Cin
R1
CO
D2
Adjust
1N4002
R2
CAdj
Figure 19. Voltage Regulator with
Protection Diodes
+25V
Vout
LM317L
1.25k
Vin
Adjust
D1
1N4002
D1
1N914
R2
500
* To provide current limiting of IO
to the system ground, the source of
the current limiting diode must be tied to
a negative voltage below - 7.25 V.
Vin
Vout
LM317L
D2
1N914
+
1.0mF
120
Adjust
MPS2222
1N5314
Vref
R2 ≥
IDSS
R1 =
IO
VO
R1
TTL
Control
720
1.0k
VSS*
Vref
IOmax + IDSS
Minimum Vout = 1.25 V
VO < POV + 1.25 V + VSS
ILmin - IP < IO < 100 mA - IP
As shown O < IO < 95 mA
D1 protects the device during an input short circuit.
Figure 20. Adjustable Current Limiter
Figure 21. 5.0 V Electronic Shutdown Regulator
R1
Vin
Iout
R2
LM317L
Vout
IAdj
Adjust
Vout
Vin
LM317L
240
Ioutmax =
Vref
R1
Ioutmax =
Vref
R1 + R2
50k
Adjust
R2
1N4002
MPS2907
+
10mF
+ IAdj ^
1.25 V
R1
+ IAdj ^
1.25 V
R1 + R2
5.0 mA < Iout < 100 mA
Figure 22. Slow Turn−On Regulator
Figure 23. Current Regulator
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8
JUNCTION-TO-AIR ( °C/W)
R θ JA, THERMAL RESISTANCE
170
3.2
150
2.8
PD(max) for TA = 50°C
130
110
2.4
ÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
2.0
Graph represents symmetrical layout
90
L
70
1.6
2.0 oz.
Copper
L
1.2
3.0 mm
0.8
50
RθJA
30
0
10
0.4
20
30
40
PD, MAXIMUM POWER DISSIPATION (W)
LM317L, NCV317L
50
L, LENGTH OF COPPER (mm)
Figure 24. SOP−8 Thermal Resistance and Maximum
Power Dissipation versus P.C.B. Copper Length
MARKING DIAGRAMS
TO−92
CASE 29−10
SOIC−8
CASE 751
8
LM317
XXX
ALYW
1
1 2 3
XXX
A
L
Y
W
XXXXX
ALYW
G
XXXXX = 317LB, LM317
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W = Work Week
G
= Pb−Free Package
= LBZ, LZ, LZR
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Package
Shipping†
LM317LBDG
SOIC−8 (Pb−Free)
98 Units / Rail
LM317LBDR2G
SOIC−8 (Pb−Free)
2500/Tape & Reel
LM317LBZG
TO−92 (Pb−Free)
2000 Units / Bag
LM317LBZRAG
TO−92 (Pb−Free)
2000 Tape & Reel
TO−92 (Pb−Free)
2000 Ammo Pack
Device
LM317LBZRPG
Operating Temperature Range
TJ = −40°C to +125°C
NCV317LBDG*
SOIC−8 (Pb−Free)
98 Units / Rail
NCV317LBDR2G*
SOIC−8 (Pb−Free)
2500/Tape & Reel
NCV317LBZG*
TO−92 (Pb−Free)
2000 Units / Bag
NCV317LBZRAG*
TO−92 (Pb−Free)
2000 Tape & Reel
LM317LDG
SOIC−8 (Pb−Free)
98 Units / Rail
LM317LDR2G
SOIC−8 (Pb−Free)
2500/Tape & Reel
LM317LZG
TO−92 (Pb−Free)
2000 Units / Bag
LM317LZRAG
TO−92 (Pb−Free)
2000 Tape & Reel
LM317LZREG
TO−92 (Pb−Free)
2000 Tape & Reel
LM317LZRMG
TO−92 (Pb−Free)
2000 Ammo Pack
LM317LZRPG
TO−92 (Pb−Free)
2000 Ammo Pack
TJ = 0°C to +125°C
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV devices: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV Prefix for Automotive and Other Applications Requiring Unique Site
and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
SCALE 1:1
12
3
STRAIGHT LEAD
1
DATE 05 MAR 2021
2
3
BENT LEAD
STYLES AND MARKING ON PAGE 3
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
DATE 05 MAR 2021
STYLES AND MARKING ON PAGE 3
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
DATE 05 MAR 2021
STYLE 1:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
STYLE 2:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. ANODE
STYLE 5:
PIN 1. DRAIN
2. SOURCE
3. GATE
STYLE 6:
PIN 1. GATE
2. SOURCE & SUBSTRATE
3. DRAIN
STYLE 7:
PIN 1. SOURCE
2. DRAIN
3. GATE
STYLE 8:
PIN 1. DRAIN
2. GATE
3. SOURCE & SUBSTRATE
STYLE 9:
PIN 1. BASE 1
2. EMITTER
3. BASE 2
STYLE 10:
PIN 1. CATHODE
2. GATE
3. ANODE
STYLE 11:
PIN 1. ANODE
2. CATHODE & ANODE
3. CATHODE
STYLE 12:
PIN 1. MAIN TERMINAL 1
2. GATE
3. MAIN TERMINAL 2
STYLE 13:
PIN 1. ANODE 1
2. GATE
3. CATHODE 2
STYLE 14:
PIN 1. EMITTER
2. COLLECTOR
3. BASE
STYLE 15:
PIN 1. ANODE 1
2. CATHODE
3. ANODE 2
STYLE 16:
PIN 1. ANODE
2. GATE
3. CATHODE
STYLE 17:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
STYLE 18:
PIN 1. ANODE
2. CATHODE
3. NOT CONNECTED
STYLE 19:
PIN 1. GATE
2. ANODE
3. CATHODE
STYLE 20:
PIN 1. NOT CONNECTED
2. CATHODE
3. ANODE
STYLE 21:
PIN 1. COLLECTOR
2. EMITTER
3. BASE
STYLE 22:
PIN 1. SOURCE
2. GATE
3. DRAIN
STYLE 23:
PIN 1. GATE
2. SOURCE
3. DRAIN
STYLE 24:
PIN 1. EMITTER
2. COLLECTOR/ANODE
3. CATHODE
STYLE 25:
PIN 1. MT 1
2. GATE
3. MT 2
STYLE 26:
PIN 1.
2.
3.
STYLE 27:
PIN 1. MT
2. SUBSTRATE
3. MT
STYLE 28:
PIN 1. CATHODE
2. ANODE
3. GATE
STYLE 29:
PIN 1. NOT CONNECTED
2. ANODE
3. CATHODE
STYLE 30:
PIN 1. DRAIN
2. GATE
3. SOURCE
STYLE 32:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
STYLE 33:
PIN 1. RETURN
2. INPUT
3. OUTPUT
STYLE 34:
PIN 1. INPUT
2. GROUND
3. LOGIC
STYLE 35:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
VCC
GROUND 2
OUTPUT
STYLE 31:
PIN 1. GATE
2. DRAIN
3. SOURCE
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 3 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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