NCV33375ST1.8T3G

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These devices feature a very low quiescent current and are capable of supplying output currents up to 300 mA. Internal current and thermal limiting protection are provided by the presence of a short circuit at the output and an internal thermal shutdown circuit. The MC33375 has a control pin that allows a logic level signal to turn−off or turn−on the regulator output. Due to the low input−to−output voltage differential and bias current specifications, these devices are ideally suited for battery powered computer, consumer, and industrial equipment where an extension of useful battery life is desirable. Features: www.onsemi.com LOW DROPOUT MICROPOWER VOLTAGE REGULATOR MARKING DIAGRAMS 4 1 • Low Quiescent Current (0.3 A in OFF mode; 125 A in ON mode) • Low Input−to−Output Voltage Differential of 25 mV at IO = 10 mA, • • • • • • and 260 mV at IO = 300 mA Extremely Tight Line and Load Regulation Stable with Output Capacitance of only 0.33 F for 2.5 V Output Voltage Internal Current and Thermal Limiting Logic Level ON/OFF Control NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These are Pb−Free Devices Vin SOT−223 ST SUFFIX CASE 318E AYM 375xx G G 1 8 8 1 375xx ALYW G SOIC−8 D SUFFIX CASE 751 1 A = Assembly Location Y = Year M = Date Code L = Wafer Lot W = Work Week xx = Voltage Version G = Pb−Free Package (Note: Microdot may be in either location) Vout ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. Thermal & Anti−sat Protection On/Off Rint On/Off Block 1.23 V V. Ref. 54 K GND This device contains 41 active transistors Figure 1. Simplified Block Diagram © Semiconductor Components Industries, LLC, 2013 January, 2020 − Rev. 18 1 Publication Order Number: MC33375/D MC33375, NCV33375 Series PIN CONNECTIONS Gnd 4 Input Gnd Gnd 1 ON/OFF 2 3 Vin ON/ Vout OFF 1 8 2 7 3 6 4 5 Output Gnd Gnd N/C MAXIMUM RATINGS Rating Symbol Value Unit VCC 13 Vdc PD Internally Limited W RJA RJC 160 25 °C/W °C/W RJA RJC 245 15 °C/W °C/W Output Current IO 300 mA Maximum Junction Temperature TJ 150 °C Operating Ambient Temperature Range TA − 40 to +125 °C Storage Temperature Range Tstg − 65 to +150 °C Input Voltage Power Dissipation and Thermal Characteristics TA = 25°C Maximum Power Dissipation Case 751 (SOP−8) D Suffix Thermal Resistance, Junction−to−Ambient Thermal Resistance, Junction−to−Case Case 318E (SOT−223) ST Suffix Thermal Resistance, Junction−to−Air Thermal Resistance, Junction−to−Case Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2 MC33375, NCV33375 Series ELECTRICAL CHARACTERISTICS (CL = 1.0 F, TA = 25°C, for min/max values TJ = −40°C to +125°C, Note 1) Symbol Characteristic Output Voltage 1.8 V Suffix 2.5 V Suffix 3.0 V Suffix 3.3 V Suffix 5.0 V Suffix IO = 0 mA to 250 mA TA = 25°C, Vin = [VO + 1] V VO Min Typ Max 1.782 2.475 2.970 3.267 4.950 1.80 2.50 3.00 3.30 5.00 1.818 2.525 3.030 3.333 5.05 1.764 2.450 2.940 3.234 4.900 − − − − − 1.836 2.550 3.060 3.366 5.100 Unit Vdc 1.8 V Suffix 2.5 V Suffix 3.0 V Suffix 3.3 V Suffix 5.0 V Suffix Vin = [VO + 1] V, 0 < IO < 100 mA 2% Tolerance from TJ = −40 to +125°C Line Regulation Vin = [VO + 1] V to 12 V, IO = 250 mA, All Suffixes TA = 25°C Regline − 2.0 10 mV Load Regulation Vin = [VO + 1] V, IO = 0 mA to 250 mA, All Suffixes TA = 25°C Regload − 5.0 25 mV − − − − 25 115 220 260 100 200 400 500 65 75 − − − 160 46 − − IQOn − 125 200 A IQOff − 0.3 4.0 A − − − 1500 1500 1500 2000 2000 2000 − 450 − 2.4 − − − − − − 0.5 0.3 − 150 − Dropout Voltage (Note 3) TJ = −40°C to +125°C IO = 10 mA IO = 100 mA IO = 250 mA IO = 300 mA Ripple Rejection (120 Hz) Vin − VO Vin(peak−peak) = [VO + 1.5] V to [VO + 5.5] V Output Noise Voltage CL = 1.0 F IO = 50 mA (10 Hz to 100 kHz) CL = 200 F − Vn mV dB Vrms CURRENT PARAMETERS Quiescent Current ON Mode Vin = [VO + 1] V, IO = 0 mA Quiescent Current OFF Mode Quiescent Current ON Mode SAT 3.0 V Suffix 3.3 V Suffix 5.0 V Suffix Vin = [VO − 0.5] V, IO = 0 mA (Notes 2, 4) IQSAT Current Limit Vin = [VO + 1] V, VO Shorted ILIMIT A mA ON/OFF INPUTS On/Off Input Voltage Logic “1” (Regulator On) Vout = VO ± 2% Logic “0” (Regulator Off) Vout < 0.03 V Logic “0” (Regulator Off) Vout < 0.05 V (1.8 V Option) VCTRL V THERMAL SHUTDOWN Thermal Shutdown 1. 2. 3. 4. − Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Quiescent Current is measured where the PNP pass transistor is in saturation. Vin = [VO − 0.5] V guarantees this condition. For 1.8 V version VDO is constrained by the minimum input voltage of 2.5 V. For 1.8 V and 2.5 V versions, IQSAT is constrained by the minimum input voltage of 2.5 V. www.onsemi.com 3 °C MC33375, NCV33375 Series DEFINITIONS Load Regulation − The change in output voltage for a change in load current at constant chip temperature. Dropout Voltage − The input/output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 100 mV below its nominal value (which is measured at 1.0 V differential), dropout voltage is affected by junction temperature, load current and minimum input supply requirements. Output Noise Voltage − The RMS AC voltage at the output with a constant load and no input ripple, measured over a specified frequency range. Maximum Power Dissipation − The maximum total dissipation for which the regulator will operate within specifications. Quiescent Current − Current which is used to operate the regulator chip and is not delivered to the load. Line Regulation − The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Maximum Package Power Dissipation − The maximum package power dissipation is the power dissipation level at which the junction temperature reaches its maximum value i.e. 150°C. The junction temperature is rising while the difference between the input power (VCC X ICC) and the output power (Vout X Iout) is increasing. Depending on ambient temperature, it is possible to calculate the maximum power dissipation and so the maximum current as following: T –T Pd + J A R JA The maximum operating junction temperature TJ is specified at 150°C, if TA = 25°C, then PD can be found. By neglecting the quiescent current, the maximum power dissipation can be expressed as: I out + P D V – Vout CC The thermal resistance of the whole circuit can be evaluated by deliberately activating the thermal shutdown of the circuit (by increasing the output current or raising the input voltage for example). Then you can calculate the power dissipation by subtracting the output power from the input power. All variables are then well known: power dissipation, thermal shutdown temperature (150°C for MC33375) and ambient temperature. R www.onsemi.com 4 T –T + J A JA P D MC33375, NCV33375 Series 7 150 TA = 25° C 6 CL = 33 F IL = 10 mA 5 Vout = 3.3 V 100 4 50 3 0 2 Vout -50 1 0 0 20 40 60 80 100 120 140 160 70 60 Vin Vin , INPUT VOLTAGE (V) Vin 200 40 4 30 3 20 10 2 0 Vout 1 0 50 100 Figure 3. Line Transient Response 1.0 300 0 -300 Vout CHANGE -400 CL = 1.0 F Vout = 3.3 V -500 TA = 25° C -600 Vin = 4.3 V 0 50 -0.2 -0.4 -0.6 -0.8 100 150 200 250 300 350 LOAD CURRENT (mA) LOAD CURRENT (mA) 0.2 LOAD CURRENT 150 -50 0.04 -150 -0.01 -250 -350 CL = 33.0 F Vout = 3.3 V TA = 25° C Vin = 4.3 V Vout CHANGE -450 -550 -0.06 -0.11 -650 -750 -1.0 400 -0.16 0 50 TIME (S) 100 150 200 250 300 TIME (S) Figure 5. Load Transient Response Figure 4. Load Transient Response 300 3.5 3.0 IL = 1 mA 2.5 DROPOUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 0.09 50 OUTPUT VOLTAGE CHANGE (V) 0.4 -200 0.14 250 0.6 OUTPUT VOLTAGE CHANGE (V) LOAD CURRENT -100 -700 350 0.8 0 -20 200 150 TIME (S) Figure 2. Line Transient Response 100 -10 0 -100 180 200 TIME (S) 200 50 OUTPUT VOLTAGE CHANGE (mV) TA = 25° C 6 CL = 0.47 F IL = 10 mA 5 Vout = 3.3 V OUTPUT VOLTAGE CHANGE (mV) Vin , INPUT VOLTAGE (V) 7 IL = 250 mA 2.0 1.5 1.0 250 200 150 100 50 0.5 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1 4.5 5.0 10 100 1000 INPUT VOLTAGE (V) IO, OUTPUT CURRENT (mA) Figure 6. Output Voltage versus Input Voltage Figure 7. Dropout Voltage versus Output Current www.onsemi.com 5 MC33375, NCV33375 Series 12 250 10 IL = 300 mA 8 200 Ignd (mA) DROPOUT VOLTAGE (mV) 300 IL = 250 mA 150 IL = 100 mA 100 50 4 0 IL = 100 mA 2 IL = 10 mA 0 -40 IL = 300 mA 6 IL = 50 mA 25 0 85 0 1 2 3 TEMPERATURE (°C) 4 5 6 7 8 Vin (VOLTS) Figure 9. Ground Pin Current versus Input Voltage Figure 8. Dropout Voltage versus Temperature 2.5 8 7 IL = 250 mA IO = 0 2.495 Vout (VOLTS) Ignd (mA) 6 5 4 3 IL = 100 mA 2.49 IO = 250 mA 2.485 2.48 2 IL = 50 mA 1 0 -40 -20 0 20 40 60 80 100 120 2.475 2.47 -40 140 0 25 TA (°C) TEMPERATURE (°C) Figure 10. Ground Pin Current versus Ambient Temperature Figure 11. Output Voltage versus Ambient Temperature (Vin = Vout + 1V) www.onsemi.com 6 85 MC33375, NCV33375 Series 2.5 IO = 0 2.495 Vout (VOLTS) 2.49 IO = 250 mA 2.485 2.48 2.475 2.47 2.465 -40 0 25 85 TEMPERATURE (°C) Figure 12. Output Voltage versus Ambient Temperature (Vin = 12 V) 70 70 60 50 IL = 1 mA dB 30 20 20 10 10 1 10 IL = 250 mA 40 30 0 0.1 IL = 100 mA 50 40 0 0.1 100 1 10 FREQUENCY (kHz) FREQUENCY (kHz) Figure 13. Ripple Rejection Figure 14. Ripple Rejection 5 ENABLE 4.5 4 VOLTAGE (V) dB 60 IL = 10 mA 3.5 CL = 1.0 F 3 2.5 CL = 33 F 2 1.5 1 0.5 0 0 100 200 300 400 TIME (S) Figure 15. Enable Transient www.onsemi.com 7 500 100 MC33375, NCV33375 Series 1.8 V Option 2.0 1.85 ILOAD = 100 mA 1.8 VOUT, OUTPUT VOLTAGE (V) VOUT , OUTPUT VOLTAGE (V) 1.84 1.83 1.82 1.81 1.80 1.79 1.78 1.77 1.76 1.75 -40 1.6 1.4 1.2 1.0 0.8 0.6 TA = 25° C ILOAD = 0 mA 0.4 0.2 0 -20 0 20 40 60 80 100 120 1 0 3 2 TA, AMBIENT TEMPERATURE (°C) Figure 16. Output Voltage versus Temperature 140 10 120 TA = 25° C VCC = 3 V IQ ( A) Ignd , (mA) 100 6 4 80 60 40 2 TA = 25° C ILOAD = 0 mA 20 0 0 50 0 100 150 200 250 300 350 0 1 3 2 ILOAD, (mA) 5 4 6 VCC, (V) Figure 19. Quiescent Current versus Input Voltage Figure 18. Ground Current versus Load Current 80 VCC = 3 V ILOAD = 1 mA TA = 25°C COUT = 1 F 2V 70 60 PSRR (dB) 6 Figure 17. Output Voltage versus Input Voltage 12 8 5 4 VCC, (V) 50 ENABLE VOUT 40 30 20 0V 10 0 0.1 1 10 100 0 1000 5 10 15 20 25 30 35 40 f, FREQUENCY (kHz) t, TIME (s) Figure 20. PSRR versus Frequency Figure 21. Enable Response www.onsemi.com 8 45 50 MC33375, NCV33375 Series VCC = 3 V ILOAD = 1 mA to 100 mA TA = 25°C 1.82 V 1.80 V 1.78 V 100 mA 1 mA 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 t, TIME (ms) Figure 22. Load Transient Response APPLICATIONS INFORMATION ON/OFF Vout Vin MC33375−xx Cin Cout LOAD GND Figure 23. Typical Application Circuit frequencies. A 0.33 F or larger tantalum, mylar, ceramic, or other capacitor having low internal impedance at high frequencies should be chosen. The bypass capacitor should be mounted with shortest possible lead or track length directly across the regulator’s input terminals. Figure 16 shows the ESR that allows the LDO to remain stable for various load currents. The MC33375 regulators are designed with internal current limiting and thermal shutdown making them user−friendly. Figure 15 is a typical application circuit. The output capability of the regulator is in excess of 300 mA, with a typical dropout voltage of less than 260 mV. Internal protective features include current and thermal limiting. EXTERNAL CAPACITORS These regulators require only a 0.33 F (or greater) capacitance between the output and ground for stability for 1.8 V, 2.5 V, 3.0 V, and 3.3 V output voltage options. Output voltage options of 5.0 V require only 0.22 F for stability. The output capacitor must be mounted as close as possible to the MC33375. If the output capacitor must be mounted further than two centimeters away from the MC33375, then a larger value of output capacitor may be required for stability. A value of 0.68 F or larger is recommended. Most type of aluminum, tantalum, or multilayer ceramic will perform adequately. Solid tantalums or appropriate multilayer ceramic capacitors are recommended for operation below 25°C. An input bypass capacitor is recommended to improve transient response or if the regulator is connected to the supply input filter with long wire lengths, more than 4 inches. This will reduce the circuit’s sensitivity to the input line impedance at high ESR (ohm) 100 Vout = 3.0 V Cout = 1.0 F Cin = 1.0 F 10 Stable Region 1.0 0.1 0 50 100 150 200 250 300 LOAD CURRENT (mA) Figure 24. ESR for Vout = 3.0V Applications should be tested over all operating conditions to insure stability. www.onsemi.com 9 MC33375, NCV33375 Series THERMAL PROTECTION The internal current limit will typically limit current to 450 mA. If during current limit the junction exceeds 150°C, the thermal protection will protect the device also. Current limit is not a substitute for proper heatsinking. Internal thermal limiting circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 150°C, the output is disabled. There is no hysteresis built into the thermal protection. As a result the output will appear to be oscillating during thermal limit. The output will turn off until the temperature drops below the 150°C then the output turns on again. The process will repeat if the junction increases above the threshold. This will continue until the existing conditions allow the junction to operate below the temperature threshold. OUTPUT NOISE In many applications it is desirable to reduce the noise present at the output. Reducing the regulator bandwidth by increasing the size of the output capacitor will reduce the noise on the MC33375. ON/OFF PIN Thermal limit is not a substitute for proper heatsinking. 1.6 160 1.4 PD(max) for TA = 50°C 140 L 100 80 60 RJA 0 5.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1.2 2.0 oz. Copper L Minimum Size Pad 120 10 15 20 25 L, LENGTH OF COPPER (mm) 1.0 0.8 0.6 0.4 30 Figure 25. SOT−223 Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length R θ JA, THERMAL RESISTANCE, JUNCTION‐TO‐AIR (°C/W) RJA, THERMAL RESISTANCE, JUNCTION−TO−AIR (°CW) 180 PD, MAXIMUM POWER DISSIPATION (W) When this pin is pulled low, the MC33375 is off. This pin should not be left floating. The pin should be pulled high for the MC33375 to operate. 3.2 170 150 2.8 PD(max) for TA = 50°C 130 2.4 110 Graph Represents Symmetrical Layout 2.0 90 L 70 30 0 10 2.0 oz. Copper 3.0 mm L RJA 50 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ 20 30 40 50 1.6 1.2 0.8 0.4 L, LENGTH OF COPPER (mm) Figure 26. SOP−8 Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length www.onsemi.com 10 MC33375, NCV33375 Series ORDERING INFORMATION Operating Temperature Range, Tolerance Package Shipping† SOT−223 (Pb−Free) 4000 / Tape & Reel SOIC−8 (Pb−Free) 98 Units / Rail SOIC−8 (Pb−Free) 2500 / Tape & Reel MC33375ST−2.5T3G SOT−223 (Pb−Free) 4000 / Tape & Reel MC33375D−3.0G SOIC−8 (Pb−Free) 98 Units / Rail 1% Tolerance at TA = 25°C SOIC−8 (Pb−Free) 2500 / Tape & Reel 2% Tolerance at TJ from −40 to +125°C SOT−223 (Pb−Free) 4000 / Tape & Reel SOIC−8 (Pb−Free) 98 Units / Rail SOIC−8 (Pb−Free) 2500 / Tape & Reel SOT−223 (Pb−Free) 4000 / Tape & Reel SOIC−8 (Pb−Free) 98 Units / Rail SOIC−8 (Pb−Free) 2500 / Tape & Reel SOIC−8 (Pb−Free) 2500 / Tape & Reel SOT−223 (Pb−Free) 4000 / Tape & Reel Device Type MC33375ST−1.8T3G 1.8 V (Fixed Voltage) NCV33375ST1.8T3G* MC33375D−2.5G MC33375D−2.5R2G 2.5 V (Fixed Voltage) NCV33375D−2.5R2G* MC33375D−3.0R2G 3.0 V (Fixed Voltage) MC33375ST−3.0T3G MC33375D−3.3G MC33375D−3.3R2G 3.3 V (Fixed Voltage) NCV33375D−3.3R2G* MC33375ST−3.3T3G NCV33375ST3.3T3G* MC33375D−5.0G MC33375D−5.0R2G 5.0 V (Fixed Voltage) NCV33375D−5.0R2G* MC33375ST−5.0T3G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable DEVICE MARKING Device Version Marking (1st line) MC33375, NCV33375 1.8 V 37518 MC33375, NCV33375 2.5 V 37525 MC33375 3.0 V 37530 MC33375, NCV33375 3.3 V 37533 MC33375, NCV33375 5.0 V 37550 www.onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−223 (TO−261) CASE 318E−04 ISSUE R DATE 02 OCT 2018 SCALE 1:1 q q DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com SOT−223 (TO−261) CASE 318E−04 ISSUE R STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. ANODE CATHODE NC CATHODE STYLE 6: PIN 1. 2. 3. 4. RETURN INPUT OUTPUT INPUT STYLE 7: PIN 1. 2. 3. 4. ANODE 1 CATHODE ANODE 2 CATHODE STYLE 11: PIN 1. MT 1 2. MT 2 3. GATE 4. MT 2 STYLE 3: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 8: STYLE 12: PIN 1. INPUT 2. OUTPUT 3. NC 4. OUTPUT CANCELLED DATE 02 OCT 2018 STYLE 4: PIN 1. 2. 3. 4. SOURCE DRAIN GATE DRAIN STYLE 5: PIN 1. 2. 3. 4. STYLE 9: PIN 1. 2. 3. 4. INPUT GROUND LOGIC GROUND STYLE 10: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE DRAIN GATE SOURCE GATE STYLE 13: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR GENERIC MARKING DIAGRAM* AYW XXXXXG G 1 A = Assembly Location Y = Year W = Work Week XXXXX = Specific Device Code G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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