DATA SHEET
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Fixed/Adjustable
Current‐Limiting
Power‐Distribution
Switches
UDFN6
CASE 517AB
TSOP−5
CASE 483
MARKING DIAGRAMS
NCP380, NCV380
1
2
3
The NCP380 is a high side power-distribution switch designed for
applications where heavy capacitive loads and short-circuits are likely
to be encountered. The device includes an integrated 55 mW (DFN
package), P-channel MOSFET. The device limits the output current to
a desired level by switching into a constant-current regulation mode
when the output load exceeds the current-limit threshold or a short is
present. The current-limit threshold is either user adjustable between
500 mA and 2.1 A via an external resistor or internally fixed. The
power-switch rise and fall times are controlled to minimize current
ringing during switching.
An internal reverse-voltage detection comparator disables the
power-switch if the output voltage is higher than the input voltage to
protect devices on the input side of the switch.
The FLAG logic output asserts low during over current,
reverse-voltage or over temperature conditions. The switch is
controlled by a logic enable input active high or low.
Features
• 2.5 V – 5.5 V Operating Range
• 70 mW High-side MOSFET
• Current Limit:
User adjustable from 500 mA to 2.1 A
Fixed 500 mA, 1 A, 1.5 A, 2 A and 2.1 A
Under Voltage Lock-out (UVLO)
Built-in Soft-start
Thermal Protection
Soft Turn-off
Reverse Voltage Protection
Junction Temperature Range: −40°C to 125°C
Enable Active High or Low (EN or EN)
Compliance to IEC61000−4−2 (Level 4)
♦ 8.0 kV (Contact)
♦ 15 kV (Air)
UL Listed − File No. E343275 (NCP Versions Only)
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb-Free Devices
♦
•
•
•
•
•
•
•
•
•
•
•
TSOP−6
CASE 318G
♦
XXMG
G
6
5
4
UDFN6
5
XXXAYWG
G
1
TSOP−5
XXXAYWG
G
1
TSOP−6
XXX
A
M
Y
W
G
= Specific Device Code
=Assembly Location
= Date Code
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 20 of this data sheet.
Typical Applications
• Laptops
• USB Ports/Hubs
• TVs
© Semiconductor Components Industries, LLC, 2016
August, 2021 − Rev. 19
1
Publication Order Number:
NCP380/D
NCP380, NCV380
USB
DATA
USB INPUT
5V
OUT
IN
Rfault
100 kW
D+
D−
VBUS
GND
1 mF
120 mF
USB
Port
NCP380
FLAG
FLAG
EN
ILIM*
EN
Rlim
GND
*For Adjustable Version Only.
Figure 1. Typical Application Circuit
OUT 1
ILIM* 2
FLAG
PAD1
3
6 IN
OUT
1
5 GND
GND
2
FLAG
3
4 EN
5
IN
4
EN
TSOP−5
UDFN6
(Top view)
IN
1
6
OUT
GND
2
5
ILIM*
EN
3
4
FLAG
TSOP−6
*For adjustable version only, otherwise not connected.
Figure 2. Pin Connections
Table 1. PIN FUNCTION DESCRIPTION
Pin Name
Type
Description
EN
INPUT
GND
POWER
Ground connection;
IN
POWER
Power-switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as close as possible to the IC.
FLAG
OUTPUT
Active-low open-drain output, asserted during overcurrent, overtemperature or reverse-voltage conditions.
Connect a 10 kW or greater resistor pull-up, otherwise leave unconnected.
OUT
OUTPUT
Power-switch output; connect a 1 mF ceramic capacitor from OUT to GND as close as possible to the IC
is recommended. A 1 mF or greater ceramic capacitor from OUT to GND must be connected if the USB
requirement (i.e.120 mF capacitor minimum) is not met.
ILIM*
INPUT
PAD1**
THERMAL
Enable input, logic low/high (i.e. EN or EN) turns on power switch
External resistor used to set current-limit threshold; recommended 5 kW < RILIM < 250 kW.
Exposed Thermal Pad: Must be soldered to PCB Ground plane
*(For adjustable version only, otherwise not connected.
**For DFN version only.
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2
NCP380, NCV380
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN , VOUT
−7.0 to +7.0
V
VEN, VILIM, VFLAG, VIN, VOUT
−0.3 to +7.0
V
ISINK
1
mA
From IN to OUT Pins: Input/Output (Note 1)
IN, OUT, EN, ILIM, FLAG, Pins: Input/Output (Note 1)
FLAG Sink Current
ILIM Source Current
ILIM
1
mA
ESD Withstand Voltage (IEC 61000−4−2)
(Output Only, when Bypassed with 1.0 mF Capacitor Minimum)
ESD IEC
15 Air, 8 Contact
kV
Human Body Model (HBM) ESD Rating (Note 2)
ESD HBM
2,000
V
Machine Model (MM) ESD Rating (Notes 2 and 3)
ESD MM
200
V
Latch-up Protection (Note 4)
Pins IN, OUT, EN, ILIM, FLAG
LU
mA
Maximum Junction Temperature Range (Note 6)
TJ
−40 to +TSD
°C
Storage Temperature Range
TSTG
−40 to +150
°C
Moisture Sensitivity (Note 5)
MSL
Level 1
100
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. According to JEDEC standard JESD22−A108.
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115 for all pins.
3. Except EN pin, 150 V.
4. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
6. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.
Table 3. OPERATING CONDITIONS
Symbol
Parameter
VIN
Operational Power Supply
VEN
Enable Voltage
Conditions
Min
Typ
Max
Unit
2.5
−
5.5
V
0
−
5.5
TA
Ambient Temperature Range
−40
25
+85
TJ
°C
Junction Temperature Range
−40
25
+125
°C
RILIM
Resistor from ILIM to GND Pin
5.0
−
250
kW
ISINK
FLAG Sink Current
−
−
1.0
mA
mF
CIN
Decoupling Input Capacitor
COUT
Decoupling Output Capacitor
RqJA
Thermal Resistance Junction-to-Air
IOUT
PD
Maximum DC Current
Power Dissipation Rating (Note 9)
1.0
−
−
USB Port per Hub
120
−
−
mF
UDFN−6 Package (Notes 7 and 8)
−
120
−
°C/W
TSOP−5 Package (Notes 7 and 8)
−
305
−
°C/W
TSOP−6 Package (Notes 7 and 8)
−
280
−
°C/W
UDFN−6 Package
−
−
2.1
A
TSOP−5, TSOP−6 Package
−
−
1.0
A
UDFN−6 Package
−
830
−
mW
TSOP−5 Package
−
325
−
mW
TSOP−6 Package
−
350
−
mW
UDFN−6 Package
−
325
−
mW
TSOP−5 Package
−
130
−
mW
TSOP−6 Package
−
145
−
mW
TA v 25°C
TA = 85°C
7. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.
8. The RqJA is dependent of the PCB heat dissipation. Board used to drive this data was a 2” × 2” NCP380EVB board. It is a 2 layers board
with 2-once copper traces on top and bottom of the board. Exposed pad is connected to ground plane for UDFN−6 version only.
9. The maximum power dissipation (PD) is given by the following formula:
T JMAX * T A
PD +
R qJA
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NCP380, NCV380
Table 4. ELECTRICAL CHARACTERISTICS
(Min & Max Limits apply for TA between −40°C to +85°C and TJ up to +125°C for VIN between 2.5 V to 5.5 V (Unless otherwise noted).
Typical values are referenced to TA = +25°C and VIN = 5 V.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
mW
POWER SWITCH
RDS(on)
Static Drain-source On-state
Resistance
DFN Package
TSOP Package
TR
Output Rise Time
TF
Output Fall Time
VIN = 5 V
–40°C < TJ < 125°C
−
55
75
2.5 V < VIN < 5.5 V
–40°C < TJ < 125°C
−
−
110
VIN = 5 V
–40°C < TJ < 125°C
−
70
95
2.5 V < VIN < 5.5 V
–40°C < TJ < 125°C
−
−
135
VIN = 5 V
CLOAD = 1 mF,
RLOAD = 100 W (Note 10)
0.3
1.0
1.5
VIN = 2.5 V
0.2
0.65
1.0
VIN = 5 V
0.1
−
0.5
VIN = 2.5 V
0.1
−
0.5
1.2
−
−
mW
ms
ENABLE INPUT EN OR EN
VIH
High-level Input Voltage
V
VIL
Low-level Input Voltage
−
−
0.4
V
IEN
Input Current
VEN = 0 V, VEN = 5 V
−0.5
−
0.5
mA
TON
Turn On Time
CLOAD = 1 mF, RLOAD = 100 W (Note 11)
2.0
3.0
4.0
ms
TOFF
Turn Off Time
1.0
−
3.0
ms
RILIM = 20 kW (Note 11)
1.02
1.20
1.38
A
RILIM = 40 kW
(Notes 11 and 13)
0.595
0.700
0.805
Fixed 0.5 A (Note 12)
0.5
0.58
0.65
Fixed 1.0 A (Note 12)
1.0
1.15
1.3
Fixed 1.5 A (Note 12)
1.5
1.75
1.9
Fixed 2.0 A (Note 12)
2.0
2.25
2.5
Fixed 2.1 A (Note 12)
2.1
2.25
2.5
CURRENT LIMIT
IOCP
Current-limit Threshold
(Maximum DC Output Current
IOUT Delivered to Load)
VIN = 5 V
VIN = 5 V
A
TDET
Response Time to Short Circuit
−
2.0
−
ms
TREG
Regulation Time
1.8
3.0
4.0
ms
TOCP
Overcurrent Protection Time
14
20
26
ms
−
100
−
mV
4.0
6.0
9.0
ms
7.0
10
15
ms
REVERSE-VOLTAGE PROTECTION
VREV
Reverse-voltage Comparator
Trip Point (VOUT – VIN)
TREV
Time from Reverse-voltage
Condition to MOSFET Switch Off
& FLAG Low
TRREV
Re-arming Time
VIN = 5 V
UNDERVOLTAGE LOCKOUT
VUVLO
IN Pin Low-level Input Voltage
VIN Rising
2.0
2.3
2.4
V
VHYST
IN Pin Hysteresis
TJ = 25°C
25
−
60
mV
TRUVLO
Re-arming Time
7.0
10
15
ms
−
1.0
2.1
mA
−
−
−
−
−
−
90
80
70
−
−
1.0
SUPPLY CURRENT
IINOFF
Low-level Output Supply Current
IINON
High-level Output Supply
Current
IREV
Reverse Leakage Current
VIN = 5 V, No Load on OUT, Device OFF
VEN = 0 V or VEN = 5 V
VIN = 5 V, Device Enable
2 A and 2.1 A Versions
1 A and 1.5 A Current Versions
0.5 A Current Version
VOUT = 5 V, VIN = 0 V
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TJ = 25°C
mA
mA
NCP380, NCV380
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(Min & Max Limits apply for TA between −40°C to +85°C and TJ up to +125°C for VIN between 2.5 V to 5.5 V (Unless otherwise noted).
Typical values are referenced to TA = +25°C and VIN = 5 V.)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
mV
FLAG PIN
FLAG Output Low Voltage
IFLAG = 1 mA
400
ILEAK
Off-state Leakage
VFLAG = 5 V
1.0
mA
TFLG
FLAG Deglitch
FLAG De-assertion Time due to Overcurrent or
Reverse Voltage Condition
4.0
6.0
9.0
ms
TFOCP
FLAG Deglitch
FLAG Assertion due to Overcurrent
6.0
8.0
12
ms
VOL
THERMAL SHUTDOWN
TSD
Thermal Shutdown Threshold
140
°C
TSDOCP
Thermal Regulation Threshold
125
°C
TRSD
Thermal Shutdown Rearming
Threshold
115
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground, See Figure 3.
11. Adjustable current version, RILIM tolerance ±1%.
12. Fixed current version.
13. Not production test, guaranteed by characterization.
VIN
IN
OUT
1 mF
CLOAD
RLOAD
NCP380
GND
Figure 3. Test Configuration
50%
VEN
TR
TF
VEN
TOFF
TON
VOUT
VOUT
90%
10%
90%
10%
Figure 4. Voltage Waveform
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5
10%
NCP380, NCV380
BLOCK DIAGRAM
Blocking Control
IN
ILIM*
OUT
Current
Limiter
Vref
TSD
Gate Driver
UVLO
Osc
GND
Flag
/FLAG
EN
EN Block
Control Logic and Timer
*For adjustable version only, otherwise not connected.
Figure 5. Block Diagram
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NCP380, NCV380
Ton + TR
Figure 6. Ton Delay and Trise Time
Toff + Tfall
Figure 7. Toff Delay and Tfall
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NCP380, NCV380
Figure 8. Turn On a Short
TSD
Warning
Treg
TOCP
Figure 9. 2 W Short on Output. Complete Regulation Sequence
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NCP380, NCV380
TFOCP
TSD Warning
VIN
VOUT
IIN
/FLAG
Figure 10. OCP Regulation and TSD Warning Event
TOCP
Treg
Figure 11. Timer Regulation Sequence During 2 W Overload
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NCP380, NCV380
Figure 12. Direct Short on OUT Pin
Figure 13. From Timer Regulation to Load Removal Sequence
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NCP380, NCV380
TFOCP
VOUT
IOUT
/FLAG
Figure 14. From No Load to Direct Short Circuit
VREV
VOUT
VIN
TFREV
/FLAG
Figure 15. Reverse Voltage Detection
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NCP380, NCV380
T RREV
Figure 16. Reverse Voltage Removal
2.4
2.38
2.36
UVLO (V)
2.34
2.32
2.3
2.28
2.26
2.24
UVLO vs. Temperature
2.22
UVLO − hysteresis vs.
Temperature
2.2
−50
0
50
100
150
Temperature (°C)
Figure 17. Undervoltage Threshold (Falling) and Hysteresis
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NCP380, NCV380
Low−Level Output Supply Current vs Vin
−40°C
25°C
85°C
125°C
2.0
1.8
1.6
IINOFF (mA)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.4
2.9
3.4
3.9
4.4
4.9
5.4
Vin(V)
Figure 18. Standby Current vs Vin
High−Level Output Supply Current vs Vin
−40°C
25°C
85°C
125°C
100
90
80
IINON (mA)
70
60
50
40
30
20
10
0
2.4
2.9
3.4
3.9
4.4
Vin(V)
Figure 19. Quiescent Current vs Vin
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13
4.9
5.4
NCP380, NCV380
TSOP Package
100
95
RDS(on) vs. Temperature
90
85
75
70
65
60
55
50
45
40
−50 −40 −30 −20 −10
0
10
20
30
40
50
60
70
80
90
100 110 120 130 140
Temperature (°C)
Figure 20. RDS(on) vs Temperature, TSOP Package
mDFN Package
100
95
90
RDS(on) vs. Temperature
85
RDS(on) (mW)
RDS(on) (mW)
80
80
75
70
65
60
55
50
45
40
−50 −40 −30 −20 −10
0
10
20
30
40
50
60
70
80
90 100 110 120 130 140
Temperature (°C)
Figure 21. RDS(on) vs Temperature, mDFN Package
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NCP380, NCV380
FUNCTIONAL DESCRIPTION
Overview
device enters in thermal shutdown (MOSFET is
turned-off).
The NCP380 is a high side P channel MOSFET power
distribution switch designed to protect the input supply
voltage in case of heavy capacitive loads, short circuit or
over current. In addition, the high side MOSFET is turned
off during under voltage, thermal shutdown or reverse
voltage condition. Adjustable version allows the user to
program the current limit threshold using an external
resistor. Thanks to the soft start circuitry, NCP380 is able to
limit large current and voltage surges.
VOUT
Thermal
Regulation
Threshold
Timer
Regulation
Mode
IOUT
IOCP
Overcurrent Protection
NCP380 switches into a constant current regulation mode
when the output current is above the IOCP threshold.
Depending on the load, the output voltage is decreased
accordingly.
• In case of hot plug with heavy capacitive load, the
output voltage is brought down to the capacitor voltage.
The NCP380 will limit the current to the IOCP threshold
value until the charge of the capacitor is completed.
TOCP
Figure 24. Short circuit
Then, the device enters in timer regulation mode, described
in 2 phases:
• Off-phase: Power MOSFET is off during TOCP to allow
the die temperature to drop.
• On-phase: regulation current mode during TREG. The
current is regulated to the IOCP level.
VOUT
Drop due to
Capacitor Charge
The timer regulation mode allows the device to handle
high thermal dissipation (in case of short circuit for
example) within temperature operating condition.
NCP380 stays in on-phase/off-phase loop until the over
current condition is removed or enable pin is toggled.
IOUT
IOCP
Remark: Other regulation modes can be available for
different applications. Please contact our onsemi
representative for availability.
Figure 22. Heavy capacitive load
• In case of overload, the current is limited to the IOCP
FLAG Indicator
value and the voltage value is reduced according to the
load by the following relation:
V OUT + R LOAD
I OCP
TREG
The FLAG pin is an open-drain MOSFET asserted low
during over current, reverse-voltage or over temperature
conditions. When an over current or a reverse voltage fault
is detected on the power path, FLAG pin is asserted low at
the end of the associate deglitch time (see electrical
characteristics). Thanks to this feature, the FLAG pin is not
tied low during the charge of a heavy capacitive load or a
voltage transient on output. Deglitch time is TFOCP for over
current fault and TREV for reverse voltage. The FLAG pin
remains low until the fault is removed. Then, the FLAG pin
goes high at the end of TFGL.
(eq. 1)
VOUT
IOCP × RLOAD
IOUT
IOCP
Undervoltage Lock-out
Thanks to a built-in under voltage lockout (UVLO)
circuitry, the output remains disconnected from input until
VIN voltage is below VUVLO. When VIN voltage is above
VUVLO, the system try to reconnect the output after
a rearming time. TRUVLO. This circuit has a VHYST
hysteresis witch provides noise immunity to transient.
Figure 23. Overload
• In case of short circuit or huge load, the current is
limited to the IOCP value within TDET time until the
short condition is removed. If the output remains
shorted or tied to a very low voltage, the junction
temperature of the chip exceeds TSDOCP value and the
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NCP380, NCV380
Thermal Sense
well established and stablized prior to enabling the IC. If no
separate EN signal is available, a 10 kW/100 nF RC network
can be added between VIN and EN to delay the EN signal.
A logic low on EN or high on EN turns-on the device. A logic
high on EN or low on EN turns off device and reduces the
current consumption down to IINOFF.
Thermal shutdown turns off the power MOSFET if the die
temperature exceeds TSD. A Hysteresis prevents the part
from turning on until the die temperature cools at TRSD.
Reverse Voltage Protection
When the output voltage exceeds the input voltage by
VREV voltage during TREV, the reverse voltage circuitry
disconnects the output in order to protect the power supply.
The same time TREV is needed to turn on again the power
MOS plus a rearming time TRREV.
Blocking Control
The blocking control circuitry switches the bulk of the
power MOS. When the part is off, the body diode limits the
leakage current IREV from OUT to IN. In this mode, anode
of the body diode is connected to IN pin and cathode is
connected to OUT pin. In operating condition, anode of the
body diode is connected to OUT pin and cathode is
connected to IN pin preventing the discharge of the power
supply.
Enable Input
Enable pin must be driven by a logic signal (CMOS or
TTL compatible) or connected to the GND. VIN and EN
should not be connected together directly. VIN should be
APPLICATION INFORMATION
Power Dissipation
Adjustable Current-Limit Programming
(for adjustable version only)
The junction temperature of the device depends on
different contributing factors such as board layout, ambient
temperature, device environment, etc... Yet, the main
contributor in terms of junction temperature is the power
dissipation of the power MOSFET. Assuming this, the
power dissipation and the junction temperature in normal
mode can be calculated with the following equations:
R D + R DS(on)
Where:
PD
RDS(on)
IOUT
2
(eq. 2)
= Power dissipation (W)
= Power MOSFET on resistance (W)
= Output current (A)
TJ + PD
Where:
TJ
RqJA
TA
ǒIOUTǓ
The NCP380xMUAJAA and NCP380xSNAJAA,
respectively mDFN and TSOP6 packages, are proposed to
have current limit flexibility for end Customer. Indeed, Ilim
pin is available to connect pull down resistor to ground,
which participate to the current threshold adjustment. It’s
strongly recommended to use 0.1 or 1% resistor tolerance to
keep the over current accuracy.
For this resistance selection, Customer should define first
of all, the USB current to sustain, without the device enters
in the protection sequence. Main rule is to select this pull
down resistor in order to make sure min current limit is
above the USB current to provide continuously to the
upstream accessory.
Following, the main table selection contains the USB
current port for the accessory, the standard resistor selection
and typical/max over current threshold.
R qJA ) T A
(eq. 3)
= Junction temperature (°C)
= Package thermal resistance (°C/W)
= Ambient temperature (°C)
Power dissipation in regulation mode can be calculated by
taking into account the drop VIN−VOUT link to the load by
the following relation:
P D + ǒV IN * R LOAD
Where:
PD
VIN
RLOAD
IOCP
I OCPǓ
I OCP
(eq. 4)
= Power dissipation (W)
= Input Voltage (V)
= Load Resistance (W)
= Output regulated current (A)
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NCP380, NCV380
Table 5. RESISTOR SELECTION FOR ADJUSTABLE CURRENT LIMIT VERSION
Min Current
Limit Value
(A)
Theoric Resistor Value
(kW)
Selected Resistor Value
(kW)
1% or 0.1%
Typical OCP Target Value
(A)
Maximum
Current Value
(A)
0.5
44.2
44.2
0.59
0.67
0.6
37.5
37.4
0.71
0.81
0.7
32.2
31.6
0.825
0.95
0.8
27.7
27.4
0.94
1.08
0.9
24.0
23.7
1.06
1.22
1.0
21.0
21
1.18
1.35
1.1
18.5
18.2
1.3
1.49
1.2
16.6
16.5
1.41
1.62
1.3
14.6
14.3
1.53
1.76
1.4
13.0
13
1.65
1.9
1.5
11.4
11.3
1.78
2.05
1.6
10.4
10.2
1.88
2.17
1.7
9.2
9.09
2.01
2.31
1.8
8.3
8.25
2.12
2.438
1.9
7.4
7.32
2.23
2.56
2.0
6.5
6.49
2.36
2.7
2.1
5.6
5.49
2.48
2.85
The “Min current limit Value” column, represents the DC
current to provide to the accessory without over current
activation.
ILIM 5 ) 45.256
ILIM 4 * 155.25
ILIM 3 ) 274.39
ILIM 2 * 267.6
ILIM ) 134.21
Rlim Versus OCP Average
RLIM (kW)
Rlim + −5.2959
Second column is the theoretical resistor value obtained
with following formula to achieve typical current target:
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
RLIM vs. OCP Average
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
Current Limit (A)
Figure 25. RLIM Curve vs. Current Limit
www.onsemi.com
17
2.4
2.6
2.8
(eq. 5)
NCP380, NCV380
When the resistor is choosing to fit with the Customer
application, the limits of the over current threshold can be
calculated with the following formula:
IOCP min + 1.6915129 * 0.0330328
Rlim ) 0.0011207(Rlim * 22.375) 2 * 0.0000451
(Rlim * 22.375) 3 )
(Rlim * 22.375) 4
) 0.0000009
IOCP max + 2.2885175 * 0.0446914
Rlim ) 0.0015163(Rlim * 22.375) 2 * 0.000061
(Rlim * 22.375) 3 )
(Rlim * 22.375) 4
) 0.0000012
Rlim ) 0.0013185(Rlim * 22.375) 2 * 0.0000531
IOCPtyp + 1.9900152 * 0.0388621
(Rlim * 22.375) 3 )
(Rlim * 22.375) 4
) 0.0000011
(eq. 6)
(eq. 7)
(eq. 8)
The minimum, typical and maximum current curves are
described in the following graph:
3.0
2.8
IOCP min vs. RLIM
2.6
IOCP vs. RLIM
2.4
IOCP max vs. RLIM
2.2
2.0
ILIM (A)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35 37
39
41
43 45
47
RLIM (kW)
Figure 26. Current Threshold vs. Rlim Resistor
PCB Recommendations
That is recommended to respect 6 kW−47 kW resistor
range for two reasons.
For the low resistor values, the current limit is pushed up
to high current level. Due to internal power dissipation
capability, a maximum of 2.4 A typical can be set for the
mDFN package if thermal consideration are respected. For
the TSOP6 version 1.2 A is the maximum recommended
value because the part could enter in thermal shutdown
mode before constant current regulation mode.
In the other side, if we want to keep 15% of accuracy, high
resistor values can be used up to 50 kW. With higher value,
the current threshold is lower than 500 mA, so in this case
degraded accuracy can be observed.
The NCP380 integrates a PMOS FET rated up to 2 A, and
the PCB design rules must be respected to properly evacuate
the heat out of the silicon. The UDFN6 PAD1 must be
connected to ground plane to increase the heat transfer if
necessary. This pad must be connected to ground plane. By
increasing PCB area, the RqJA of the package can be
decreased, allowing higher power dissipation.
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18
www.onsemi.com
19
Figure 27. USB Host Typical Application
USB Port
GND
D−
D+
VBUS
OUT
2
3
USB
Transceiver
GND
1
IN
LDO 3.3 V
10 mF
GND
D−
10
GND
3
2
1
EN
DATA_OUT[x:0]
DATA_IN[x:0]
GND
CRTL_OUT[x:0]
SYS
CRTL_IN[x:0]
VCC
4
5
6
USB Host
Controller
/FLAG
ILIM
OUT
NCP380
GND
IN
STATUS
EN
GPM21BR61C106KE15L
VCC
12
VBUS(sense) CRTL[x:0]
11
DATA[x:0]
D+
1
4.7 mF
Upstream USB Port
3
4
2
5
IN
Power Supply
10
Downstream USB Port
5
12
CRTL[x:0] VBUS(sense)
11
2
DATA[x:0]
D+
3
D−
4
GND
GND
USB
Transceiver 1
VCC
SYSTEM
GPM31CR60J107ME39L
100 mF
USB Port
GND
D−
D+
VBUS
NCP380, NCV380
NCP380, NCV380
Table 6. ORDERING INFORMATION
Device
Marking
Active
Enable
Level
Over
Current
Limit
Evaluation Board
UL
Listed
CB
Scheme
NCP380LSNAJAAT1G
AAC
Adj.
NCP380LSNAJAGEVB
Y
Y
NCP380LSN05AAT1G
AC5
0.5 A
NCP380LSN05AGEVB
Y
Y
NCP380LSN10AAT1G
AC6
1.0 A
NCP380LSN10AGEVB
Y
Y
Low
NCP380LMUAJAATBG
AA
Adj.
NCP380LMUAJAGEVB
Y
Y
NCV380LMUAJAATBG*
AN
Adj.
NCP380LMUAJAGEVB
N
N
NCP380LMU05AATBG
AE
0.5 A
NCP380LMU05AGEVB
Y
Y
NCP380HSNAJAAT1G
AAD
Adj.
NCP380HSNAJAGEVB
Y
Y
NCP380HSN05AAT1G
AC7
0.5 A
NCP380HSN05AGEVB
Y
Y
NCP380HSN10AAT1G
ADA
1.0 A
NCP380HSN10AGEVB
Y
Y
NCP380HMUAJAATBG
AC
Adj.
NCP380HMUAJAGEVB
Y
Y
NCV380HMUAJAATBG*
AP
Adj.
NCP380HMUAJAGEVB
N
N
NCP380HMU05AATBG
AH
0.5 A
NCP380HMU05AGEVB
Y
Y
NCP380HMU10AATBG
AJ
1.0 A
NCP380HMU10AGEVB
Y
Y
NCP380HMU15AATBG
AK
1.5 A
NCP380HMU15AGEVB
Y
Y
NCP380HMU20AATBG
AM
2.0 A
NCP380HMU20AGEVB
Y
Y
NCP380HMU21AATBG
AU
2.1 A
NCP380HMU21AGEVB
Y
Y
High
Package
Shipping†
TSOP−6
(Pb−Free)
TSOP−5
(Pb−Free)
UDFN6
(Pb−Free)
TSOP−6
(Pb−Free)
TSOP−5
(Pb−Free)
3,000
Tape / Reel
UDFN6
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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20
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
1
SCALE 2:1
D
H
ÉÉ
ÉÉ
6
E1
1
NOTE 5
5
2
L2
4
GAUGE
PLANE
E
3
L
b
SEATING
PLANE
C
DETAIL Z
e
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
c
A
0.05
M
DATE 12 JUN 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
A1
DETAIL Z
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
10°
−
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2
STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in
6. V out
STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTER
STYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GND
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
STYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/O
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE
STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
XXXAYWG
G
1
6X
3.20
XXX
A
Y
W
G
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14888C
TSOP−6
1
IC
0.95
XXX MG
G
= Specific Device Code
=Assembly Location
= Year
= Work Week
= Pb−Free Package
STANDARD
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
*This information is generic. Please refer to device data sheet
for actual part marking. Pb−Free indicator, “G” or microdot “
G”, may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN6 2x2, 0.65P
CASE 517AB
ISSUE C
DATE 10 APR 2013
SCALE 4:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE
TERMINALS.
5. TIE BARS MAY BE VISIBLE IN THIS VIEW AND ARE CONNECTED TO
THE THERMAL PAD.
A B
D
NOTE 5
PIN ONE
REFERENCE
0.10 C
0.10 C
ÍÍ
ÍÍ
ÍÍ
E
END VIEW
TOP VIEW
ÉÉÉ
ÉÉÉ
ÇÇÇ
A3
DETAIL B
0.10 C
EXPOSED Cu
A
6X
0.08 C
A1
NOTE 4
C
SIDE VIEW
DETAIL A
D2
1
SEATING
PLANE
L
3
4
6X
L
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
b
e
BOTTOM VIEW
0.10
M
C A B
0.05
M
C
A1
GENERIC
MARKING DIAGRAM*
ALTERNATE
CONSTRUCTIONS
L1
6
A3
DETAIL B
L
E2
ÉÉ
ÉÉ
ÇÇ
MOLD CMPD
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.25
0.35
2.00 BSC
1.50
1.70
2.00 BSC
0.80
1.00
0.65 BSC
0.25
0.35
--0.15
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
XXMG
G
XX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
RECOMMENDED
SOLDERING FOOTPRINT*
PACKAGE
OUTLINE
1.70
6X
0.47
2.30
0.95
1
0.65
PITCH
6X
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON22162D
UDFN6 2X2, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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