High Performance
Current Mode Controllers
NCV3843BV
The NCV3843BV is a high performance fixed frequency current
mode controller. They are specifically designed for Off−Line and
DC−DC converter applications offering the designer a cost−effective
solution with minimal external components. These integrated circuits
feature a trimmed oscillator for precise duty cycle control, a
temperature compensated reference, high gain error amplifier, current
sensing comparator, and a high current totem pole output ideally
suited for driving a power MOSFET.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, programmable output deadtime, and a latch for single
pulse metering.
These devices are available in a surface mount (SOIC−8) plastic
package as well as the 14−pin plastic surface mount (SOIC−14). The
SOIC−14 package has separate power and ground pins for the totem
pole output stage.
The NCV3843BV is tailored for lower voltage applications having
UVLO thresholds of 8.5 V (on) and 7.6 V (off).
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SOIC−14
D SUFFIX
CASE 751A
14
1
SOIC−8
D1 SUFFIX
CASE 751
8
1
PIN CONNECTIONS
Features
•
•
•
•
•
•
•
•
•
•
Compensation
Voltage Feedback
Current Sense
RT/CT
Trimmed Oscillator for Precise Frequency Control
Oscillator Frequency Guaranteed at 250 kHz
Current Mode Operation to 500 kHz
Automatic Feed Forward Compensation
Latching PWM for Cycle−By−Cycle Current Limiting
Internally Trimmed Reference with Undervoltage Lockout
High Current Totem Pole Output
Undervoltage Lockout with Hysteresis
Low Startup and Operating Current
These are Pb−Free Devices
VCC
Vref
5.0V
Reference
8(14)
R
R
RT/CT
Voltage
Feedback
Input
2(3)
Output
Compensation
1(1)
Compensation
NC
Voltage Feedback
NC
Current Sense
NC
RT/CT
7
3
6
4
5
Vref
VCC
Output
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
Vref
NC
VCC
VC
Output
GND
Power Ground
(Top View)
VCC
Undervoltage
Lockout
ORDERING INFORMATION
VC
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
7(11)
Output
Oscillator
4(7)
8
2
(Top View)
7(12)
Vref
Undervoltage
Lockout
1
6(10)
Power
Ground
5(8)
Latching
PWM
+
-
Error
Amplifier
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 15 of this data sheet.
Current
Sense
3(5) Input
GND
5(9)
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2010
February, 2020 − Rev. 3
1
Publication Order Number:
NCV3843BV/D
NCV3843BV
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec)
VCC, VC
30
V
Total Power Supply and Zener Current
(ICC + IZ)
30
mA
IO
1.0
A
Output Current, Source or Sink
Output Energy (Capacitive Load per Cycle)
W
5.0
mJ
Current Sense and Voltage Feedback Inputs
Vin
− 0.3 to + 5.5
V
Error Amp Output Sink Current
IO
10
mA
PD
RqJA
862
145
mW
°C/W
PD
RqJA
702
178
mW
°C/W
TJ
+150
°C
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, SOIC−14 Case 751A
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction−to−Air
D1 Suffix, Plastic Package, SOIC−8 Case 751
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction−to−Air
Operating Junction Temperature
Operating Ambient Temperature
TA
−40 to +125
°C
Storage Temperature Range
Tstg
− 65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 4000 V per JEDEC Standard JESD22-A114B
Machine Model Method 200 V per JEDEC Standard JESD22-A115-A
2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78
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2
NCV3843BV
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 3], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 4], unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C)
Vref
4.9
5.0
5.1
V
Line Regulation (VCC = 12 V to 25 V)
Regline
−
2.0
20
mV
Load Regulation (IO = 1.0 mA to 20 mA)
Regload
−
3.0
25
mV
mV/°C
Temperature Stability
TS
−
0.2
−
Total Output Variation over Line, Load, and Temperature
Vref
4.82
−
5.18
V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C)
Vn
−
50
−
mV
Long Term Stability (TA = 125°C for 1000 Hours)
Output Short Circuit Current
S
−
5.0
−
mV
ISC
− 30
− 85
−180
mA
49
48
225
52
−
250
55
56
275
OSCILLATOR SECTION
fOSC
Frequency
TJ = 25°C
TA = Tlow to Thigh
TJ = 25°C (RT = 6.2 k, CT = 1.0 nF)
kHz
Frequency Change with Voltage (VCC = 12 V to 25 V)
DfOSC/DV
−
0.2
1.0
%
Frequency Change with Temperature, TA = Tlow to Thigh
DfOSC/DT
−
0.5
−
%
Oscillator Voltage Swing (Peak−to−Peak)
VOSC
−
1.6
−
Discharge Current (VOSC = 2.0 V)
TJ = 25°C, TA = Tlow to Thigh
Idischg
7.8
7.2
8.3
−
8.8
8.8
V
mA
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V)
Input Bias Current (VFB = 5.0 V)
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V)
Unity Gain Bandwidth (TJ = 25°C)
VFB
2.42
2.5
2.58
V
IIB
−
− 0.1
− 2.0
mA
AVOL
65
90
−
dB
BW
0.7
1.0
−
MHz
PSRR
60
70
−
dB
ISink
ISource
2.0
− 0.5
12
−1.0
−
−
VOH
VOL
5.0
−
6.2
0.8
−
1.2
Current Sense Input Voltage Gain (Notes 5 and 6)
AV
2.85
3.0
3.25
V/V
Maximum Current Sense Input Threshold (Note 5)
Vth
0.85
1.0
1.1
V
PSRR
−
70
−
dB
IIB
−
− 2.0
−10
mA
tPLH(In/Out)
−
150
300
ns
Power Supply Rejection Ratio (VCC = 12 V to 25 V)
Output Current
Sink (VO = 1.1 V, VFB = 2.7 V)
Source (VO = 5.0 V, VFB = 2.3 V)
Output Voltage Swing
High State (RL = 15 k to ground, VFB = 2.3 V)
Low State (RL = 15 k to Vref, VFB = 2.7 V)
mA
V
CURRENT SENSE SECTION
Power Supply Rejection Ratio (VCC = 12 V to 25 V, Note 5)
Input Bias Current
Propagation Delay (Current Sense Input to Output)
3. Adjust VCC above the Startup threshold before setting to 15 V.
4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
NCV3843BV: Tlow = −40°C, Thigh = +125°C. Guaranteed by design.
NCV prefix is for automotive and other applications requiring site and change control.
5. This parameter is measured at the latch trip point with VFB = 0 V.
6. Comparator gain is defined as: AV DV Output Compensation
DV Current Sense Input
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3
NCV3843BV
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 7], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 8], unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
VOL
−
−
12.9
12
0.1
1.6
13.5
13.4
0.4
2.3
−
−
Unit
OUTPUT SECTION
Output Voltage
Low State (ISink = 20 mA)
(ISink = 200 mA)
High State (ISource = 20 mA)
(ISource = 200 mA)
VOH
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA)
V
VOL(UVLO)
−
0.1
1.1
V
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C)
tr
−
50
150
ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C)
tf
−
50
150
ns
Vth
7.8
8.4
9.0
V
VCC(min)
7.0
7.6
8.2
V
DC(max)
DC(min)
93
−
96
−
−
0
−
−
0.3
12
0.5
17
30
36
−
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold (VCC)
Minimum Operating Voltage After Turn−On (VCC)
PWM SECTION
Duty Cycle
Maximum
Minimum
%
TOTAL DEVICE
Power Supply Current (Note 7)
Startup (VCC 6.5 V)
Startup (VCC 14 V)
ICC + IC
Power Supply Zener Voltage (ICC = 25 mA)
VZ
mA
V
7. Adjust VCC above the Startup threshold before setting to 15 V.
8. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
NCV3843BV: Tlow = −40°C, Thigh = +125°C. Guaranteed by design.
NCV prefix is for automotive and other applications requiring site and change control.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCV3843BV
80
100
% DT, PERCENT OUTPUT DEADTIME
20
8.0
5.0
2.0
0.8
10 k
VCC = 15 V
TA = 25°C
20 k
50 k
100 k
200 k
500 k
fOSC, OSCILLATOR FREQUENCY (kHz)
F sw [
1. CT = 10 nF
50 2. CT = 5.0 nF
3. CT = 2.0 nF
4. CT = 1.0 nF
20 5. CT = 500 pF
6. CT = 200 pF
10 7. CT = 100 pF
7
20 k
50 k
100 k
200 k
500 k
fOSC, OSCILLATOR FREQUENCY (kHz)
1.0 M
1
C t ǒ0.588 R t ) 217Ǔ
Figure 3. Output Deadtime
versus Oscillator Frequency
D max , MAXIMUM OUTPUT DUTY CYCLE (%)
9.0
I dischg , DISCHARGE CURRENT (mA)
6
VCC = 15 V
TA = 25°C
2.0
Figure 2. Timing Resistor
versus Oscillator Frequency
VCC = 15 V
VOSC = 2.0 V
8.5
8.0
7.5
-25
1
5
C t in farads and R t in ohms
7.0
-55
3
2
5.0
1.0
10 k
1.0 M
4
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
100
90
80
70
60
40
0.8
1.0
2.0
3.0
4.0
RT, TIMING RESISTOR (kW)
VCC = 15 V
CT = 3.3 nF
TA = 25°C
5.0 6.0 7.0 8.0
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor
VCC = 15 V
AV = -1.0
TA = 25°C
VCC = 15 V
AV = -1.0
TA = 25°C
3.0 V
20 mV/DIV
2.50 V
Idischg = 8.8 mA
50
Figure 4. Oscillator Discharge Current
versus Temperature
2.55 V
Idischg = 7.5 mA
20 mV/DIV
R T, TIMING RESISTOR (k Ω)
50
2.5 V
2.45 V
2.0 V
0.5 ms/DIV
1.0 ms/DIV
Figure 6. Error Amp Small Signal
Transient Response
Figure 7. Error Amp Large Signal
Transient Response
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5
Gain
60
0
30
60
40
90
Phase
20
120
0
150
100
1.0 k
10 k
100 k
180
10 M
1.0 M
0.8
TA = 25°C
0.6
TA = 125°C
0.4
TA = -55°C
0.2
0
0
Figure 8. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 9. Current Sense Input Threshold
versus Error Amp Output Voltage
ÄÄÄÄ
-4.0
-8.0
-12
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
TA = 125°C
-16
-20
ÄÄÄ
ÄÄÄ
TA = -55°C
TA = 25°C
20
40
60
80
100
120
8.0
ÄÄÄ
ÄÄÄ
110
VCC = 15 V
RL ≤ 0.1 W
90
70
50
-55
-25
0
25
50
75
100
Iref, REFERENCE SOURCE CURRENT (mA)
TA, AMBIENT TEMPERATURE (°C)
Figure 10. Reference Voltage Change
versus Source Current
Figure 11. Reference Short Circuit Current
versus Temperature
Δ V O , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
Δ V O , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
VCC = 15 V
1.0
2.0
4.0
6.0
VO, ERROR AMP OUTPUT VOLTAGE (V)
VCC = 15 V
0
1.2
f, FREQUENCY (Hz)
0
-24
Vth, CURRENT SENSE INPUT THRESHOLD (V)
80
-20
10
Δ Vref , REFERENCE VOLTAGE CHANGE (mV)
VCC = 15 V
VO = 2.0 V to 4.0 V
RL = 100 K
TA = 25°C
φ, EXCESS PHASE (DEGREES)
100
I SC , REFERENCE SHORT CIRCUIT CURRENT (mA)
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
NCV3843BV
VCC = 15 V
IO = 1.0 mA to 20 mA
TA = 25°C
2.0 ms/DIV
Figure 12. Reference Load Regulation
VCC = 12 V to 25
TA = 25°C
2.0 ms/DIV
Figure 13. Reference Line Regulation
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6
125
0
-1.0
-2.0
Source Saturation
(Load to Ground)
VCC = 15 V
80 ms Pulsed Load
120 Hz Rate
VCC = 15 V
CL = 1.0 nF
TA = 25°C
90%
TA = -55°C
3.0
TA = -55°C
2.0
TA = 25°C
0
Sink Saturation
(Load to VCC)
GND
400
600
200
10%
800
IO, OUTPUT LOAD CURRENT (mA)
50 ns/DIV
Figure 14. Output Saturation Voltage
versus Load Current
Figure 15. Output Waveform
25
VCC = 30 V
CL = 15 pF
TA = 25°C
100 mA/DIV
I CC , SUPPLY CURRENT
20 V/DIV
I CC , SUPPLY CURRENT (mA)
1.0
0
ÄÄÄÄÄÄÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄÄÄÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄ
ÄÄÄ
ÄÄÄÄ ÄÄÄ
ÄÄÄÄ ÄÄ
VCC
TA = 25°C
V O , OUTPUT VOLTAGE
Vsat, OUTPUT SATURATION VOLTAGE (V)
NCV3843BV
20
15
10
RT = 10 k
CT = 3.3 nF
VFB = 0 V
ISense = 0 V
TA = 25°C
5
0
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
0
10
100 ns/DIV
20
30
40
VCC, SUPPLY VOLTAGE (V)
Figure 16. Output Cross Conduction
Figure 17. Supply Current versus Supply Voltage
PIN FUNCTION DESCRIPTION
8−Pin
14−Pin
Function
1
1
Compensation
2
3
Voltage
Feedback
3
5
Current
Sense
4
7
RT/CT
The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor
RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible.
GND
This pin is the combined control circuitry and power ground.
6
10
Output
7
12
VCC
This pin is the positive supply of the control IC.
8
14
Vref
This is the reference output. It provides charging current for capacitor CT through resistor RT.
8
Power
Ground
11
VC
The Output high state (VOH) is set by the voltage applied to this pin. With a separate power
source connection, it can reduce the effects of switching transient noise on the control circuitry.
9
GND
This pin is the control circuitry ground return and is connected back to the power source ground.
2,4,6,1
3
NC
5
Description
This pin is the Error Amplifier output and is made available for loop compensation.
This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
and sunk by this pin.
This pin is a separate power ground return that is connected back to the power source. It is used
to reduce the effects of switching transient noise on the control circuitry.
No connection. These pins are not internally connected.
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NCV3843BV
OPERATING DESCRIPTION
is removed, or at the beginning of a soft−start interval
(Figures 24, 25). The Error Amp minimum feedback
resistance is limited by the amplifier’s source current
(0.5 mA) and the required output voltage (VOH) to reach the
comparator’s 1.0 V clamp level:
The NCV3843BV is a high performance, fixed frequency,
current mode controller. They are specifically designed for
Off−Line and DC−to−DC converter applications offering
the designer a cost−effective solution with minimal external
components. A representative block diagram is shown in
Figure 18.
Rf(min) ≈
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor CT
is charged from the 5.0 V reference through resistor RT to
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of CT, the oscillator
generates an internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
deadtime. Figure 2 shows RT versus Oscillator Frequency
and Figure 3, Output Deadtime versus Frequency, both for
given values of CT. Note that many values of RT and CT will
give the same oscillator frequency but only one combination
will yield a specific output deadtime at a given frequency.
The oscillator thresholds are temperature compensated to
within ±6% at 50 kHz. The NCV3843BV is guaranteed to
within ±10% at 250 kHz. These internal circuit refinements
minimize variations of oscillator frequency and maximum
output duty cycle. The results are shown in Figures 4 and 5.
In many noise−sensitive applications it may be desirable
to frequency−lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 21. For reliable locking, the
free−running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi−unit
synchronization is shown in Figure 22. By tailoring the
clock waveform, accurate Output duty cycle clamping can
be achieved.
3.0 (1.0 V) + 1.4 V
= 8800 W
0.5 mA
Current Sense Comparator and PWM Latch
The NCV3843BV operates as a current mode controller,
whereby output switch conduction is initiated by the
oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error
Amplifier Output/Compensation (Pin 1). Thus the error
signal controls the peak inductor current on a
cycle−by−cycle basis. The Current Sense Comparator PWM
Latch configuration used ensures that only a single pulse
appears at the Output during any given oscillator cycle. The
inductor current is converted to a voltage by inserting the
ground−referenced sense resistor RS in series with the
source of output switch Q1. This voltage is monitored by the
Current Sense Input (Pin 3) and compared to a level derived
from the Error Amp Output. The peak inductor current under
normal operating conditions is controlled by the voltage at
pin 1 where:
Ipk =
V(Pin 1) − 1.4 V
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
Ipk(max) =
1.0 V
RS
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of RS to a reasonable
level. A simple method to adjust this voltage is shown in
Figure 23. The two external diodes are used to compensate
the internal diodes, yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the Ipk(max) clamp
voltage.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with
a time constant that approximates the spike duration will
usually eliminate the instability (refer to Figure 27).
Error Amplifier
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical
DC voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 8). The
non−inverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is −2.0 mA which can cause an output
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external
loop compensation (Figure 32). The output voltage is offset
by two diode drops (≈1.4 V) and divided by three before it
connects to the non−inverting input of the Current Sense
Comparator. This guarantees that no drive pulses appear at
the Output (Pin 6) when pin 1 is at its lowest state (VOL).
This occurs when the power supply is operating and the load
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8
NCV3843BV
VCC
VCC
7(12)
36V
Vref
Reference
Regulator
8(14)
R
2.5V
RT
Vin
+
-
VCC
UVLO
Internal
Bias
R
+
-
3.6V
(See
Text)
VC
7(11)
Vref
UVLO
Output
Q1
Oscillator
CT
4(7)
6(10)
+ 1.0mA
S
Voltage
Feedback
Input 2(3)
Output/
Compensation 1(1)
2R
Q
R
R
Error
Amplifier
Power Ground
PWM
Latch
1.0V
Current Sense Input
Current Sense
Comparator
GND
5(8)
3(5)
5(9)
Pin numbers adjacent to terminals are for the 8-pin package.
Pin numbers in parenthesis are for the D suffix SOIC-14 package.
= Sink Only Positive True Logic
Figure 18. Representative Block Diagram
Capacitor CT
Latch
“Set" Input
Output/
Compensation
Current Sense
Input
Latch
“Reset" Input
Output
Small RT/Large CT
Large RT/Small CT
Figure 19. Timing Diagram
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9
RS
NCV3843BV
Undervoltage Lockout
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 mF) connected directly to VCC, VC,
and Vref may be required depending upon circuit layout.
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise−generating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulator’s closed loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 20A
shows the phenomenon graphically. At t0, switch
conduction begins, causing the inductor current to rise at a
slope of m1. This slope is a function of the input voltage
divided by the inductance. At t1, the Current Sense Input
reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at
a slope of m2, until the next oscillator cycle. The unstable
condition can be shown if a perturbation is added to the
control voltage, resulting in a small DI (dashed line). With
a fixed oscillator period, the current decay time is reduced,
and the minimum current at switch turn−on (t2) is increased
by DI + DI m2/m1. The minimum current at the next cycle
(t3) decreases to (DI + DI m2/m1) (m2/m1). This perturbation
is multiplied by m2/m1 on each succeeding cycle, alternately
increasing and decreasing the inductor current at switch
turn−on. Several oscillator cycles may be required before
the inductor current reaches zero causing the process to
commence again. If m2/m1 is greater than 1, the converter
will be unstable. Figure 20B shows that by adding an
artificial ramp that is synchronized with the PWM clock to
the control voltage, the DI perturbation will decrease to zero
on succeeding cycles. This compensating ramp (m3) must
have a slope equal to or slightly greater than m2/2 for
stability. With m2/2 slope compensation, the average
inductor current follows the control voltage, yielding true
current mode operation. The compensating ramp can be
derived from the oscillator and added to either the Voltage
Feedback or Current Sense inputs (Figure 33).
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (VCC) and the reference output (Vref) are
each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 8.4 V/7.6 V for the
NCV3843BV. The Vref comparator upper and lower
thresholds are 3.6 V/3.4 V. The NCV3843BV is intended for
lower voltage DC−to−DC converter applications. A 36 V
Zener is connected as a shunt regulator from VCC to ground.
Its purpose is to protect the IC from excessive voltage that
can occur during system startup. The minimum operating
voltage (VCC) for the NCV3843BV is 8.2 V.
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull−down resistor.
The SOIC−14 surface mount package provides separate
pins for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the Ipk(max)
clamp level. The separate VC supply input allows the
designer added flexibility in tailoring the drive voltage
independent of VCC. A Zener clamp is typically connected
to this input when driving power MOSFETs in systems
where VCC is greater than 20 V. Figure 26 shows proper
power and control ground connections in a current−sensing
power MOSFET application.
Reference
The 5.0 V bandgap reference is trimmed to ±2.0% on the
NCV3843BV. Its primary purpose is to supply charging
current to the oscillator timing capacitor. The reference has
short− circuit protection and is capable of providing in
excess of 20 mA for powering additional control system
circuitry.
Design Considerations
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse−width jitter. This is usually caused by excessive noise
www.onsemi.com
10
NCV3843BV
(A)
DI
Control Voltage
m2
m1
Inductor
Current
Dl ) Dl m2
m1
Dl ) Dl m2 m2
m1 m1
Vref
8(14)
Oscillator Period
t0
t1
t2
External
Sync
Input
m3
DI
Bias
RT
t3
(B)
Control Voltage
R
R
Osc
4(7)
CT
+
0.01
2R
m1
2(3)
47
m2
Inductor
Current
R
EA
1(1)
5(9)
Oscillator Period
t4
t5
The diode clamp is required if the Sync amplitude is large enough to cause the bottom
side of CT to go more than 300 mV below ground.
t6
Figure 20. Continuous Current Waveforms
Figure 21. External Clock Synchronization
VCC
Vin
7(12)
5.0V Ref
8(14)
8(14)
6
Q1
Osc
5.0k
3
5.0k
2
7(11)
+
-
R
4
4(7)
Osc
R
5
R
Bias
8
+
-
Bias
R
RA
RB
R
4(7)
Q
Q
2R
S
S
1.0 mA
+
7
R
2R
R
EA
2(3)
1.0V
C
5.0k
MC1455
2(3)
EA
6(10)
VClamp
+
R2
5(8)
Comp/Latch
R
3(5)
1(1)
1
R1
5(9)
1(1)
f +
1.44
(RA ) 2RB)C
D(max) +
RB
RA ) 2RB
5(9)
To Additional
UCX84XBs
Figure 22. External Duty Cycle Clamp and
Multi−Unit Synchronization
VClamp ≈
1.67
ǒ
Ǔ
R2
)1
R1
+ 0.33x10-3
ǒR1R)1R2R2Ǔ
Where: 0 ≤ VClamp ≤ 1.0 V
Ipk(max) [
VClamp
RS
Figure 23. Adjustable Reduction of Clamp Level
www.onsemi.com
11
RS
NCV3843BV
VCC
Vin
7(12)
5.0V Ref
8(14)
+
-
R
Bias
5.0V Ref
8(14)
R
7(11)
+
-
R
Bias
Q1
Osc
R
4(7)
Q
Q
EA
C
1.0V
R1
3(5)
MPSA63
VClamp [
tSoftStart + * In 1 *
Figure 24. Soft−Start Circuit
VCC
1.67
ǒRR21 ) 1Ǔ
ƪ
C
5(9)
Where: 0 ≤ VClamp ≤ 1.0 V
ƫ
R1R2
VC
C
R1 ) R2
3VClamp
Ipk(max) [
VClamp
RS
Figure 25. Adjustable Buffered Reduction of
Clamp Level with Soft−Start
Vin
VPin 5 [
(12)
RS Ipk rDS(on)
rDM(on) ) RS
VCC
If: SENSEFET = MTP10N10M
RS = 200
5.0V Ref
Vin
7(12)
Then : VPin5 [ 0.075Ipk
+
-
5.0V Ref
D
(11)
+
-
RS
5(9)
1(1)
tSoft-Start ≈ 3600C in mF
5(8)
Comp/Latch
1(1)
R
2R
R
1.0V
R2
S
1.0mA
2(3)
R
2R
R
EA
2(3)
+
1.0M
S
1.0 mA
Osc
4(7)
6(10)
VClamp
+
+
-
+
-
SENSEFET
S
K
(10)
7(11)
+
-
G
Q1
M
6(10)
S
Q
R
S
(8)
Q
5(8)
R
Comp/Latch
(5)
RS
1/4 W
Power Ground:
To Input Source
Return
Comp/Latch
3(5)
R
C
RS
Control Circuitry Ground:
To Pin (9)
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over-current conditions, a
reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 23 and 25.
The addition of the RC filter will eliminate instability caused by the leading
edge spike on the current waveform.
Figure 26. Current Sensing Power MOSFET
Figure 27. Current Waveform Spike Suppression
www.onsemi.com
12
NCV3843BV
VCC
Vin
IB
7(12)
Vin
+
0
5.0V Ref
+
-
Base Charge
Removal
7(11)
+
-
C1
Rg
Q1
Q1
6(10)
6(10)
S
Q
R
5(8)
5(8)
Comp/Latch
3(5)
RS
3(5)
RS
Series gate resistor Rg will damp any high frequency parasitic oscillations
caused by the MOSFET input capacitance and any series wiring inductance in
the gate-source circuit.
The totem pole output can furnish negative base current for enhanced
transistor turn-off, with the addition of capacitor C1.
Figure 28. MOSFET Parasitic Oscillations
Figure 29. Bipolar Transistor Drive
Vin
VCC
8(14)
R
Bias
7(12)
R
Isolation
Boundary
Osc
5.0V Ref
4(7)
+
7(11)
+
-
Q1
+
50% DC
Q
5(8)
Ipk +
R
Comp/Latch
2(3)
0
-
6(10)
25% DC
ǒ Ǔ
V(Pin1) * 1.4 NS
Np
3RS
R
3(5)
C
RS
NS
1.0 mA
2R
+
0
S
+
VGS Waveforms
EA
R
1(1)
MCR
101
2N
3905
5(9)
2N
3903
NP
The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The simple two
transistor circuit can be used in place of the SCR as shown. All resistors are 10 k.
Figure 30. Isolated MOSFET Drive
Figure 31. Latched Shutdown
www.onsemi.com
13
NCV3843BV
From VO
2.5V
+
Ri
1.0mA 2R
2(3)
Cf
Rd
EA
Rf
R
1(1)
Rf ≥ 8.8 k
5(9)
Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback
converters operating with continuous inductor current.
From VO
2.5V
+
Rp
Cp
1.0mA
Ri
2(3)
Cf
Rd
2R
R
EA
Rf
1(1)
5(9)
Error Amp compensation circuit for stabilizing current mode boost and flyback
topologies operating with continuous inductor current.
Figure 32. Error Amplifier Compensation
VCC
Vin
7(12)
36V
8(14)
RT
RSlope
CT
Rd
+
+
2(3)
Cf
Rf
1(1)
7(11)
Osc
4(7)
1.0mA
Ri
+
-
Bias
R
MPS3904
From VO
5.0V Ref
R
-m
R
EA
R
1.0V
6(10)
S
2R
Q
m
- 3.0m
5(9)
The buffered oscillator ramp can be resistively summed with either the voltage
feedback or current sense inputs to provide slope compensation.
Figure 33. Slope Compensation
www.onsemi.com
14
5(8)
Comp/Latch
3(5)
RS
NCV3843BV
ORDERING INFORMATION
Device
Operating Temperature Range
NCV3843BVD1R2G
TA = −40° to +125°C
NCV3843BVDR2G
Package
Shipping†
SOIC−8
(Pb−Free)
2500 Tape & Reel
SOIC−14
(Pb−Free)
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
SOIC−14
D SUFFIX
CASE 751A
SOIC−8
D1 SUFFIX
CASE 751
14
8
3843B
ALYW
G
UC3843BVDG
AWLYWW
1
1
A
WL, L
Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
www.onsemi.com
15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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