NCV3843BVDR2G

NCV3843BV High Performance Current Mode Controllers The NCV3843BV is a high performance fixed frequency current mode controller. They are specifically designed for Off−Line and DC−DC converter applications offering the designer a cost−effective solution with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle−by−cycle current limiting, programmable output deadtime, and a latch for single pulse metering. These devices are available in a surface mount (SOIC−8) plastic package as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14 package has separate power and ground pins for the totem pole output stage. The NCV3843BV is tailored for lower voltage applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off). Features http://onsemi.com 14 1 SOIC−14 D SUFFIX CASE 751A 8 1 SOIC−8 D1 SUFFIX CASE 751 PIN CONNECTIONS Compensation Voltage Feedback Current Sense RT/CT 1 2 3 4 8 7 6 5 • • • • • • • • • • Trimmed Oscillator for Precise Frequency Control Oscillator Frequency Guaranteed at 250 kHz Current Mode Operation to 500 kHz Automatic Feed Forward Compensation Latching PWM for Cycle−By−Cycle Current Limiting Internally Trimmed Reference with Undervoltage Lockout High Current Totem Pole Output Undervoltage Lockout with Hysteresis Low Startup and Operating Current These are Pb−Free Devices VCC Vref 8(14) R R RT/CT 4(7) Voltage Feedback Input + - Vref VCC Output GND (Top View) Compensation NC Voltage Feedback NC Current Sense NC RT/CT 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Vref NC VCC VC Output GND Power Ground 7(12) (Top View) 5.0V Reference Vref Undervoltage Lockout Oscillator Latching PWM Error Amplifier GND 5(9) VCC Undervoltage Lockout VC 7(11) Output 6(10) Power Ground 5(8) Current Sense 3(5) Input ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 15 of this data sheet. 2(3) Output Compensation 1(1) Pin numbers in parenthesis are for the D suffix SOIC−14 package. Figure 1. Simplified Block Diagram © Semiconductor Components Industries, LLC, 2008 September, 2008 − Rev. 0 1 Publication Order Number: NCV3843BV/D NCV3843BV MAXIMUM RATINGS Rating Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) Total Power Supply and Zener Current Output Current, Source or Sink Output Energy (Capacitive Load per Cycle) Current Sense and Voltage Feedback Inputs Error Amp Output Sink Current Power Dissipation and Thermal Characteristics D Suffix, Plastic Package, SOIC−14 Case 751A Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction−to−Air D1 Suffix, Plastic Package, SOIC−8 Case 751 Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction−to−Air Operating Junction Temperature Operating Ambient Temperature Storage Temperature Range Symbol VCC, VC (ICC + IZ) IO W Vin IO Value 30 30 1.0 5.0 − 0.3 to + 5.5 10 Unit V mA A mJ V mA PD RqJA PD RqJA TJ TA Tstg 862 145 702 178 +150 −40 to +125 − 65 to +150 mW °C/W mW °C/W °C °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC Standard JESD22-A114B Machine Model Method 200 V per JEDEC Standard JESD22-A115-A 2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78 http://onsemi.com 2 NCV3843BV ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 3], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 4], unless otherwise noted.) Characteristics REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Line Regulation (VCC = 12 V to 25 V) Load Regulation (IO = 1.0 mA to 20 mA) Temperature Stability Total Output Variation over Line, Load, and Temperature Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Long Term Stability (TA = 125°C for 1000 Hours) Output Short Circuit Current OSCILLATOR SECTION Frequency TJ = 25°C TA = Tlow to Thigh TJ = 25°C (RT = 6.2 k, CT = 1.0 nF) Frequency Change with Voltage (VCC = 12 V to 25 V) Frequency Change with Temperature, TA = Tlow to Thigh Oscillator Voltage Swing (Peak−to−Peak) Discharge Current (VOSC = 2.0 V) TJ = 25°C, TA = Tlow to Thigh ERROR AMPLIFIER SECTION Voltage Feedback Input (VO = 2.5 V) Input Bias Current (VFB = 5.0 V) Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) Unity Gain Bandwidth (TJ = 25°C) Power Supply Rejection Ratio (VCC = 12 V to 25 V) Output Current Sink (VO = 1.1 V, VFB = 2.7 V) Source (VO = 5.0 V, VFB = 2.3 V) Output Voltage Swing High State (RL = 15 k to ground, VFB = 2.3 V) Low State (RL = 15 k to Vref, VFB = 2.7 V) CURRENT SENSE SECTION Current Sense Input Voltage Gain (Notes 5 and 6) Maximum Current Sense Input Threshold (Note 5) Power Supply Rejection Ratio (VCC = 12 V to 25 V, Note 5) Input Bias Current Propagation Delay (Current Sense Input to Output) AV Vth PSRR IIB tPLH(In/Out) 2.85 0.85 − − − 3.0 1.0 70 − 2.0 150 3.25 1.1 − −10 300 V/V V dB mA ns VFB IIB AVOL BW PSRR ISink 2.42 − 65 0.7 60 2.0 − 0.5 5.0 − 2.5 − 0.1 90 1.0 70 12 −1.0 6.2 0.8 2.58 − 2.0 − − − − − − 1.2 V mA dB MHz dB mA fOSC 49 48 225 − − − 7.8 7.2 52 − 250 0.2 0.5 1.6 8.3 − 55 56 275 1.0 − − 8.8 8.8 kHz Vref Regline Regload TS Vref Vn S ISC 4.9 − − − 4.82 − − − 30 5.0 2.0 3.0 0.2 − 50 5.0 − 85 5.1 20 25 − 5.18 − − −180 V mV mV mV/°C V mV mV mA Symbol Min Typ Max Unit DfOSC/DV DfOSC/DT VOSC Idischg % % V mA ISource VOH VOL V 3. Adjust VCC above the Startup threshold before setting to 15 V. 4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. NCV3843BV: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site and change control. 5. This parameter is measured at the latch trip point with VFB = 0 V. 6. Comparator gain is defined as: AV DV Output Compensation DV Current Sense Input http://onsemi.com 3 NCV3843BV ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 7], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 8], unless otherwise noted.) Characteristics OUTPUT SECTION Output Voltage Low State (ISink = 20 mA) (ISink = 200 mA) High State (ISource = 20 mA) (ISource = 200 mA) Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) UNDERVOLTAGE LOCKOUT SECTION Startup Threshold (VCC) Minimum Operating Voltage After Turn−On (VCC) PWM SECTION Duty Cycle Maximum Minimum TOTAL DEVICE Power Supply Current Startup (VCC 14 V) (Note 7) Power Supply Zener Voltage (ICC = 25 mA) ICC + IC VZ − 30 12 36 17 − mA V DC(max) DC(min) 93 − 96 − − 0 % Vth VCC(min) 7.8 7.0 8.4 7.6 9.0 8.2 V V VOL VOH VOL(UVLO) tr tf − − 12.9 12 − − − 0.1 1.6 13.5 13.4 0.1 50 50 0.4 2.3 − − 1.1 150 150 V Symbol Min Typ Max Unit V ns ns 7. Adjust VCC above the Startup threshold before setting to 15 V. 8. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. NCV3843BV: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site and change control. http://onsemi.com 4 NCV3843BV 80 % DT, PERCENT OUTPUT DEADTIME 50 R T, TIMING RESISTOR (k Ω) 20 8.0 5.0 2.0 0.8 10 k VCC = 15 V TA = 25°C 20 k 50 k 100 k 200 k 500 k fOSC, OSCILLATOR FREQUENCY (kHz) 1.0 M 100 1. CT = 10 nF 50 2. CT = 5.0 nF 3. CT = 2.0 nF 4. CT = 1.0 nF 20 5. CT = 500 pF 6. CT = 200 pF 10 7. CT = 100 pF 5.0 2.0 1.0 10 k 20 k 4 3 2 1 5 6 7 VCC = 15 V TA = 25°C 50 k 100 k 200 k 500 k fOSC, OSCILLATOR FREQUENCY (kHz) 1.0 M Freq + 1 Vosc Ct Vosc ) Ct Idis*I I Rt Rt Where: Vosc = 1.7 V IRt = Vref/Rt Idis = 8.3 mA Figure 2. Timing Resistor versus Oscillator Frequency Figure 3. Output Deadtime versus Oscillator Frequency 9.0 I dischg , DISCHARGE CURRENT (mA) VCC = 15 V VOSC = 2.0 V 8.5 D max , MAXIMUM OUTPUT DUTY CYCLE (%) 100 90 80 70 60 50 40 0.8 Idischg = 8.8 mA Idischg = 7.5 mA 8.0 7.5 VCC = 15 V CT = 3.3 nF TA = 25°C 5.0 6.0 7.0 8.0 7.0 - 55 - 25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 1.0 2.0 3.0 4.0 RT, TIMING RESISTOR (kW) Figure 4. Oscillator Discharge Current versus Temperature Figure 5. Maximum Output Duty Cycle versus Timing Resistor 2.55 V VCC = 15 V AV = -1.0 TA = 25°C 20 mV/DIV 3.0 V VCC = 15 V AV = -1.0 TA = 25°C 20 mV/DIV 1.0 ms/DIV 2.50 V 2.5 V 2.45 V 0.5 ms/DIV 2.0 V Figure 6. Error Amp Small Signal Transient Response Figure 7. Error Amp Large Signal Transient Response http://onsemi.com 5 NCV3843BV A VOL , OPEN LOOP VOLTAGE GAIN (dB) 100 80 Gain 60 40 Phase 20 0 120 150 100 1.0 k 10 k 100 k 1.0 M 180 10 M VCC = 15 V VO = 2.0 V to 4.0 V RL = 100 K TA = 25°C Vth, CURRENT SENSE INPUT THRESHOLD (V) 0 30 60 90 φ EXCESS PHASE (DEGREES) , 1.2 VCC = 15 V 1.0 0.8 0.6 0.4 0.2 0 TA = 25°C TA = 125°C TA = -55°C - 20 10 0 f, FREQUENCY (Hz) 2.0 4.0 6.0 VO, ERROR AMP OUTPUT VOLTAGE (V) 8.0 Figure 8. Error Amp Open Loop Gain and Phase versus Frequency Figure 9. Current Sense Input Threshold versus Error Amp Output Voltage I SC , REFERENCE SHORT CIRCUIT CURRENT (mA) Δ Vref , REFERENCE VOLTAGE CHANGE (mV) 0 110 - 4.0 - 8.0 -12 -16 - 20 - 24 0 20 Iref, REFERENCE SOURCE CURRENT (mA) Figure 10. Reference Voltage Change versus Source Current Δ V O , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV) VCC = 15 V IO = 1.0 mA to 20 mA TA = 25°C Δ V O , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV) Figure 12. Reference Load Regulation ÄÄÄÄ ÄÄÄÄ ÄÄÄÄ TA = 25°C 60 40 80 2.0 ms/DIV TA = 125°C ÄÄÄÄ ÄÄÄ ÄÄÄ TA = -55°C 100 120 6 VCC = 15 V 90 70 50 - 55 - 25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) Figure 11. Reference Short Circuit Current versus Temperature VCC = 12 V to 25 TA = 25°C 2.0 ms/DIV Figure 13. Reference Line Regulation http://onsemi.com ÄÄÄ ÄÄÄ VCC = 15 V RL ≤ 0.1 W 100 125 NCV3843BV Vsat, OUTPUT SATURATION VOLTAGE (V) 0 -1.0 - 2.0 3.0 2.0 1.0 0 0 V O , OUTPUT VOLTAGE I CC , SUPPLY CURRENT (mA) 20 V/DIV I CC , SUPPLY CURRENT 10 5 0 0 10 20 100 ns/DIV VCC, SUPPLY VOLTAGE (V) Figure 16. Output Cross Conduction Figure 17. Supply Current versus Supply Voltage PIN FUNCTION DESCRIPTION 8−Pin 1 2 3 4 5 6 7 8 10 12 14 8 11 9 2,4,6,1 3 14−Pin 1 3 5 7 Function Compensation Voltage Feedback Current Sense RT/CT GND Output VCC Vref Power Ground VC GND NC Description This pin is the Error Amplifier output and is made available for loop compensation. This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible. This pin is the combined control circuitry and power ground. This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sunk by this pin. This pin is the positive supply of the control IC. This is the reference output. It provides charging current for capacitor CT through resistor RT. This pin is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. This pin is the control circuitry ground return and is connected back to the power source ground. No connection. These pins are not internally connected. http://onsemi.com 7 ÄÄÄÄ ÄÄÄÄ ÄÄÄÄ ÄÄÄÄ 100 mA/DIV ÄÄ ÄÄÄÄ ÄÄÄ ÄÄÄÄ ÄÄÄ ÄÄÄ ÄÄÄ ÄÄÄÄ ÄÄÄÄ ÄÄÄÄ ÄÄÄÄÄ Ä ÄÄ Ä Ä Ä Ä Ä Ä Ä Ä Ä ÄÄÄ Ä Ä Ä Ä Ä Ä Ä ÄÄÄÄ Ä VCC TA = 25°C Source Saturation (Load to Ground) VCC = 15 V 80 ms Pulsed Load 120 Hz Rate TA = - 55°C TA = - 55°C TA = 25°C Sink Saturation (Load to VCC) 400 GND 600 200 IO, OUTPUT LOAD CURRENT (mA) 90% VCC = 15 V CL = 1.0 nF TA = 25°C 10% 800 50 ns/DIV Figure 14. Output Saturation Voltage versus Load Current 25 VCC = 30 V CL = 15 pF TA = 25°C 20 15 Figure 15. Output Waveform RT = 10 k CT = 3.3 nF VFB = 0 V ISense = 0 V TA = 25°C 30 40 NCV3843BV OPERATING DESCRIPTION The NCV3843BV is a high performance, fixed frequency, current mode controller. They are specifically designed for Off−Line and DC−to−DC converter applications offering the designer a cost−effective solution with minimal external components. A representative block diagram is shown in Figure 18. Oscillator is removed, or at the beginning of a soft−start interval (Figures 24, 25). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5 mA) and the required output voltage (VOH) to reach the comparator’s 1.0 V clamp level: Rf(min) ≈ 3.0 (1.0 V) + 1.4 V = 8800 W 0.5 mA The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 2 shows RT versus Oscillator Frequency and Figure 3, Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated to within ±6% at 50 kHz. The NCV3843BV is guaranteed to within ±10% at 250 kHz. These internal circuit refinements minimize variations of oscillator frequency and maximum output duty cycle. The results are shown in Figures 4 and 5. In many noise−sensitive applications it may be desirable to frequency−lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 21. For reliable locking, the free−running oscillator frequency should be set about 10% less than the clock frequency. A method for multi−unit synchronization is shown in Figure 22. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved. Error Amplifier Current Sense Comparator and PWM Latch The NCV3843BV operates as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak inductor current on a cycle−by−cycle basis. The Current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground−referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: Ipk = V(Pin 1) − 1.4 V 3 RS Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is: Ipk(max) = 1.0 V RS A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical DC voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz with 57 degrees of phase margin (Figure 8). The non−inverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is −2.0 mA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 32). The output voltage is offset by two diode drops (≈1.4 V) and divided by three before it connects to the non−inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when pin 1 is at its lowest state (VOL). This occurs when the power supply is operating and the load When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 23. The two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk(max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability (refer to Figure 27). http://onsemi.com 8 NCV3843BV VCC Vin VCC 7(12) Vref 8(14) RT 2.5V R R Internal Bias 3.6V Oscillator CT 4(7) + 1.0mA 36V Reference Regulator VCC UVLO + Vref UVLO + (See Text) VC 7(11) Output 6(10) Q1 S Voltage Feedback Input 2(3) Output/ Compensation 1(1) 2R R Error Amplifier R 1.0V Current Sense Comparator GND 5(9) Q Power Ground PWM Latch 5(8) Current Sense Input 3(5) RS Pin numbers adjacent to terminals are for the 8-pin package. Pin numbers in parenthesis are for the D suffix SOIC-14 package. = Sink Only Positive True Logic Figure 18. Representative Block Diagram Capacitor CT Latch “Set" Input Output/ Compensation Current Sense Input Latch “Reset" Input Output Large RT/Small CT Small RT/Large CT Figure 19. Timing Diagram http://onsemi.com 9 NCV3843BV Undervoltage Lockout Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (VCC) and the reference output (Vref) are each monitored by separate comparators. Each has built−in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 8.4 V/7.6 V for the NCV3843BV. The Vref comparator upper and lower thresholds are 3.6 V/3.4 V. The NCV3843BV is intended for lower voltage DC−to−DC converter applications. A 36 V Zener is connected as a shunt regulator from VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage (VCC) for the NCV3843BV is 8.2 V. These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. It is capable of up to ±1.0 A peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pull−down resistor. The SOIC−14 surface mount package provides separate pins for VC (output supply) and Power Ground. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the Ipk(max) clamp level. The separate VC supply input allows the designer added flexibility in tailoring the drive voltage independent of VCC. A Zener clamp is typically connected to this input when driving power MOSFETs in systems where VCC is greater than 20 V. Figure 26 shows proper power and control ground connections in a current−sensing power MOSFET application. Reference The 5.0 V bandgap reference is trimmed to ±2.0% on the NCV3843BV. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short− circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry. Design Considerations Do not attempt to construct the converter on wire−wrap or plug−in prototype boards. High frequency circuit layout techniques are imperative to prevent pulse−width jitter. This is usually caused by excessive noise pick−up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low−current signal and high−current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 mF) connected directly to VCC, VC, and Vref may be required depending upon circuit layout. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise−generating components. Current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. This instability is independent of the regulator’s closed loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. Figure 20A shows the phenomenon graphically. At t0, switch conduction begins, causing the inductor current to rise at a slope of m1. This slope is a function of the input voltage divided by the inductance. At t1, the Current Sense Input reaches the threshold established by the control voltage. This causes the switch to turn off and the current to decay at a slope of m2, until the next oscillator cycle. The unstable condition can be shown if a perturbation is added to the control voltage, resulting in a small DI (dashed line). With a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turn−on (t2) is increased by DI + DI m2/m1. The minimum current at the next cycle (t3) decreases to (DI + DI m2/m1) (m2/m1). This perturbation is multiplied by m2/m1 on each succeeding cycle, alternately increasing and decreasing the inductor current at switch turn−on. Several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. If m2/m1 is greater than 1, the converter will be unstable. Figure 20B shows that by adding an artificial ramp that is synchronized with the PWM clock to the control voltage, the DI perturbation will decrease to zero on succeeding cycles. This compensating ramp (m3) must have a slope equal to or slightly greater than m2/2 for stability. With m2/2 slope compensation, the average inductor current follows the control voltage, yielding true current mode operation. The compensating ramp can be derived from the oscillator and added to either the Voltage Feedback or Current Sense inputs (Figure 33). http://onsemi.com 10 NCV3843BV DI Control Voltage m1 Inductor Current m2 Dl ) Dl m2 m2 m1 m1 t2 (B) Control Voltage DI m3 m1 m2 Oscillator Period t4 t5 t6 The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300 mV below ground. Vref 8(14) R Bias R (A) Dl ) Dl m 2 m1 Oscillator Period t0 t1 t3 External Sync Input 0.01 RT Osc CT 4(7) + 2R 47 2(3) EA R Inductor Current 1(1) 5(9) Figure 20. Continuous Current Waveforms Figure 21. External Clock Synchronization VCC 7(12) Vin 5.0V Ref 8(14) 8(14) RA 8 RB 6 5 2 C 5.0k 1 1(1) To Additional UCX84XBs 5(9) R Bias R R Bias R + + 7(11) Q1 4 5.0k R 5.0k S MC1455 2(3) Q 7 3 Osc 4(7) Osc 4(7) + 2R R 1(1) R1 1.67 R2 )1 R1 5(9) R2 + 1.0 mA VClamp S Q R 1.0V Comp/Latch 6(10) 2(3) EA 2R R 5(8) EA 3(5) RS VClamp ≈ + 0.33x10-3 R1R2 R1 ) R2 Where: 0 ≤ VClamp ≤ 1.0 V Ipk(max) [ VClamp RS f+ 1.44 (RA ) 2RB)C D(max) + RB RA ) 2RB Figure 22. External Duty Cycle Clamp and Multi−Unit Synchronization Figure 23. Adjustable Reduction of Clamp Level http://onsemi.com 11 NCV3843BV VCC 7(12) Vin 5.0V Ref 8(14) 5.0V Ref 8(14) R Bias Osc R + Osc 4(7) + 1.0mA 2(3) 1.0M 1(1) C tSoft-Start ≈ 3600C in mF 5(9) R Bias R + - + 7(11) Q1 6(10) S Q R 1.0V Comp/Latch 3(5) 5(9) 4(7) + 1.0 mA VClamp 2(3) S Q 2R R R 1.0V C R2 1(1) R1 MPSA63 EA 2R R 5(8) RS EA VClamp [ 1.67 R2 )1 R1 Where: 0 ≤ VClamp ≤ 1.0 V tSoftStart + * In 1 * R1 R2 VC C R1 ) R2 3 VClamp Ipk(max) [ VClamp RS Figure 24. Soft−Start Circuit Figure 25. Adjustable Buffered Reduction of Clamp Level with Soft−Start VCC (12) Vin VPin 5 [ RS Ipk rDS(on) rDM(on) ) RS VCC 7(12) Vin If: SENSEFET = MTP10N10M RS = 200 5.0V Ref + D + (11) G K (10) S Q R Comp/Latch (5) Control Circuitry Ground: To Pin (9) Virtually lossless current sensing can be achieved with the implementation of a SENSEFET power switch. For proper operation during over-current conditions, a reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 23 and 25. RS 1/4 W Power Ground: To Input Source Return (8) R Comp/Latch S Q M Then : VPin 5 [ 0.075 Ipk 5.0V Ref SENSEFET S + - + 7(11) Q1 6(10) 5(8) 3(5) C R RS The addition of the RC filter will eliminate instability caused by the leading edge spike on the current waveform. Figure 26. Current Sensing Power MOSFET Figure 27. Current Waveform Spike Suppression http://onsemi.com 12 NCV3843BV VCC 7(12) + 5.0V Ref + + 7(11) C1 Rg 6(10) S Q R Comp/Latch 3(5) RS 5(8) 5(8) 6(10) Q1 Q1 0 Base Charge Removal Vin IB Vin 3(5) RS Series gate resistor Rg will damp any high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate-source circuit. The totem pole output can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor C1. Figure 28. MOSFET Parasitic Oscillations Figure 29. Bipolar Transistor Drive VCC 7(12) Isolation Boundary 5.0V Ref + + 7(11) Q1 Vin 8(14) R Bias R Osc 4(7) VGS Waveforms + 0 6(10) S Q R 5(8) 50% DC V(Pin1) * 1.4 3 RS + 0 25% DC NS Np MCR 101 2N 3905 2N 3903 2(3) EA R + 1.0 mA 2R 1(1) 5(9) Ipk + R C RS NS Comp/Latch 3(5) NP The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10 k. Figure 30. Isolated MOSFET Drive Figure 31. Latched Shutdown http://onsemi.com 13 NCV3843BV From VO Ri Cf 2.5V + 2(3) Rf 1(1) Rf ≥ 8.8 k 5(9) 1.0mA 2R EA R Rd Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback converters operating with continuous inductor current. From VO Rp Cp 2.5V + 1.0mA Ri Rd Cf 2(3) Rf 1(1) 5(9) 2R R EA Error Amp compensation circuit for stabilizing current mode boost and flyback topologies operating with continuous inductor current. Figure 32. Error Amplifier Compensation VCC 7(12) Vin 36V 8(14) RT MPS3904 RSlope Ri Cf 5.0V Ref R Bias R Osc + 1.0mA 2(3) Rf 1(1) EA 2R R 1.0V -m S R Q 5(8) 3(5) RS 6(10) + + 7(11) From VO CT 4(7) Rd Comp/Latch m - 3.0m 5(9) The buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation. Figure 33. Slope Compensation http://onsemi.com 14 NCV3843BV ORDERING INFORMATION Device NCV3843BVD1R2G NCV3843BVDR2 NCV3843BVDR2G TA = −40° to +125°C Operating Temperature Range Package SOIC−8 (Pb−Free) SOIC−14 SOIC−14 (Pb−Free) Shipping† 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS SOIC−14 D SUFFIX CASE 751A 14 NCV3843BVDG AWLYWW 1 A WL, L Y WW, W G or G 1 8 3843B ALYW G SOIC−8 D1 SUFFIX CASE 751 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package http://onsemi.com 15 NCV3843BV PACKAGE DIMENSIONS SOIC−8 D1 SUFFIX CASE 751−07 ISSUE AJ −X− A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 B 1 S 4 0.25 (0.010) M Y M −Y− G K C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 16 NCV3843BV PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE J −A− 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 −B− P 7 PL 0.25 (0.010) M B M 1 7 G C R X 45 _ F −T− SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J SOLDERING FOOTPRINT 7X 7.04 1 0.58 14X 14X 1.52 1.27 PITCH DIMENSIONS: MILLIMETERS SENSEFET is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 17 NCV3843BV/D