NCV4264-2
Linear Regulator,
Low Dropout, Low IQ
The NCV4264−2 is functionally and pin for pin compatible with
NCV4264 with a lower quiescent current consumption. Its output
stage supplies 100 mA with ±2.0% output voltage accuracy.
Maximum dropout voltage is 500 mV at 100 mA load current.
It is internally protected against 45 V input transients, input supply
reversal, output overcurrent faults, and excess die temperature. No
external components are required to enable these features.
Features
•
•
•
•
•
•
•
•
3.3 V and 5.0 V Fixed Output
±2.0% Output Accuracy, Over Full Temperature Range
60 mA Maximum Quiescent Current at IOUT = 100 mA
500 mV Maximum Dropout Voltage at 100 mA Load Current
Wide Input Voltage Operating Range of 4.5 V to 45 V
Internal Fault Protection
♦ −42 V Reverse Voltage
♦ Short Circuit/Overcurrent
♦ Thermal Overload
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This is a Pb−Free Device
www.onsemi.com
MARKING
DIAGRAM
TAB
1
2
3
SOT−223
ST SUFFIX
CASE 318E
AYW
V642xG
G
1
8
8
1
SOIC−8 Fused
CASE 751
1
x
A
L
Y
W
G
V642x
ALYWX
G
= 5 (5.0 V Version)
= 3 (3.3 V Version)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
(SOT−223)
PIN
FUNCTION
1
VIN
2,TAB GND
3
VOUT
(SOIC−8 Fused)
PIN
FUNCTION
1
NC
2,
VIN
3
GND
4.
VOUT
5−8.
NC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
November, 2018 − Rev. 10
1
Publication Order Number:
NCV4264−2/D
NCV4264−2
IN
OUT
1.3 V
Reference
+
Error
Amp
-
Thermal
Shutdown
GND
Figure 1. Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
SOT−223
SOIC−8
Symbol
1
2
VIN
2
3
GND
Ground; substrate.
3
4
VOUT
Regulated output voltage; collector of the internal PNP pass transistor.
TAB
−
GND
−
1, 5−8
NC
Function
Unregulated input voltage; 4.5 V to 45 V.
Ground; substrate and best thermal connection to the die.
No Connection.
OPERATING RANGE
Rating
Symbol
Min
Max
Unit
VIN, DC Input Operating Voltage (Note 3)
VIN
4.5
+45
V
Junction Temperature Operating Range
TJ
−40
+150
°C
Symbol
Min
Max
Unit
VIN
−42
+45
V
VOUT
−0.3
+18
V
Tstg
−55
+150
°C
MAXIMUM RATINGS
Rating
VIN, DC Input Voltage
VOUT, DC Voltage
Storage Temperature
Moisture Sensitivity Level
SOT223
SOIC−8 Fused
MSL
3
1
−
ESD Capability, Human Body Model (Note 1)
VESDHB
4000
−
V
ESD Capability, Machine Model (Note 1)
VESDMIM
200
−
V
−
265 pk
Lead Temperature Soldering
Reflow (SMD Styles Only), Lead Free (Note 2)
Tsld
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A 114C)
ESD MM tested per AEC−Q100−003 (EIA/JESD22−A 115C)
2. Lead Free, 60 sec – 150 sec above 217°C, 40 sec max at peak.
3. See specific conditions for DC operating input voltage lower than 4.5 V in the ELECTRICAL CHRACTERISTICS table at page 3
www.onsemi.com
2
NCV4264−2
THERMAL RESISTANCE
Parameter
Symbol
Min
Max
Unit
°C/W
Junction−to−Ambient
SOT−223
SOIC−8 Fused
RqJA
−
99 (Note 4)
145
Junction−to−Case
SOT−223
SOIC−8 Fused
RqJC
−
17
−
ELECTRICAL CHARACTERISTICS (VIN = 13.5 V, TJ = −40°C to +150°C, unless otherwise noted.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Voltage
5.0 V Version
VOUT
5.0 mA v IOUT v 100 mA (Note 5)
6.0 V v VIN v 28 V
4.900
5.000
5.100
V
Output Voltage
3.3 V Version
VOUT
5.0 mA v IOUT v 100 mA (Note 5)
4.5 V v VIN v 28 V
3.234
3.300
3.366
V
Output Voltage
3.3 V Version
VOUT
IOUT = 5 mA, VIN = 4 V (Note 7)
3.234
3.300
3.366
V
Line Regulation
5.0 V Version
DVOUT vs. VIN
IOUT = 5.0 mA
6.0 V v VIN v 28 V
−30
5.0
+30
mV
Line Regulation
3.3 V Version
DVOUT vs. VIN
IOUT = 5.0 mA
4.5 V v VIN v 28 V
−30
5.0
+30
mV
Load Regulation
DVOUT vs. IOUT
1.0 mA v IOUT v 100 mA (Note 5)
−40
5.0
+40
mV
Dropout Voltage − 5.0 V Version
VIN−VOUT
IOUT = 100 mA (Notes 5 & 6)
−
270
500
mV
Dropout Voltage − 3.3 V Version
VIN−VOUT
IOUT = 100 mA (Notes 5 & 8)
−
−
1.266
V
Iq
IOUT = 100 mA
TJ = 25°C
TJ = −40°C to +85°C
TJ = −40°C to 150°C
−
−
−
33
33
33
55
60
70
Active Ground Current
IG(ON)
IOUT = 50 mA (Note 5)
−
1.5
4.0
mA
Power Supply Rejection
PSRR
VRIPPLE = 0.5 VP−P, F = 100 Hz
−
67
−
dB
Output Capacitor for Stability
5.0 V Version
COUT
ESR
IOUT = 0.1 mA to 100 mA
(Notes 5 & 7)
10
−
−
−
−
9.0
mF
W
Output Capacitor for Stability
3.3 V Version
COUT
ESR
IOUT = 0.1 mA to 100 mA
(Notes 5 & 7)
22
−
−
−
−
16
mF
W
Current Limit
IOUT(LIM)
VOUT = 4.5 V (5.0 V Version) (Note 5)
VOUT = 3.0 V (3.3 V Version) (Note 5)
150
150
−
−
500
500
mA
Short Circuit Current Limit
IOUT(SC)
VOUT = 0 V (Note 5)
40
−
500
mA
TTSD
(Note 7)
150
−
200
°C
Quiescent Current
mA
PROTECTION
Thermal Shutdown Threshold
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. 1 oz., 100 mm2 copper area.
5. Use pulse loading to limit power dissipation.
6. Dropout voltage = (VIN–VOUT), measured when the output voltage has dropped 100 mV relative to the nominal value obtained with
VIN = 13.5 V.
7. Not tested in production. Limits are guaranteed by design.
8. VDO = VIN − VOUT. For output voltage set to < 4.5 V, VDO will be constrained by the minimum input voltage.
4.5−45 V
Input
Vin
Cin
100 nF
4264−2
Vout
Output
COUT
10 mF − 5.0 V Version
22 mF − 3.3 V Version
GND
Figure 2. Applications Circuit
www.onsemi.com
3
NCV4264−2
TYPICAL CHARACTERISTIC CURVES − 5 V Version
10
Unstable Region
9
8
7
ESR (W)
6
5
4
3
2
1
0
Vin = 13.5 V
Cout ≥ 10 mF
Stable Region
0
25
50
75
100
125
150
OUTPUT CURRENT (mA)
Figure 3. ESR Stability vs. Output Current
(5 V Version)
0.4
125°C
10
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
12
25°C
8
−40°C
6
4
2
VIN = 13.5 V
0
0
50
100
150
200
25°C
−40°C
0.25
0.2
0.15
0.1
0.05
VIN = 13.5 V
0
5
10
15
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Figure 4. Quiescent Current vs. Output Current
(5 V Version)
Figure 5. Quiescent Current vs. Output Current
(Light Load) (5 V Version)
5.10
125°C
0.40
5.08
0.35
0.30
25°C
0.25
−40°C
OUTPUT VOLTAGE (V)
DROPOUT VOLTAGE (V)
125°C
0.3
0
0.45
0.20
0.15
0.10
0.05
0
0.35
0
50
100
150
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
−50
200
0
50
100
OUTPUT CURRENT (mA)
TEMPERATURE (°C)
Figure 6. Dropout Voltage vs. Output Current
(5 V Version)
Figure 7. Output Voltage vs. Temperature
(5 V Version)
www.onsemi.com
4
150
NCV4264−2
TYPICAL CHARACTERISTIC CURVES − 5 V Version
180
6.0
5.0
OUTPUT VOLTAGE (V)
140
120
100
80
TA = 25°C
60
40
0
0
10
20
4.0
3.0
2.0
1.0
TA = 125°C
20
30
40
0
50
RL = 50 W
0
2.0
4.0
6.0
8.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 8. Output Current vs. Input Voltage
(5 V Version)
Figure 9. Output Voltage vs. Input Voltage
(5 V Version)
16
QUIESCENT CURRENT (mA)
OUTPUT CURRENT (mA)
160
14
12
10
8
6
RL = 50 W
4
2
0
RL = 100 W
0
10
30
20
40
INPUT VOLTAGE (V)
Figure 10. Quiescent Current vs. Input Voltage
(5 V Version)
www.onsemi.com
5
50
10
NCV4264−2
TYPICAL CHARACTERISTIC CURVES − 3.3 V Version
9
3.6
3.3
125°C
8
25°C
OUTPUT VOLTAGE (V)
QUIESCENT CURRENT (mA)
10
7
−40°C
6
5
4
3
2
1
0
Vin = 13.5 V
0
25
50
75
100
125
150
175
1.2
0.9
0.6
Iout = 5 mA
0
5
10
15
20
25
30
35
40
INPUT VOLTAGE (V)
Figure 11. Quiescent Current vs. Output
Current (3.3 V Version)
Figure 12. Output Voltage vs. Input Voltage
(3.3 V Version)
45
3.366
3.355
3.344
7
OUTPUT VOLTAGE (V)
QUIESCENT CURRENT (mA)
1.5
OUTPUT CURRENT (mA)
6
5
4
3
Iout = 66 mA
2
1
Iout = 33 mA
0
5
10
15
20
25
30
35
40
45
3.333
3.322
3.311
3.300
3.289
3.278
3.267
3.256
3.245
3.234
−50
Vin = 13.5 V
Iout = 5 mA
−25
0
25
50
75
100
125
INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 13. Quiescent Current vs. Input Voltage
(3.3 V Version)
Figure 14. Output Voltage vs. Temperature
(3.3 V Version)
150
150
180
Vin = 13.5 V
Iout = 5 mA
140
OUTPUT CURRENT (mA)
QUIESCENT CURRENT (mA)
2.4
2.1
1.8
0.3
0
8
0
3.0
2.7
130
120
110
100
−50
−25
0
25
50
75
100
125
150
120
90
60
30
0
150
0
5
10
15
20
25
30
35
40
TEMPERATURE (°C)
INPUT VOLTAGE (V)
Figure 15. Quiescent Current vs. Temperature
(3.3 V Version)
Figure 16. Output Current vs. Input Voltage
(3.3 V Version)
www.onsemi.com
6
45
NCV4264−2
TYPICAL CHARACTERISTIC CURVES − 3.3 V Version
20
Unstable Region
ESR (W)
15
10
5
0
Vin = 13.5 V
Cout ≥ 22 mF
Stable Region
0
30
60
90
120
OUTPUT CURRENT (mA)
Figure 17. ESR Stability vs. Output Current
(3.3 V Version)
www.onsemi.com
7
150
NCV4264−2
Circuit Description
Calculating Power Dissipation in a Single Output
Linear Regulator
The NCV4264−2 is functionally and pin for pin
compatible with NCV4264 with a lower quiescent current
consumption. Its output stage supplies 100 mA with
$2.0% output voltage accuracy.
Maximum dropout voltage is 500 mV at 100 mA load
current. It is internally protected against 45 V input
transients, input supply reversal, output overcurrent faults,
and excess die temperature. No external components are
required to enable these features.
The maximum power dissipation for a single output
regulator (Figure 2) is:
(eq. 1)
PD(max) +
ƪ VIN(max) * VOUT(min) ƫ * IOUT(max) ) VIN(max) * Iq
Where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current for the
application, and Iq is the quiescent current the regulator
consumes at IOUT(max). Once the value of PD(max) is known,
the maximum permissible value of RqJA can be calculated:
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (VOUT) and drives the base of
a PNP series pass transistor by a buffer. The reference is a
bandgap design to give it a temperature−stable output.
Saturation control of the PNP is a function of the load
current and input voltage. Oversaturation of the output
power device is prevented, and quiescent current in the
ground pin is minimized.
PqJA +
(150° C * TA)
PD
(eq. 2)
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA’s less than the calculated value in Equation 2 will
keep the die temperature below 150°C. In some cases, none
of the packages will be sufficient to dissipate the heat
generated by the IC, and an external heat sink will be
required. The current flow and voltages are shown in the
Measurement Circuit Diagram.
Regulator Stability Considerations
The input capacitor CI1 in Figure 2 is necessary for
compensating input line reactance. Possible oscillations
caused by input inductance and input capacitance can be
damped by using a resistor of approximately 1 W in series
with CI2. The output or compensation capacitor, COUT
helps determine three main characteristics of a linear
regulator: startup delay, load transient response and loop
stability. Tantalum, aluminum electrolytic, film, or
ceramic capacitors are all acceptable solutions, however,
attention must be paid to ESR constraints. The capacitor
manufacturer ’s data sheet usually provides this
information. The value for the output capacitor COUT
shown in Figure 2 should work for most applications;
however, it is not necessarily the optimized solution.
Stability is guaranteed at values of CQ w 10 mF, with an
ESR v 9 W for the 5.0 V Version, and CQ w 22 mF with
an ESR v 16 W for the 3.3 V Version within the operating
temperature range. Actual limits are shown in a graph in the
Typical Performance Characteristics section.
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air. Each material in the heat flow path
between the IC and the outside environment will have a
thermal resistance. Like series electrical resistances, these
resistances are summed to determine the value of RqJA:
RqJA + RqJC ) RqCS ) RqSA
(eq. 3)
Where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heat sink thermal resistance, and
RqSA = the heat sink−to−ambient thermal resistance.
RqJA appears in the package section of the data sheet.
Like RqJA, it too is a function of package type. RqCS and
RqSA are functions of the package type, heat sink and the
interface between them. These values appear in data sheets
of heat sink manufacturers. Thermal, mounting, and heat
sinking are discussed in the ON Semiconductor application
note AN1040/D, available on the ON Semiconductor
Website.
www.onsemi.com
8
NCV4264−2
160
140
qJA (°C/W)
120
SOIC−8 Fused
100
SOT223
80
60
40
20
0
0
100
200
300
400
500
600
700
COPPER AREA (mm2)
Figure 18. qJA vs. Copper Spreader Area
1000
SOT223
100
SOIC−8 Fused
R(t) (°C/W)
10
1
0.1
0.01
0.001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 19. R(t) vs. Pulse Time
ORDERING INFORMATION
Device*
Package
Shipping†
NCV4264−2ST50T3G
SOT−223
(Pb−Free)
4000 / Tape & Reel
NCV4264−2ST33T3G
SOT−223
(Pb−Free)
4000 / Tape & Reel
NCV4264−2D33R2G
SOIC−8 Fused
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
www.onsemi.com
9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
ANODE
CATHODE
NC
CATHODE
STYLE 6:
PIN 1.
2.
3.
4.
RETURN
INPUT
OUTPUT
INPUT
STYLE 7:
PIN 1.
2.
3.
4.
ANODE 1
CATHODE
ANODE 2
CATHODE
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 8:
STYLE 12:
PIN 1. INPUT
2. OUTPUT
3. NC
4. OUTPUT
CANCELLED
DATE 02 OCT 2018
STYLE 4:
PIN 1.
2.
3.
4.
SOURCE
DRAIN
GATE
DRAIN
STYLE 5:
PIN 1.
2.
3.
4.
STYLE 9:
PIN 1.
2.
3.
4.
INPUT
GROUND
LOGIC
GROUND
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
DRAIN
GATE
SOURCE
GATE
STYLE 13:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
XXXXX = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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