NCV4264
Linear Regulator,
100 mA, Low Dropout
The NCV4264 is a wide input range, precision 3.3 V and 5.0 V
fixed output, low dropout integrated voltage regulator with a full
load current rating of 100 mA.
The output voltage is accurate within ±2.0%, and maximum
dropout voltage is 500 mV at 100 mA load current.
It is internally protected against 45 V input transients, input supply
reversal, output overcurrent faults, and excess die temperature. No
external components are required to enable these features.
www.onsemi.com
MARKING
DIAGRAMS
TAB
•
•
•
•
•
•
•
•
3.3 V and 5.0 V Fixed Output
±2.0% Output Accuracy, Over Full Temperature Range
Quiescent Current 400 mA at IOUT = 1.0 mA
500 mV Maximum Dropout Voltage at 100 mA Load Current
Wide Input Voltage Operating Range of 4.5 V to 45 V
Internal Fault Protection
♦ −42 V Reverse Voltage
♦ Short Circuit/Overcurrent
♦ Thermal Overload
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
1
2
AYW
V64_xG
G
SOT−223
ST SUFFIX
CASE 318E
Features
3
1
8
SO−8
D SUFFIX
CASE 751
8
1
1
A
L
Y
W
x
V4264x
ALYW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= 3 (3.3 V Version)
= 5 (5.0 V Version)
= Pb−Free Package
G
(Note: Microdot may be in either location)
PIN CONNECTIONS
GND
1
VIN GND VOUT
SOT−223
(Top View)
Vout
1
8
NC
NC
Vin
NC
NC
GND
NC
SO−8
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
November, 2018 − Rev. 4
1
Publication Order Number:
NCV4264/D
NCV4264
IN
OUT
1.3 V
Reference
+
Error
Amp
-
Thermal
Shutdown
GND
Figure 1. Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
SOT−223
Pin No.
SO−8
Symbol
1
8
VIN
2
4
GND
Ground; substrate.
3
1
VOUT
Regulated output voltage; collector of the internal PNP pass transistor.
TAB
−
GND
Ground; substrate and best thermal connection to the die.
−
2,3,5,6,7
NC
Function
Unregulated input voltage; 4.5 V to 45 V.
Not Connected
MAXIMUM RATINGS
Rating
VIN, DC Input Voltage
VOUT, DC Voltage
Storage Temperature
Moisture Sensitivity Level
SOT−223
SO−8
Symbol
Min
Max
Unit
VIN
−42
+45
V
VOUT
−0.3
+16
V
Tstg
−55
+150
_C
MSL
3
1
−
ESD Capability, Human Body Model (Note 1)
VESDHB
4000
−
V
ESD Capability, Machine Model (Note 1)
VESDMIM
200
−
V
−
265 pk
Lead Temperature Soldering
Reflow (SMD Styles Only), Lead Free (Note 2)
Tsld
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A 114C)
ESD MM tested per AEC−Q100−003 (EIA/JESD22−A 115C)
2. Lead Free, 60 sec – 150 sec above 217_C, 40 sec max at peak.
OPERATING RANGE
Pin Symbol, Parameter
Symbol
Min
Max
Unit
VIN, DC Input Operating Voltage
VIN
4.5
+45
V
Junction Temperature Operating Range
TJ
−40
+150
_C
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2
NCV4264
THERMAL RESISTANCE
Parameter
Symbol
Min
Max
Unit
°C/W
Junction−to−Ambient
SOT−223
RqJA
−
99 (Note 3)
Junction−to−Case
SOT−223
RqJC
−
17
Junction−to−Ambient
SO−8
RqJA
−
162 (Note 3)
Junction−to−Lead2
SO−8
YJL2
−
45
°C/W
3. 1 oz., 100 mm2 copper area.
ELECTRICAL CHARACTERISTICS (VIN = 13.5 V, Tj = −40_C to +150_C, unless otherwise noted.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Voltage
5.0 V Version
VOUT
5.0 mA v IOUT v 100 mA (Note 4)
6.0 V v VIN v 28 V
4.900
5.000
5.100
V
Output Voltage
3.3 V Version
VOUT
5.0 mA v IOUT v 100 mA (Note 4)
4.5 V v VIN v 28 V
3.234
3.300
3.366
V
Line Regulation
5.0 V Version
DVOUT vs. VIN
IOUT = 5.0 mA
6.0 V v VIN v 28 V
−30
5.0
+30
mV
Line Regulation
3.3 V Version
DVOUT vs. VIN
IOUT = 5.0 mA
4.5 V v VIN v 28 V
−30
5.0
+30
mV
Load Regulation
DVOUT vs. IOUT
5.0 mA v IOUT v 100 mA (Note 4)
−40
5.0
+40
mV
Dropout Voltage
5.0 V Version
VIN−VOUT
IOUT = 100 mA (Notes 4 & 5)
−
275
500
mV
Dropout Voltage
3.3 V Version
VIN−VOUT
IOUT = 100 mA (Notes 4 & 7)
−
−
1.266
V
Iq
IOUT = 1.0 mA
−
100
400
mA
Active Ground Current
IG(ON)
IOUT = 100 mA (Note 4)
−
4
15
mA
Power Supply Rejection
PSRR
VRIPPLE = 0.5 VP−P, F = 100 Hz
−
67
−
dB
Output Capacitor for Stability
5.0 V Version
COUT
ESR
IOUT = 1.0 mA to 100 mA
(Note 4)
10
−
9.0
mF
W
Output Capacitor for Stability
3.3 V Version
COUT
ESR
IOUT = 1.0 mA to 100 mA
(Note 4)
22
−
−
−
−
16
mF
W
Current Limit
IOUT(LIM)
VOUT = 4.5 V (5.0 V Version) (Note 4)
VOUT = 3.0 V (3.3 V Version) (Note 4)
150
150
−
−
500
500
mA
Short Circuit Current Limit
IOUT(SC)
VOUT = 0 V (Note 4)
40
−
500
mA
TTSD
(Note 6)
150
−
200
_C
Quiescent Current
PROTECTION
Thermal Shutdown Threshold
4. Use pulse loading to limit power dissipation.
5. Dropout voltage = (VIN–VOUT), measured when the output voltage has dropped 100 mV relative to the nominal value obtained with
VIN = 13.5 V.
6. Not tested in production. Limits are guaranteed by design.
7. VDO = VIN − VOUT. For output voltage set to < 4.5 V, VDO will be constrained by the minimum input voltage.
www.onsemi.com
3
NCV4264
4.5−45 V
Input
II
CI1
10 mF
Vin
1
100 nF
4264
3
IQ
Vout
Output
COUT
10 mF, 5.0 V Version
22 mF, 3.3 V Version
2
RL
GND
Figure 2. Measurement Circuit
4.5−45 V
Input
Vin
1
Cin
100 nF
4264
3
Vout
2
Output
COUT
10 mF, 5.0 V Version
22 mF, 3.3 V Version
GND
Figure 3. Applications Circuit
TYPICAL CHARACTERISTIC CURVES − 5 V Version
10
0.45
Unstable Region
9
DROPOUT VOLTAGE (V)
ESR (W)
7
6
5
4
3
2
1
0
Vin = 13.5 V
Cout ≥ 10 mF
Stable Region
0
25
125°C
0.40
8
50
75
100
0.35
0.30
25°C
0.25
−40°C
0.20
0.15
0.10
0.05
125
0
150
0
50
100
150
OUTPUT CURRENT (mA)
OUTPUT LOAD (mA)
Figure 4. ESR Characterization
(5 V Version)
Figure 5. Dropout Voltage vs. Output Load
(5 V Version)
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4
200
NCV4264
14
14
12
10
8.0
6.0
RL = 50 W
4.0
RL = 100 W
2.0
0
0
10
20
30
40
6.0
4.0
2.0
0
50
100
150
Figure 6. Current Consumption vs. Input
Voltage (5 V Version)
Figure 7. Current Consumption vs. Output
Current (5 V Version)
125°C
350
25°C
5.08
−40°C
5.06
250
200
150
100
50
5.0
10
200
5.10
300
0
25°C
−40°C
8.0
0
50
125°C
10
OUTPUT CURRENT (mA)
400
0
12
INPUT VOLTAGE (V)
450
QUIESCENT CURRENT (mA)
CURRENT CONSUMPTION (mA)
16
OUTPUT VOLTAGE (V)
CURRENT CONSUMPTION (mA)
18
15
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
−50
20
0
50
100
OUTPUT LOAD (mA)
TEMPERATURE (°C)
Figure 8. Quiescent Current vs. Output Load
(5 V Version)
Figure 9. Output Voltage vs. Temperature
(5 V Version)
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5
150
NCV4264
TYPICAL CHARACTERISTIC CURVES − 5 V Version
6.0
180
5.0
140
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
160
120
100
80
TA = 25°C
60
40
0
0
10
20
3.0
2.0
1.0
TA = 125°C
20
4.0
30
40
0
50
RL = 50 W
0
2.0
4.0
6.0
8.0
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 10. Output Current vs. Input Voltage
(5 V Version)
Figure 11. Input Voltage vs. Output Voltage
(5 V Version)
0
TA = 125°C,
RL = 100
TA = −40°C, RL = 100
VIN
−0.2
TA = 25°C, RL = 100
−0.3
TA = 125°C, RL = R
−
−0.4
−0.5
+
NCV4264
3
VOUT
2
1 mF
1 mF
TA = 25°C, RL = R
−0.6
−0.7
−0.8
−40
1
TA = −40°C, RL = R
−35
−30
−25
−20
−15
−10
MEASUREMENT CIRCUIT
−5
INPUT VOLTAGE (V)
Figure 12. Reverse Voltage Characteristics
(5 V Version)
www.onsemi.com
6
RL
OUTPUT VOLTAGE (V)
−0.1
NCV4264
TYPICAL CHARACTERISTIC CURVES − 3.3 V Version
20
180
OUTPUT CURRENT (mA)
Unstable Region
ESR (W)
15
10
5
0
30
60
90
120
120
90
60
30
0
150
0
5
10
15
20
25
35
30
40
OUTPUT CURRENT (mA)
INPUT VOLTAGE (V)
Figure 13. ESR Stability vs. Output Current
(3.3 V Version)
Figure 14. Output Current vs. Input Voltage
(3.3 V Version)
10
7.0
9.0
QUIESCENT CURRENT (mA)
8.0
6.0
5.0
4.0
3.0
RL = 50 W
2.0
RL = 100 W
1.0
0
OUTPUT VOLTAGE (V)
Stable Region
0
5
10
15
20
25
30
35
40
45
125°C
7.0
25°C
6.0
5.0
−40°C
4.0
3.0
2.0
0
25
50
75
100
125
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Figure 15. Input Voltage vs. Quiescent Current
(3.3 V Version)
Figure 16. Quiescent Current vs. Output
Current (3.3 V Version)
3.344
0.19
3.333
0.18
3.322
3.311
3.300
3.289
3.278
3.267
3.256
3.245
3.234
−50
Iout = 5 mA
−25
0
25
50
75
100
125
150
45
8.0
1.0
0
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
0
Cout ≥ 22 mF
Vin = 13.5 V
150
150
0.17
0.16
0.15
0.14
0.13
0.12
Vin = 13.5 V
Iout = 5 mA
0.11
0.10
−50
−25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Output Voltage vs. Temperature
(3.3 V Version)
Figure 18. Quiescent Current vs. Temperature
(3.3 V Version)
www.onsemi.com
7
NCV4264
90
90
80
80
70
70
60
60
50
50
MAG (dB)
MAG (dB)
TYPICAL CHARACTERISTIC CURVES − 3.3 V Version
40
30
Iout = 5 mA
Vin = 13.5 V
TA = 25°C
Cout = 22 mF
20
10
100
30
Iout = 150 mA
Vin = 13.5 V
TA = 25°C
Cout = 22 mF
20
10
0
0
10
40
1k
10 k
100 k
10
Figure 19. Power Supply Rejection Ratio
(3.3 V Version)
100
1k
10 k
100 k
Figure 20. Power Supply Rejection Ratio
(3.3 V Version)
www.onsemi.com
8
NCV4264
Circuit Description
Calculating Power Dissipation in a Single Output
Linear Regulator
The NCV4264 is a precision trimmed 5.0 V and 3.3 V
fixed output regulator. The device has current capability of
100 mA, with 500 mV of dropout voltage at 100 mA of
current. The regulation is provided by a PNP pass transistor
controlled by an error amplifier with a bandgap reference.
The regulator is protected by both current limit and short
circuit protection. Thermal shutdown occurs above 150°C
to protect the IC during overloads and extreme ambient
temperatures.
The maximum power dissipation for a single output
regulator (Figure 3) is:
PD(max) + [VIN(max) * VOUT(min)] @
IQ(max) ) VI(max) @ Iq
(eq. 1)
Where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IQ(max) is the maximum output current for the
application, and Iq is the quiescent current the regulator
consumes at IQ(max).
Once the value of PD(Max) is known, the maximum
permissible value of RqJA can be calculated:
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (Vout) and drives the base of
a PNP series pass transistor by a buffer. The reference is a
bandgap design to give it a temperature−stable output.
Saturation control of the PNP is a function of the load
current and input voltage. Over saturation of the output
power device is prevented, and quiescent current in the
ground pin is minimized.
PqJA +
150 oC * TA
PD
(eq. 2)
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA’s less than the calculated value in Equation 2 will keep
the die temperature below 150°C. In some cases, none of
the packages will be sufficient to dissipate the heat
generated by the IC, and an external heat sink will be
required. The current flow and voltages are shown in the
Measurement Circuit Diagram.
Regulator Stability Considerations
The input capacitor CIN1 in Figure 2 is necessary for
compensating input line reactance. Possible oscillations
caused by input inductance and input capacitance can be
damped by using a resistor of approximately 1 W in series
with CIN2. The output or compensation capacitor, COUT
helps determine three main characteristics of a linear
regulator: startup delay, load transient response and loop
stability. The capacitor value and type should be based on
cost, availability, size and temperature constraints.
Tantalum, aluminum electrolytic, film, or ceramic
capacitors are all acceptable solutions, however, attention
must be paid to ESR constraints. The aluminum
electrolytic capacitor is the least expensive solution, but, if
the circuit operates at low temperatures (−25°C to −40°C),
both the value and ESR of the capacitor will vary
considerably. The capacitor manufacturer’s data sheet
usually provides this information. The value for the output
capacitor COUT shown in Figure 2 should work for most
applications; however, it is not necessarily the optimized
solution. Stability is guaranteed at values of CQ ≥ 10 mF,
with an ESR ≤ 9 W for the 5.0 V Version, and CQ ≥ 22 mF
with an ESR ≤ 16 W for the 3.3 V Version within the
operating temperature range. Actual limits are shown in a
graph in the Typical Performance Characteristics section.
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air. Each material in the heat flow path
between the IC and the outside environment will have a
thermal resistance. Like series electrical resistances, these
resistances are summed to determine the value of RqJA:
RqJA + RqJC ) RqCS ) RqSA
(eq. 3)
Where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heat sink thermal resistance, and
RqSA = the heat sink−to−ambient thermal resistance.
RqJA appears in the package section of the data sheet.
Like RqJA, it too is a function of package type. RqCS and
RqSA are functions of the package type, heat sink and the
interface between them. These values appear in data sheets
of heat sink manufacturers. Thermal, mounting, and heat
sinking are discussed in the ON Semiconductor application
note AN1040/D, available on the ON Semiconductor
Website.
www.onsemi.com
9
NCV4264
160
140
SO−8
qJA (°C/W)
120
100
SOT223
80
60
40
20
0
0
100
200
300
400
COPPER AREA
500
600
700
(mm2)
Figure 21.
1000
SO−8
R(t) (°C/W)
100
SOT223
10
1.0
0.1
0.000001 0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
PULSE TIME (sec)
Figure 22.
ORDERING INFORMATION
Device*
Marking
Package
Shipping†
NCV4264ST50T3G
V64_5
SOT−223
4000 / Tape & Reel
NCV4264ST33T3G
V64_3
SOT−223
4000 / Tape & Reel
NCV4264D50R2G
V42645
SO−8
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
www.onsemi.com
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
ANODE
CATHODE
NC
CATHODE
STYLE 6:
PIN 1.
2.
3.
4.
RETURN
INPUT
OUTPUT
INPUT
STYLE 7:
PIN 1.
2.
3.
4.
ANODE 1
CATHODE
ANODE 2
CATHODE
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 8:
STYLE 12:
PIN 1. INPUT
2. OUTPUT
3. NC
4. OUTPUT
CANCELLED
DATE 02 OCT 2018
STYLE 4:
PIN 1.
2.
3.
4.
SOURCE
DRAIN
GATE
DRAIN
STYLE 5:
PIN 1.
2.
3.
4.
STYLE 9:
PIN 1.
2.
3.
4.
INPUT
GROUND
LOGIC
GROUND
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
DRAIN
GATE
SOURCE
GATE
STYLE 13:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
XXXXX = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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