NCV4269
5.0 V Micropower 150 mA
LDO Linear Regulator with
DELAY, Adjustable RESET,
and Sense Output
The NCV4269 is a 5.0 V precision micropower voltage regulator
with an output current capability of 150 mA.
The output voltage is accurate within ±2.0% with a maximum
dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature
drawing only 240 mA with a 1.0 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
Microprocessor control logic includes an active reset output RO
with delay and a SI/SO monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending reset
signal. The use of the SI/SO monitor allows the microprocessor to
finish any signal processing before the reset shuts the microprocessor
down.
The active Reset circuit operates correctly at an output voltage as
low as 1.0 V. The Reset function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.
The reset threshold voltage can be decreased by the connection of an
external resistor divider to the RADJ lead. The regulator is protected
against reverse battery, short circuit, and thermal overload conditions.
The device can withstand load dump transients making it suitable for
use in automotive environments. The device has also been optimized
for EMC conditions.
•
•
•
•
•
•
•
5.0 V ± 2.0% Output
Low 240 mA Quiescent Current
Active Reset Output Low Down to VQ = 1.0 V
Adjustable Reset Threshold
150 mA Output Current Capability
Fault Protection
♦ +60 V Peak Transient Voltage
♦ −40 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload
Early Warning through SI/SO Leads
Internally Fused Leads in SO−14 and SO−20L Packages
Integrated Pullup Resistor at Logic Outputs (To Use External
Resistors, Select the NCV4279)
Very Low Dropout Voltage
Electrical Parameters Guaranteed Over Entire Temperature Range
NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2008
November, 2008 − Rev. 13
MARKING
DIAGRAMS
8
SO−8
D SUFFIX
CASE 751
8
1
1
4269
ALYW
G
8
8
1
SO−8
EXPOSED PAD
D SUFFIX
CASE 751AC
V4269
ALYW
G
1
14
SO−14
D SUFFIX
CASE 751A
14
1
NCV4269
AWLYWWG
1
20
20
Features
•
•
•
•
•
•
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1
NCV4269
AWLYYWWG
1
SO−20L
DW SUFFIX
CASE 751D
A
WL, L
YY, Y
WW, W
G, G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb Free
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Publication Order Number:
NCV4269/D
NCV4269
I
Q
Error
Amplifier
Current and
Saturation
Control
Reference
and Trim
RSO
RRO
RO
D
or
Reference
SO
RADJ
+
SI
−
GND
Figure 1. Block Diagram
PIN CONNECTIONS
I
1
8
SI
RADJ
D
GND
GND
GND
GND
RO
Q
SO
RO
RADJ
D
GND
SO−8
1
14
RADJ
D
NC
GND
GND
GND
GND
NC
NC
RO
SI
I
GND
GND
GND
Q
SO
1
SO−14
20
SI
I
NC
GND
GND
GND
GND
NC
Q
SO
SO−20L
PACKAGE PIN DESCRIPTION
Package Pin Number
SO−8
SO−8 EP
SO−14
SO−20L
Pin
Symbol
3
3
1
1
RADJ
4
4
2
2
D
5
5
3, 4, 5, 6,
10, 11, 12
4, 5, 6, 7, 14,
15, 16, 17
GND
−
−
−
3, 8, 9, 13, 18
NC
No connection to these pins from the IC.
6
6
7
10
RO
Reset Output; The Open−Collector Output has a 20 kW Pullup Resistor
to Q. Leave Open if Not Used.
7
7
8
11
SO
Sense Output; This Open−Collector Output is Internally Pulled Up by
20 kW pullup resistor to Q. If not used, keep open.
8
8
9
12
Q
5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 10 W.
1
1
13
19
I
Input; Connect to GND Directly at the IC with a Ceramic Capacitor.
2
2
14
20
SI
−
EPAD
−
−
EPAD
Function
Reset Threshold Adjust; if not used to connect to GND.
Reset Delay; To Set Time Delay, Connect to GND with Capacitor
Ground
Sense Input; If not used, Connect to Q.
Connect to ground potential or leave unconnected
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NCV4269
MAXIMUM RATINGS (TJ = −40°C to 150°C)
Parameter
Input to Regulator
Symbol
Min
Max
Unit
VI
II
−40
Internally Limited
45
Internally Limited
V
Input Transient to Regulator
VI
−
60
V
Sense Input
VSI
ISI
−40
−1
45
1
V
mA
VRADJ
IRADJ
−0.3
−10
7
10
V
mA
Reset Delay
VD
ID
−0.3
Internally Limited
7
Internally Limited
V
Ground
Iq
50
−
mA
Reset Output
VRO
IRO
−0.3
Internally Limited
7
Internally Limited
V
Sense Output
VSO
ISO
−0.3
Internally Limited
7
Internally Limited
V
Regulated Output
VQ
IQ
−0.5
−10
7.0
−
V
mA
TJ
TSTG
−
−50
150
150
°C
°C
VI
TJ
−
−40
45
150
V
°C
Reset Threshold Adjust
Junction Temperature
Storage Temperature
Input Voltage Operating Range
Junction Temperature Operating Range
LEAD TEMPERATURE SOLDERING AND MSL
Parameter
Symbol
Value
MSL, 20−Lead LS Temperature 265°C Peak (Note 3)
MSL
3
MSL, 20−Lead, LS Temperature 240°C Peak (Note 4)
MSL
1
MSL, 8−Lead, 14−Lead, LS Temperature 265°C Peak (Note 3)
MSL
1
MSL, 8−Lead EP, LS Temperature 260°C
MSL
2
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series incorporates ESD protection and exceeds the following ratings:
Human Body Model (HBM) ≤ 2.0 kV per JEDEC standard: JESD22–A114.
Machine Model (MM) ≤ 200 V per JEDEC standard: JESD22–A115.
2. Latchup Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78.
3. +5°C/−0°C, 40 Sec Max−at−Peak, 60 − 150 Sec above 217°C.
4. +5°C/−0°C, 30 Sec Max−at−Peak, 60 − 150 Sec above 183°C.
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NCV4269
THERMAL CHARACTERISTICS
Characteristic
Test Conditions (Typical Values)
Unit
Junction−to−Pin 4 ( Y − JL4, YL4)
53.8
°C/W
Junction−to−Ambient Thermal Resistance (RqJA, qJA)
170.9
°C/W
Junction−to−Pin 8 ( Y − JL8, YL8)
23.7
°C/W
Junction−to−Ambient Thermal Resistance (RqJA, qJA)
71.4
°C/W
Junction−to−Pad ( Y − JPad)
7.7
°C/W
Junction−to−Pin 4 ( Y − JL4, YL4)
18.4
°C/W
Junction−to−Ambient Thermal Resistance (RqJA, qJA)
111.6
°C/W
Junction−to−Pin 4 ( Y − JL4, YL4)
21.8
°C/W
Junction−to−Ambient Thermal Resistance (RqJA, qJA)
95.3
°C/W
SO−8 Package (Note 5)
SO−8 EP Package (Note 5)
SO−14 Package (Note 5)
SO−20 Package (Note 5)
5. 2 oz copper, 50
mm2
copper area, 1.5 mm thick FR4
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NCV4269
ELECTRICAL CHARACTERISTICS (TJ = −40°C ≤ TJ ≤ 125°C, VI = 13.5 V unless otherwise specified)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Voltage
VQ
1 mA v IQ v 100 mA 6 V v VI v 16 V
4.90
5.00
5.10
V
Current Limit
IQ
−
150
200
500
mA
Current Consumption; Iq = II – IQ
Iq
IQ = 1 mA, RO, SO High
−
190
250
mA
Current Consumption; Iq = II – IQ
Iq
IQ = 10 mA, RO, SO High
−
250
450
mA
Current Consumption; Iq = II – IQ
Iq
IQ = 50 mA, RO, SO High
−
2.0
3.0
mA
Dropout Voltage
Vdr
VI = 5 V, IQ = 100 mA
−
0.25
0.5
V
Load Regulation
DVQ
IQ = 5 mA to 100 mA
−
10
20
mV
Line Regulation
DVQ
VI = 6 V to 26 V IQ = 1 mA
−
10
30
mV
VRT
−
4.50
4.65
4.80
V
VRADJ,TH
VQ > 3.5 V
1.26
1.35
1.44
V
Reset Pullup Resistance
RSO,INT
−
10
20
40
kW
Reset Output Saturation Voltage
VRO,SAT
VQ < VRT, RRO, INT
−
0.1
0.4
V
Upper Delay Switching Threshold
VUD
−
1.4
1.8
2.2
V
Lower Delay Switching Threshold
VLD
−
0.3
0.45
0.60
V
VD,SAT
VQ < VRT
−
−
0.1
V
ID,C
VD = 1 V
3.0
6.5
9.5
mA
Delay Time L ³ H
td
CD = 100 nF
17
28
−
ms
Delay Time H ³ L
tRR
CD = 100 nF
−
1.0
−
ms
Sense Threshold High
VSI,High
−
1.24
1.31
1.38
V
Sense Threshold Low
VSI,Low
−
1.16
1.20
1.28
V
Sense Output Saturation Voltage
VSO,Low
VSI < 1.20 V; VQ > 3 V; RSO
−
0.1
0.4
V
Sense Resistor Pullup
RSO,INT
−
10
20
40
kW
ISI
−
−1.0
0.1
1.0
mA
REGULATOR
RESET GENERATOR
Reset Switching Threshold
Reset Adjust Switching Threshold
Saturation Voltage on Delay Capacitor
Charge Current
INPUT VOLTAGE SENSE
Sense Input Current
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NCV4269
II
I
CI
470 nF
1000 mF
IQ
Q
CQ
22 mF
RADJ1
ISI
VI
SI
D
GND
ID
VSI
RADJ
SO
RO
Iq
VRO
VSO
IRADJ
VQ
VRADJ
VD
CD
100 nF
RADJ2
Figure 2. Measuring Circuit
VI
t
< tRR
VQ
VRT
t
dV
I
+ D
dt
CD
VD
VUD
VLD
td
t
tRR
VRO
VRO,SAT
Power−on−Reset
t
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Figure 3. Reset Timing Diagram
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Secondary
Spike
Overload
at Output
NCV4269
Sense Input Voltage
VSI,High
VSI,Low
t
Sense Output
Voltage
High
Low
t
Figure 4. Sense Timing Diagram
TYPICAL PERFORMANCE CHARACTERISTICS
16
14
VI = 13.5 V
VD = 1.0 V
2.8
10
VUD
2.0
8
6
1.6
1.2
4
0.8
2
0.4
0
−40
VI = 13.5 V
2.4
VD, (V)
ID,C, (mA)
12
3.2
0
40
80
120
0
−40
160
VLD
0
40
80
120
TJ, (°C)
TJ, (°C)
Figure 5. Charge Current ID,C vs. Temperature TJ
Figure 6. Switching Voltage VUD and VLD vs.
Temperature TJ
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160
NCV4269
TYPICAL PERFORMANCE CHARACTERISTICS
500
1.7
1.6
400
1.5
300
VRAD,JTH, (V)
Vdr, (mV)
TJ = 125°C
TJ = 25°C
200
TJ = −40°C
1.4
1.3
1.2
1.1
100
1.0
0
0
30
60
90
120
150
0.9
−40
180
40
120
160
IQ, (mA)
Figure 7. Drop Voltage Vdr vs. Output Current IQ
Figure 8. Reset Adjust Switching Threshold,
VRADJ,TH vs. Temperature TJ
35
12
30
10
8
15
VQ (V)
20
RL = 33 W
RL = 100 W
10
0
0
10
6
RL = 50 W
4
RL = 200 W
RL = 50 W
5
2
20
30
40
0
0
50
2
4
VI, (V)
10
5.2
VI = 13.5 V
1.4
5.1
VQ, (V)
VSI, Low
4.9
1.2
4.8
1.1
4.7
0
40
VI = 13.5 V
5.0
VSI, High
1.3
1.0
−40
8
Figure 10. Output Voltage VQ vs. Input Voltage VI
1.6
1.5
6
VI, (V)
Figure 9. Current Consumption Iq vs. Input
Voltage VI
VSI, (V)
80
TJ, (°C)
25
Iq, (mA)
0
80
120
4.6
−40
160
TJ, (°C)
0
40
80
120
160
TJ, (°C)
Figure 11. Sense Threshold VSI vs. Temperature TJ
Figure 12. Output Voltage VQ vs. Temperature TJ
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NCV4269
TYPICAL PERFORMANCE CHARACTERISTICS
350
12
300
10
TJ = 25°C
200
8
Iq, (mA)
IQ, (mA)
250
TJ = 125°C
150
2
50
0
0
10
20
30
40
0
0
50
20
40
120
IQ, (mA)
Figure 13. Output Current Limit IQ vs. Input
Voltage VI
Figure 14. Current Consumption Iq vs.
Output Current IQ
7
VI = 13.5 V
TJ = 25°C
TJ = 125°C
6
1.2
5
Iq, (mA)
1.0
0.8
0.6
IQ = 100 mA
4
3
2
0.4
0.2
1
0.0
0
0
6
10
20
40
30
50
IQ = 50 mA
IQ = 10 mA
8
10
12
14
16
18
20
22
IQ, (mA)
VI, (V)
Figure 15. Current Consumption Iq vs.
Output Current IQ
Figure 16. Quiescent Current Iq vs.
Input Voltage VI
250
200
26
Stable Region for
0.1 mF to 10 mF
ESR (W)
10
IQ = 100 mA
150
24
Unstable Region
for all caps
100
TJ = 25°C
Iq, (mA)
100
80
60
VI, (V)
1.6
Iq, (mA)
6
4
100
1.4
VI = 13.5 V
TJ = 25°C
1
Unstable Region
for 0.1 mF ONLY
100
50
6
8
10
12
14
16
18
20
22
24
0.1
0
26
25
50
Stable Region for
1 mF to 10 mF
75
100
125
150
VI, (V)
OUTPUT CURRENT IN MILLIAMPS
Figure 17. Quiescent Current Iq vs. Input Voltage VI
Figure 18. Output Stability, Capacitance ESR
vs. Output Load Current
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NCV4269
TYPICAL THERMAL CHARACTERISTICS
200
180
160
qJA (°C/W)
140
120
100
80
60
40
20
0
0
100
200
300
400
500
600
700
COPPER HEAT−SPREADER AREA (mm2)
SO−8 Std Package NCV4269, 1.0 oz
SO−8 Std Package NCV4269, 2.0 oz
SO−14 w/6 Thermal Leads NCV4269, 1.0 oz
SO−14 w/6 Thermal Leads NCV4269, 2.0 oz
SO−20 w/8 Thermal Leads NCV4269, 1.0 oz
SO−20 w/8 Thermal Leads NCV4269, 2.0 oz
Figure 19. Junction−to−Ambient Thermal Resistance (qJA) vs. Heat Spreader Area
1000
R(t) (°C/W)
100
10
1
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
PULSE TIME (s)
Single Pulse (SO−8 Std Package) PCB = 50 mm2, 2.0 oz
Single Pulse (SO−8 EP Package)
Single Pulse (SO−14 w/6 Thermal Leads) PCB = 50 mm2, 2.0 oz
Single Pulse (SO−20 w/8 Thermal Leads) PCB = 50 mm2, 2.0 oz
YLA (SO−8)
YLA (SO−14)
YLA (SO−20)
Figure 20. R(t) vs. Pulse Time
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1
10
100
1000
NCV4269
APPLICATION DESCRIPTION
OUTPUT REGULATOR
If the reset adjust option is not needed, the RADJ pin
should be connected to GND causing the reset threshold to
go to its default value (typically 4.65 V).
The output is controlled by a precision trimmed reference.
The PNP output has base drive quiescent current control for
regulation while the input voltage is low, preventing over
saturation. Current limit and voltage monitors complement
the regulator design to give safe operating signals to the
processor and control circuits.
RESET DELAY (D)
The reset delay circuit provides a delay (programmable by
capacitor CD) on the reset output lead RO. The delay lead D
provides charge current ID,C (typically 6.5 mA) to the
external delay capacitor CD during the following times:
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device is
back in regulation. The delay capacitor is set to
discharge when the regulation (VRT, reset
threshold voltage) has been violated. When the
delay capacitor discharges to VLD, the reset signal
RO pulls low.
RESET OUTPUT (RO)
A reset signal, Reset Output, RO, (low voltage) is
generated as the IC powers up. After the output voltage VQ
increases above the reset threshold voltage VRT, the delay
timer D is started. When the voltage on the delay timer VD
passes VUD, the reset signal RO goes high. A discharge of
the delay timer VD is started when VQ drops and stays below
the reset threshold voltage VRT. When the voltage of the
delay timer VD drops below the lower threshold voltage VLD
the reset output voltage VRO is brought low to reset the
processor.
The reset output RO is an open collector NPN transistor
with an internal 20 kW pullup resistor connected to the
output Q, controlled by a low voltage detection circuit. The
circuit is functionally independent of the rest of the IC,
thereby guaranteeing that RO is valid for VQ as low as 1.0 V.
SETTING THE DELAY TIME
The delay time is set by the delay capacitor CD and the
charge current ID. The time is measured by the delay
capacitor voltage charging from the low level of VDSAT to
the higher level VUD. The time delay follows the equation:
td + [CD (VUD * VD, SAT)]ńID, C
Example:
Using CD = 100 nF.
Use the typical value for VD,SAT = 0.1 V.
Use the typical value for VUD = 1.8 V.
Use the typical value for Delay Charge Current ID = 6.5 mA.
RESET ADJUST (RADJ)
The reset threshold VRT can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figure 21. The resistor divider keeps the voltage
above the VRADJ,TH (typical 1.35 V) for the desired input
voltages, and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
I
CI*
Q
VDD
CQ**
10 mF
RADJ1
0.1 mF
RADJ
RADJ2
NCV4269
D
Microprocessor
VBAT
td + [100 nF (1.8 * 0.1 V)] ń 6.5 mA + 26.2 ms (eq. 3)
(eq. 1)
VRT + VRADJ, TH @ (RADJ1 ) RADJ2) ń RADJ2
RSI1
SI
RSI2
CD
SO
(eq. 2)
RO
I/O
GND
*CI required if regulator is located far from the power supply filter.
** CQ required for Stability. Cap must operate at minimum temperature expected.
Figure 21. Application Diagram
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I/O
NCV4269
SENSE INPUT (SI) / SENSE OUTPUT (SO) VOLTAGE
MONITOR
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturer’s data sheet usually provides this information.
The value for the output capacitor CQ shown in Figure 21
should work for most applications; however, it is not
necessarily the optimized solution. Stability is guaranteed at
values CQ = 10 mF and an ESR = 10 W within the operating
temperature range. Actual limits are shown in a graph in the
typical data section.
An on−chip comparator is available to provide early
warning to the microprocessor of a possible reset signal
(Figure 4). The output is from an open collector driver with
an internal 20 kW pull up resistor to output Q. The reset
signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the SO pin will
allow the microprocessor time to complete its present task
before shutting down. This function is performed by a
comparator referenced to the band gap voltage. The actual
trip point can be programmed externally using a resistor
divider to the input monitor SI (Figure 21). The values for
RSI1 and RSI2 are selected for a typical threshold of 1.20 V
on the SI Pin.
CALCULATING POWER DISSIPATION IN A SINGLE
OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 21) is:
PD(max) + [VI(max) * VQ(min)] IQ(max) ) VI(max) Iq (eq. 4)
SIGNAL OUTPUT
where:
VI(max) is the maximum input voltage,
VQ(min) is the minimum output voltage,
IQ(max) is the maximum output current for the application,
and Iq is the quiescent current the regulator consumes at
IQ(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
Figure 22 shows the SO Monitor timing waveforms as a
result of the circuit depicted in Figure 21. As the output
voltage (VQ) falls, the monitor threshold (VSI,Low), is
crossed. This causes the voltage on the SO output to go low
sending a warning signal to the microprocessor that a reset
signal may occur in a short period of time. TWARNING is the
time the microprocessor has to complete the function it is
currently working on and get ready for the reset
shutdown signal.
RqJA = (150°C – TA) / PD
(eq. 5)
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C. In some cases, none of the
packages will be sufficient to dissipate the heat generated by
the IC, and an external heatsink will be required. The current
flow
and
voltages
are
shown
in
the
Measurement Circuit Diagram.
VQ
SI
VSI,Low
VRO
HEATSINKS
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
SO
TWARNING
Figure 22. SO Warning Waveform Time Diagram
RqJA + RqJC ) RqCS ) RqSA
(eq. 6)
where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heat sink thermal resistance, and
RqSA = the heat sink−to−ambient thermal resistance.
RqJC appears in the package section of the data sheet. Like
RqJA, it too is a function of package type. RqCS and RqSA are
functions of the package type, heatsink and the interface
between them. These values appear in data sheets of
heatsink manufacturers. Thermal, mounting, and
heatsinking considerations are discussed in the
ON Semiconductor application note AN1040/D, available
on the ON Semiconductor website.
STABILITY CONSIDERATIONS
The input capacitor CI in Figure 21 is necessary for
compensating input line reactance. Possible oscillations caused
by input inductance and input capacitance can be damped by
using a resistor of approximately 1.0 W in series with CI.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay,
load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
http://onsemi.com
12
NCV4269
ORDERING INFORMATION
Package
Shipping†
NCV4269D1G
SO−8
(Pb−Free)
98 Units/Rail
NCV4269D1R2G
SO−8
(Pb−Free)
2500 Tape & Reel
NCV4269PDG
SO−8 EP
(Pb−Free)
98 Units/Rail
NCV4269PDR2G
SO−8 EP
(Pb−Free)
2500 Tape & Reel
SO−14
(Pb−Free)
55 Units/Rail
NCV4269D2R2G
SO−14
(Pb−Free)
2500 Tape & Reel
NCV4269DWG
SO−20L
(Pb−Free)
38 Units/Rail
NCV4269DWR2
SO−20L
Device
NCV4269D2G
Output Voltage
5.0 V
NCV4269DWR2G
SO−20L
(Pb−Free)
1000 Tape & Reel
†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLIC).
http://onsemi.com
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC
ISSUE E
8
1
SCALE 1:1
DATE 05 OCT 2022
GENERIC
MARKING DIAGRAM*
8
XXXXX
AYWWG
G
1
DOCUMENT NUMBER:
DESCRIPTION:
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
98AON14029D
SOIC−8 EP
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”, may
or may not be present and may be in either
location. Some products may not follow the
Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
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