NCV4276DS33

NCV4276, NCV4276A 400 mA Low−Drop Voltage Regulator The NCV4276 is a 400 mA output current integrated low dropout regulator family designed for use in harsh automotive environments. It includes wide operating temperature and input voltage ranges. The device is offered with fixed output voltage options of 1.8 V and 2.5 V with 4% output voltage accuracy while the 3.3 V, 5.0 V, and adjustable voltage versions are available either in 2% or 4% output voltage accuracy. It has a high peak input voltage tolerance and reverse input voltage protection. It also provides overcurrent protection, overtemperature protection and inhibit for control of the state of the output voltage. The NCV4276 family is available in DPAK and D2PAK surface mount packages. The output is stable over a wide output capacitance and ESR range. Features http://onsemi.com 1 5 • 2.5 V and 1.8 V ±4% Output Voltage • 3.3 V, 5.0 V, and Adjustable Voltage Version (from 2.5 V to 20 V) • • • • • DPAK 5−PIN DT SUFFIX CASE 175AA • • ±4% or ±2% Output Voltage 400 mA Output Current 500 mV (max) Dropout Voltage (5.0 V Output) Inhibit Input Very Low Current Consumption Fault Protection ♦ +45 V Peak Transient Voltage ♦ −42 V Reverse Voltage ♦ Short Circuit ♦ Thermal Overload NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes Pb−Free Packages are Available 1 5 D2PAK 5−PIN DS SUFFIX CASE 936A DEVICE MARKING INFORMATION See general marking information in the device marking section on page 20 of this data sheet. ORDERING INFORMATION See detailed ordering and shipping information in the ordering information section on page 21 of this data sheet. © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 18 1 Publication Order Number: NCV4276/D NCV4276, NCV4276A I Error Amplifier − + Current Limit and Saturation Sense Q Bandgap Reference Thermal Shutdown INH GND NC Figure 1. 4276 Block Diagram I Error Amplifier − + Current Limit and Saturation Sense Q Bandgap Reference Thermal Shutdown INH GND VA Figure 2. 4276 Adjustable Block Diagram http://onsemi.com 2 NCV4276, NCV4276A PIN FUNCTION DESCRIPTION Pin No. 1 2 3 4 5 Symbol I INH GND NC / VA Q Input; Battery Supply Input Voltage. Inhibit; Set low−to inhibit. Ground; Pin 3 internally connected to heatsink. Not connected for fixed voltage version / Voltage Adjust Input for adjustable voltage version; use an external voltage divider to set the output voltage Use 22 mF, ESR < 2.5 W at 10 kHz to ground with the 5.0 V and adjustable regulators. See Figures 3, 4, and 5. Use 10 mF, ESR < 1.8 W at 10 kHz to ground with the 3.3 V, 2.5 V, and 1.8 V regulators. See Figures 3 and 6. Description MAXIMUM RATINGS* Rating Input Voltage Input Peak Transient Voltage Inhibit INH Voltage Output Voltage Ground Current Input Voltage Operating Range ESD Susceptibility (Human Body Model) (Machine Model) (Charged Device Model) Symbol VI VI VINH VQ Iq VI − − − TJ Tstg Min −42 − −42 −1.0 − VQ + 0.5 V or 4.5 V (Note 1) 4.5 250 1.25 −40 −50 Max 45 45 45 40 100 40 − − − 150 150 Unit V V V V mA V kV V kV °C °C Junction Temperature Storage Temperature Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *During the voltage range which exceeds the maximum tested voltage of I, operation is assured, but not specified. Wider limits may apply. Thermal dissipation must be observed closely. LEAD TEMPERATURE SOLDERING REFLOW (Note 2) Lead Temperature Soldering Reflow (SMD styles only), Leaded, 60−150 s above 183, 30 s max at peak Reflow (SMD styles only), Lead Free, 60−150 s above 217, 40 s max at peak Wave Solder (through hole styles only), 12 sec max TSLD − − − 240 265 310 °C THERMAL CHARACTERISTICS Characteristic DPAK 5−PIN PACKAGE Min Pad Board (Note 3) Junction−to−Tab (psi−JLx, yJLx) Junction−to−Ambient (RqJA, qJA) D2PAK 5−PIN PACKAGE 0.4 sq. in. Spreader Board (Note 5) Junction−to−Tab (psi−JLx, yJLx) Junction−to−Ambient (RqJA, qJA) 1. 2. 3. 4. 5. 6. 3.8 74.8 1.2 sq. in. Spreader Board (Note 6) 4.0 41.6 C/W C/W 4.2 100.9 1, Pad Board (Note 4) 4.7 46.8 C/W C/W Test Conditions (Typical Value) Unit Minimum VI = 4.5 V or (VQ + 0.5 V), whichever is higher. Per IPC / JEDEC J−STD−020C. 1 oz. copper, 0.26 inch2 (168 mm2) copper area, 0.062″ thick FR4. 1 oz. copper, 1.14 inch2 (736 mm2) copper area, 0.062″ thick FR4. 1 oz. copper, 0.373 inch2 (241 mm2) copper area, 0.062″ thick FR4. 1 oz. copper, 1.222 inch2 (788 mm2) copper area, 0.062″ thick FR4. http://onsemi.com 3 NCV4276, NCV4276A ELECTRICAL CHARACTERISTICS (VI = 13.5 V; −40°C < TJ < 150°C; unless otherwise noted.) NCV4276 Characteristic OUTPUT Output Voltage, 5.0 V Version Output Voltage, 5.0 V Version Output Voltage, 3.3 V Version Output Voltage, 3.3 V Version Output Voltage, 2.5 V Version Output Voltage, 2.5 V Version Output Voltage, 1.8 V Version Output Voltage, 1.8 V Version Output Voltage, Adjustable Version Output Current Limitation Quiescent Current (Sleep Mode) Iq = II − IQ Quiescent Current, Iq = II − IQ Quiescent Current, Iq = II − IQ Quiescent Current, Iq = II − IQ Dropout Voltage, 5.0 V Version 3.3 V Version 2.5 V Version 1.8 V Version Adjustable Version Dropout Voltage (5.0 V Version) Load Regulation Line Regulation Power Supply Ripple Rejection Temperature Output Voltage Drift INHIBIT Inhibit Voltage, Output High Inhibit Voltage, Output Low (Off) Input Current THERMAL SHUTDOWN Thermal Shutdown Temperature* TSD IQ = 5.0 mA 150 − 210 150 − 210 °C *Guaranteed by design, not tested in production. 7. Measured when the output voltage VQ has dropped 100 mV from the nominal valued obtained at V = 13.5 V. VINH VINH IINH VQ w VQMIN VQ v 0.1 V VINH = 5.0 V − 0.5 5.0 2.8 1.7 10 3.5 − 20 − 0.5 5.0 2.3 2.2 10 3.5 − 20 V V mA VDR DVQ,LO DVQ PSRR dVQ/dT VQ VQ VQ VQ VQ VQ VQ VQ AVQ 5.0 mA < IQ < 400 mA, 6.0 V < VI < 28 V 5.0 mA < IQ < 200 mA, 6.0 V < VI < 40 V 5.0 mA < IQ < 400 mA, 4.5 V < VI < 28 V 5.0 mA < IQ < 200 mA, 4.5 V < VI < 40 V 5.0 mA < IQ < 400 mA, 4.5 V < VI < 28 V 5.0 mA < IQ < 200 mA, 4.5 V < VI < 40 V 5.0 mA < IQ < 400 mA, 4.5 V < VI < 28 V 5.0 mA < IQ < 200 mA, 4.5 V < VI < 40 V 5.0 mA < IQ < 400 mA VQ+1 < VI < 40 V VI > 4.5 V VQ = 90% VQTYP (VQTYP = 2.5 V for ADJ version) VINH = 0 V IQ = 1.0 mA IQ = 250 mA IQ = 400 mA IQ = 250 mA, VDR = VI − VQ VI = 5.0 V VI = 4.5 V VI = 4.5 V VI = 4.5 V VI > 4.5 V IQ = 250 mA (Note 7) IQ = 5.0 mA to 400 mA DVI = 12 V to 32 V, IQ = 5.0 mA fr = 100 Hz, Vr = 0.5 VPP − 4.8 4.8 3.168 3.168 2.4 2.4 1.728 1.728 −4% 5.0 5.0 3.3 3.3 2.5 2.5 1.8 1.8 − 5.2 5.2 3.432 3.432 2.6 2.6 1.872 1.872 +4% 4.9 4.9 3.234 3.234 − − − − −2% 5.0 5.0 3.3 3.3 − − − − − 5.1 5.1 3.366 3.366 − − − − +2% V V V V V V V V V Symbol Test Conditions Min Typ Max Min NCV4276A Typ Max Unit IQ Iq Iq Iq Iq VDR 400 − − − − 700 − 130 10 25 1100 10 220 15 35 400 − − − − 700 − 130 10 25 1100 10 200 15 35 mA mA mA mA mA − − − − − − − − − − 250 − − − 250 − 10 2.5 60 0.5 500 1.332 2.1 2.772 500 − 35 25 − − − − − − − − − − − − − − − − 250 250 3.0 4.0 54 0.5 − − − − 500 500 20 15 − − mV V V V mV mV mV mV dB mV/K http://onsemi.com 4 NCV4276, NCV4276A 5.5 − 45 V Input II CI1 1.0 mF CI2 100 nF INH IINH 2 I1 5Q CQ 22 mF 4 GND NC RL IQ Output NCV4276 3 Figure 3. Applications Circuit; Fixed Voltage Version VQ = [(R1 + R2) * Vref] / R2 Input II CI1 1.0 mF CI2 100 nF INH IINH 2 I1 NCV4276 NCV4276A 3 GND 4 VA R2 5Q CQ 22 mF IQ Output R1 RL Figure 4. Applications Circuit; Adjustable Voltage Version TYPICAL PERFORMANCE CHARACTERISTICS 1000 100 10 1 0.1 0.01 Maximum ESR for CQ = 1 mF − 22 mF Stable ESR Region 0 50 100 200 250 300 350 OUTPUT CURRENT (mA) 150 400 450 Unstable ESR Region for CQ = 1 mF − 22 mF 10.0 9.0 8.0 7.0 ESR (W) ESR (W) 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0 50 100 Stable Region 150 200 250 300 350 OUTPUT CURRENT (mA) 400 450 1.8 V Unstable Region 2.5 V CQ = 10 mF for these Output Voltages 3.3 V Figure 5. Output Stability with Output Capacitor ESR, 5.0 V and Adjustable Regulator Figure 6. Output Stability with Output Capacitor ESR, 1.8 V, 2.5 V, 3.3 V Regulators http://onsemi.com 5 NCV4276, NCV4276A TYPICAL PERFORMANCE CHARACTERISTICS − 4276 Version 5.2 VI = 13.5 V, RL = 1000 W 5.1 VQ, (V) VQ, (V) 2.00 1.95 1.90 1.85 1.80 1.75 4.9 1.70 1.65 4.8 −40 0 40 TJ (°C) 80 120 160 1.60 −40 0 40 TJ (°C) 80 120 160 VI = 13.5 V RL = 1 kW 5.0 Figure 7. Output Voltage VQ vs. Temperature TJ, 5.0 V Version 2.70 2.65 2.60 VQ, (V) VQ, (V) 2.55 2.50 2.45 2.40 2.35 2.30 −40 0 40 TJ (°C) 80 120 160 3.20 3.15 −40 3.35 3.30 3.25 VI = 13.5 V RL = 1 kW 3.45 3.40 Figure 8. Output Voltage VQ vs. Junction Temperature TJ, 1.8 V Version VI = 13.5 V RL = 1 kW 0 40 TJ (°C) 80 120 160 Figure 9. Output Voltage VQ vs. Junction Temperature TJ, 2.5 V Version 45 40 35 30 Iq, (mA) 25 20 15 10 5 0 0 10 20 VI (V) 30 40 50 Iq, (mA) TJ = 25°C RL = 20 W 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 Figure 10. Output Voltage VQ vs. Junction Temperature TJ, 3.3 V Version TJ = 25°C RL = 20 W 10 20 VI (V) 30 40 50 Figure 11. Current Consumption Iq vs. Input Voltage VI, 5.0 V Version Figure 12. Current Consumption Iq vs. Input Voltage VI, 1.8 V Version http://onsemi.com 6 NCV4276, NCV4276A TYPICAL PERFORMANCE CHARACTERISTICS − 4276 Version 10 9.0 8.0 7.0 Iq, (mA) 5.0 4.0 3.0 2.0 1.0 0 0 10 20 VI (V) 30 40 50 0 0 10 20 30 VI (V) 40 50 60 Iq, (mA) 6.0 TJ = 25°C RL = 20 W 30 25 20 15 10 5.0 TJ = 25°C RL = 20 W Figure 13. Current Consumption Iq vs. Input Voltage VI, 2.5 V Version 6 4 2 0 −2 −4 −6 −8 −50 −25 0 VI (V) 25 50 VDR, (mV) II, (mA) TJ = 25°C RL = 6.8 kW 600 500 400 300 Figure 14. Current Consumption Iq vs. Input Voltage VI, 3.3 V Version TJ = 125°C TJ = 25°C 200 100 0 0 50 100 150 200 IQ (mA) 250 300 350 400 Figure 15. High Voltage Behavior 800 700 600 500 IQ, (mA) 400 300 200 100 0 0 10 20 VI (V) 30 40 50 10 0 Iq, (mA) 40 30 20 TJ = 25°C VQ = 0 V 60 50 Figure 16. Dropout Voltage VDR vs. Output Current IQ, 5.0 V Version TJ = 25°C VI = 13.5 V 0 100 200 300 IQ (mA) 400 500 600 Figure 17. Maximum Output Current IQ vs. Input Voltage VI Figure 18. Current Consumption Iq vs. Output Current IQ (High Load) http://onsemi.com 7 NCV4276, NCV4276A TYPICAL PERFORMANCE CHARACTERISTICS − 4276 Version 1.6 1.4 1.2 1.0 Iq, (mA) 0.8 0.6 0.4 0.2 0 0 10 20 30 IQ (mA) 40 50 60 VQ, (V) TJ = 25°C VI = 13.5 V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1.0 2.0 3.0 VI (V) 4.0 5.0 6.0 TJ = 25°C RL = 20 W Figure 19. Current Consumption Iq vs. Output Current IQ (Low Load) 5.0 4.5 4.0 3.5 VQ, (V) 2.5 2.0 1.5 1.0 0.5 0 VQ, (V) 3.0 TJ = 25°C RL = 20 W 6.0 5.0 4.0 3.0 2.0 1.0 0 Figure 20. Output Voltage VQ vs. Input Voltage VI, 1.8 V Version TJ = 25°C RL = 20 W 0 1.0 2.0 3.0 VI (V) 4.0 5.0 6.0 0 1.0 2.0 3.0 VI (V) 4.0 5.0 6.0 Figure 21. Output Voltage VQ vs. Input Voltage VI, 2.5 V Version 6 5 4 VQ, (V) 3 2 1 0 II, (mA) TJ = 25°C RL = 20 W 6.0 4.0 2.0 0 −2.0 −4.0 −6.0 −8.0 0 2 4 VI (V) 6 8 10 Figure 22. Output Voltage VQ vs. Input Voltage VI, 3.3 V Version TJ = 25°C RL = 6.8 kW −25 0 VI (V) 25 50 −10 −50 Figure 23. Output Voltage VQ vs. Input Voltage VI, 5.0 V Version Figure 24. Input Current II vs. Input Voltage VI, 5.0 V Version http://onsemi.com 8 NCV4276, NCV4276A TYPICAL PERFORMANCE CHARACTERISTICS − 4276 Version 1.0 0 −1.0 −2.0 II, (mA) −3.0 −4.0 −5.0 −6.0 −7.0 −50 −25 0 VI (V) TJ = 25°C RL = 6.8 kW 25 50 II, (mA) 1.0 0 −1.0 −2.0 −3.0 −4.0 −5.0 −6.0 −7.0 −50 −25 0 VI (V) TJ = 25°C RL = 6.8 kW 25 50 Figure 25. Input Current II vs. Input Voltage VI, 1.8 V Version 6.0 4.0 2.0 0 II, (mA) −2.0 −4.0 −6.0 −8.0 −10 −50 −25 0 VI (V) Figure 26. Input Current II vs. Input Voltage VI, 2.5 V Version TJ = 25°C RL = 6.8 kW 25 50 Figure 27. Input Current II vs. Input Voltage VI, 3.3 V Version http://onsemi.com 9 NCV4276, NCV4276A TYPICAL PERFORMANCE CHARACTERISTICS − 4276A Version 5.2 VQ, OUTPUT VOLTAGE (V) VQ, OUTPUT VOLTAGE (V) VI = 13.5 V RL = 1 kW 5.1 3.45 3.40 3.35 3.30 3.25 3.20 3.15 −40 0 40 80 120 160 VI = 13.5 V RL = 1 kW 5.0 4.9 4.8 −40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 28. Output Voltage VQ vs. Junction Temperature TJ, 5.0 V Version 40 Iq, CURRENT CONSUMPTION (mA) TJ = 25°C RL = 20 W 30 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 Figure 29. Output Voltage VQ vs. Junction Temperature TJ, 3.3 V Version 20 10 0 Iq, CURRENT CONSUMPTION (mA) RL = 20 W TJ = 25°C 0 10 20 30 40 50 10 20 30 40 50 VI, INPUT VOLTAGE (V) VI, INPUT VOLTAGE (V) Figure 30. Current Consumption Iq vs. Input Voltage VI, 5.0 V Version 6.0 VQ, OUTPUT VOLTAGE (V) VQ, OUTPUT VOLTAGE (V) 5.0 4.0 3.0 2.0 1.0 0 RL = 20 W TJ = 25°C 6.0 5.0 4.0 3.0 2.0 1.0 0 0 Figure 31. Current Consumption Iq vs. Input Voltage VI, 3.3 V Version TJ = 25°C RL = 20 W 0 2.0 4.0 6.0 8.0 10 1.0 2.0 3.0 4.0 5.0 6.0 VI, INPUT VOLTAGE (V) VI, INPUT VOLTAGE (V) Figure 33. Low Voltage Behavior, 5.0 V Version Figure 32. Low Voltage Behavior, 3.3 V Version http://onsemi.com 10 NCV4276, NCV4276A TYPICAL PERFORMANCE CHARACTERISTICS − 4276A Version 6.0 4.0 2.0 II (mA) II (mA) 0 −2.0 −4.0 −6.0 −8.0 −10 −50 −25 0 VI, INPUT VOLTAGE (V) 25 50 −8.0 −10 −50 RL = 6.8 kW TJ = 25°C −2.0 −4.0 −6.0 RL = 6.8 kW TJ = 25°C −25 0 VI, INPUT VOLTAGE (V) 25 50 2.0 0 Figure 34. Input Current vs. Input Voltage, 5.0 V Version 600 VDR, DROP VOLTAGE (mV) 500 TJ = 125°C 400 300 TJ = 25°C 200 100 0 IQ, OUTPUT CURRENT (mA) 800 Figure 35. Input Current II vs. Input Voltage VI, 3.3 V Version TJ = 25°C VQ = 0 V 600 400 200 0 100 200 300 400 0 0 10 20 30 40 50 IQ, OUTPUT CURRENT (mA) VI, INPUT VOLTAGE (V) Figure 36. Dropout Voltage VDR vs. Output Current IQ 60 Iq, CURRENT CONSUMPTION (mA) Iq, CURRENT CONSUMPTION (mA) 50 40 30 20 10 0 VI = 13.5 V TJ = 25°C 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 Figure 37. Maximum Output Current IQ vs. Input Voltage VI VI = 13.5 V 0 100 200 300 400 500 600 10 20 30 40 50 60 IQ, OUTPUT CURRENT (mA) IQ, OUTPUT CURRENT (mA) Figure 38. Current Consumption Iq vs. Output Current IQ (High Load) Figure 39. Current Consumption Iq vs. Output Current IQ (Low Load) http://onsemi.com 11 NCV4276, NCV4276A TYPICAL PERFORMANCE CHARACTERISTICS − Adjustable Version 2.55 2.54 2.53 2.52 VQ (V) 2.51 2.50 2.49 2.48 2.47 2.46 2.45 −40 0 40 TJ (°C) 80 120 160 Iq (mA) VI = 13.5 V, RL = 1 kW 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 10 20 VI (V) 30 40 50 TJ = 25°C RL = 20 W Figure 40. Output Voltage VQ vs. Junction Temperature TJ, Adjustable Version 4 3.5 3 II (mA) VQ (V) 2.5 2 1.5 1 0.5 0 0 2 4 VI (V) 6 8 10 TJ = 25°C RL = 20 W 2 0 −2 −4 −6 −8 −10 −12 −14 Figure 41. Current Consumption Iq vs. Input Voltage VI, Adjustable Version −16 −18 −50 TJ = 25°C RL = 6.8 kW −25 0 VI (V) 25 50 Figure 42. Low Voltage Behavior, Adjustable Version Figure 43. High Voltage Behavior, Adjustable Version http://onsemi.com 12 NCV4276, NCV4276A TYPICAL PERFORMANCE CHARACTERISTICS − Adjustable Version 600 500 400 300 200 100 0 0 50 100 150 200 IQ (mA) 250 300 350 400 TJ = 125°C 800 700 600 VDR (mV) IQ (mA) 500 400 300 200 100 0 0 10 20 VI (V) 30 40 50 TJ = 25°C VQ = 0 V TJ = 25°C Figure 44. Dropout Voltage VDR vs. Output Current IQ, Regulator Set at 5.0 V, Adjustable Version 60 50 40 IQ (mA) 30 20 10 0 0 100 200 300 IQ (mA) 400 500 600 TJ = 25°C VI = 13.5 V Iq (mA) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 Figure 45. Maximum Output Current IQ vs. Input Voltage VI, Adjustable Version TJ = 25°C VI = 13.5 V 10 20 30 IQ (mA) 40 50 60 Figure 46. Current Consumption Iq vs. Output Current IQ (High Load), Adjustable Version Figure 47. Current Consumption Iq vs. Output Current IQ (Low Load), Adjustable Version http://onsemi.com 13 NCV4276, NCV4276A Circuit Description The NCV4276 is an integrated low dropout regulator that provides a regulated voltage at 400 mA to the output. It is enabled with an input to the inhibit pin. The regulator voltage is provided by a PNP pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible dropout voltage. The output current capability is 400 mA, and the base drive quiescent current is controlled to prevent oversaturation when the input voltage is low or when the output is overloaded. The regulator is protected by both current limit and thermal shutdown. Thermal shutdown occurs above 150°C to protect the IC during overloads and extreme ambient temperatures. Regulator The error amplifier compares the reference voltage to a sample of the output voltage (VQ) and drives the base of a PNP series pass transistor via a buffer. The reference is a bandgap design to give it a temperature−stable output. Saturation control of the PNP is a function of the load current and input voltage. Oversaturation of the output power device is prevented, and quiescent current in the ground pin is minimized. See Figure 5, Test Circuit, for circuit element nomenclature illustration. Regulator Stability Considerations The input capacitors (CI1 and CI2) are necessary to stabilize the input impedance to avoid voltage line influences. Using a resistor of approximately 1.0 W in series with CI2 can stop potential oscillations caused by stray inductance and capacitance. The output capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet usually provides this information. The value for the output capacitor CQ, shown in Figure 3, should work for most applications; however, it is not necessarily the optimized solution. Stability is guaranteed for CQ w 22 mF and an ESR v 2.5 W for the 5.0 V and Adjustable regulator and CQ w 10 mF and an ESR v 1.8 W for the 1.8 V, 2.5 V, and 3.3 V regulators. See Figures 5 and 6 for output stability at various load and capacitive ESR conditions. Inhibit Input The inhibit pin is used to turn the regulator on or off. By holding the pin down to a voltage less than 0.5 V, the output of the regulator will be turned off. When the voltage on the Inhibit pin is greater than 3.5 V, the output of the regulator will be enabled to power its output to the regulated output voltage. The inhibit pin may be connected directly to the input pin to give constant enable to the output regulator. Setting the Output Voltage (Adjustable Version) The output voltage range of the adjustable version can be set between 2.5 V and 20 V (Figure ). This is accomplished with an external resistor divider feeding back the voltage to the IC back to the error amplifier by the voltage adjust pin VA. The internal reference voltage is set to a temperature stable reference of 2.5 V. The output voltage is calculated from the following formula. Ignoring the bias current into the VA pin: VQ + [(R1 ) R2) * Vref] R2 Use R2 < 50 k to avoid significant voltage output errors due to VA bias current. Connecting VA directly to Q without R1 and R2 creates an output voltage of 2.5 V. Designers should consider the tolerance of R1 and R2 during the design phase. The input voltage range for operation (pin 1) of the adjustable version is between (VQ + 0.5 V) and 40 V. Internal bias requirements dictate a minimum input voltage of 4.5 V. The dropout voltage for output voltages less than 4.0 V is (4.5 V − VQ). http://onsemi.com 14 NCV4276, NCV4276A Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 48) is: PD(max) + [VI(max) * VQ(min)] IQ(max) ) VI(max)Iq (1) where is the maximum input voltage, is the minimum output voltage, is the maximum output current for the application, Iq is the quiescent current the regulator consumes at IQ(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: T RqJA + 150°C * A PD (2) Heatsinks A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA: RqJA + RqJC ) RqCS ) RqSA (3) VI(max) VQ(min) IQ(max) where RqJC is the junction−to−case thermal resistance, RqCS is the case−to−heatsink thermal resistance, RqSA is the heatsink−to−ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in data sheets of heatsink manufacturers. Thermal, mounting, and heatsinking considerations are discussed in the ON Semiconductor application note AN1040/D. The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA less than the calculated value in Equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. II VI SMART REGULATOR® IQ VQ } Control Features Iq Figure 48. Single Output Regulator with Key Performance Parameters Labeled http://onsemi.com 15 NCV4276, NCV4276A Thermal Model A discussion of thermal modeling is in the ON Semiconductor web site: http://www.onsemi.com/pub/collateral/BR1487−D.PDF. Table 1. DPAK 5−Lead Thermal RC Network Models Drain Copper Area (1 oz thick) (SPICE Deck Format) 168 C_C1 C_C2 C_C3 C_C4 C_C5 C_C6 C_C7 C_C8 C_C9 C_C10 Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 GND GND GND GND GND GND GND GND GND GND 168 mm2 736 mm2 168 mm2 736 mm2 Cauer Network mm2 736 mm2 Units W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C R’s C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W 0.0123 0.0585 0.0304 0.3997 3.115 3.571 12.851 35.471 46.741 R’s 0.0123 0.0585 0.0287 0.3772 2.68 1.38 5.92 7.39 28.94 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Tau 1.36E−08 7.41E−07 1.04E−05 3.91E−05 1.80E−03 3.77E−01 3.79E+00 2.65E+01 8.71E+01 Foster Network Tau 1.361E−08 7.411E−07 1.029E−05 3.737E−05 1.376E−03 2.851E−02 9.475E−01 1.173E+01 8.59E+01 Units sec sec sec sec sec sec sec sec sec sec 1.00E−06 1.00E−05 6.00E−05 1.00E−04 4.36E−04 6.77E−02 1.51E−01 4.80E−01 3.740 10.322 168 mm2 1.00E−06 1.00E−05 6.00E−05 1.00E−04 3.64E−04 1.92E−02 1.27E−01 1.018 2.955 0.438 736 mm2 R_R1 R_R2 R_R3 R_R4 R_R5 R_R6 R_R7 R_R8 R_R9 R_R10 NOTE: Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 node1 node2 node3 node4 node5 node6 node7 node8 node9 GND 0.015 0.08 0.4 0.2 2.97519 8.2971 25.9805 46.5192 17.7808 0.1 0.015 0.08 0.4 0.2 2.6171 1.6778 7.4246 14.9320 19.2560 0.1758 Bold face items represent the package without the external thermal system. Junction R1 R2 R3 Rn C1 C2 C3 Cn Ambient (thermal ground) Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values. Figure 49. Grounded Capacitor Thermal Network (“Cauer” Ladder) Junction R1 R2 R3 Rn C1 C2 C3 Cn Each rung is exactly characterized by its RC−product time constant; amplitudes are the resistances. Ambient (thermal ground) Figure 50. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder) http://onsemi.com 16 NCV4276, NCV4276A Table 2. D2PAK 5−Lead Thermal RC Network Models Drain Copper Area (1 oz thick) (SPICE Deck Format) 241 mm2 788 mm2 241 mm2 788 mm2 Cauer Network 241 mm2 C_C1 C_C2 C_C3 C_C4 C_C5 C_C6 C_C7 C_C8 C_C9 C_C10 Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 GND GND GND GND GND GND GND GND GND GND 1.00E−06 1.00E−05 6.00E−05 1.00E−04 2.82E−04 5.58E−03 4.25E−01 9.22E−01 1.73 7.12 241 mm2 R_R1 R_R2 R_R3 R_R4 R_R5 R_R6 R_R7 R_R8 R_R9 R_R10 NOTE: Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 node1 node2 node3 node4 node5 node6 node7 node8 node9 GND 0.015 0.08 0.4 0.2 1.85638 1.23672 9.81541 33.1868 27.0263 1.13944 653 mm2 1.00E−06 1.00E−05 6.00E−05 1.00E−04 2.87E−04 5.95E−03 4.61E−01 2.05 4.88 1.31 653 mm2 0.0150 0.0800 0.4000 0.2000 1.8839 1.2272 5.3383 18.9591 13.3369 0.1191 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Units W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C R’s 0.0123 0.0585 0.0257 0.3413 1.77 1.54 4.13 6.27 60.80 R’s 0.0123 0.0585 0.0260 0.3438 1.81 1.52 3.46 5.03 29.30 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Tau 1.361E−08 7.411E−07 1.005E−05 3.460E−05 7.868E−04 7.431E−03 2.786E+00 2.014E+01 1.134E+02 Foster Network Tau 1.361E−08 7.411E−07 1.007E−05 3.480E−05 8.107E−04 7.830E−03 2.012E+00 2.601E+01 1.218E+02 Units sec sec sec sec sec sec sec sec sec sec Bold face items represent the package without the external thermal system. The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: R(t) + S Ri 1−e−t taui i+1 n http://onsemi.com 17 NCV4276, NCV4276A 110 100 90 qJA (C°/W) qJA (C°/W) 80 70 60 50 40 30 150 200 250 300 350 400 450 500 550 600 650 700 750 COPPER AREA (mm2) 2 oz 1 oz 110 100 90 80 70 60 50 40 30 150 200 250 300 350 400 450 500 550 600 650 700 750 COPPER AREA (mm2) 2 oz 1 oz Figure 51. qJA vs. Copper Spreader Area, DPAK 5−Lead Figure 52. qJA vs. Copper Spreader Area, D2PAK 5−Lead 100 Cu Area 167 mm2 10 R(t) C°/W Cu Area 736 mm2 1.0 sqrt(t) 0.1 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 TIME (sec) 0.1 1.0 10 100 1000 Figure 53. Single−Pulse Heating Curves, DPAK 5−Lead 100 Cu Area 167 mm2 10 R(t) C°/W Cu Area 736 mm2 1.0 0.1 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 TIME (sec) 0.1 1.0 10 100 1000 Figure 54. Single−Pulse Heating Curves, D2PAK 5−Lead http://onsemi.com 18 NCV4276, NCV4276A 100 50% Duty Cycle RqJA 736 mm2 C°/W 10 20% 10% 5% 2% 1% 1.0 0.1 Non−normalized Response 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 PULSE WIDTH (sec) Figure 55. Duty Cycle for 1, Spreader Boards, DPAK 5−Lead 100 50% Duty Cycle RqJA 788 mm2 C°/W 10 20% 10% 5% 2% 1% 1.0 0.1 Non−normalized Response 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 PULSE WIDTH (sec) Figure 56. Duty Cycle for 1, Spreader Boards, D2PAK 5−Lead http://onsemi.com 19 NCV4276, NCV4276A MARKING DIAGRAMS 76AXXG ALYWW NC V4276A−XX AWLYWWG 1 NCV4276A D2PAK 5−PIN DS SUFFIX CASE 936A 4276XG ALYWW NC V4276−XX AWLYWWG 1 NCV4276A DPAK 5−PIN DT SUFFIX CASE 175AA 1 1 NCV4276 NCV4276 D2PAK 5−PIN DS SUFFIX CASE 936A DPAK 5−PIN DT SUFFIX CASE 175AA *Tab is connected to Pin 3 on all packages. A WL, L Y WW G x, xx = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Device = Voltage Ratings as indicated below A−Version DPAK XX = AJ (Adj. Voltage) XX = 50 (5.0 V) Non−A−Version DPAK X = V (Adj. Voltage) X = 5 (5.0 V) X = 3 (3.3 V) D2PAK XX = AJ (Adj. Voltage) XX = 50 (5.0 V) XX = 33 (3.3 V) XX = 25 (2.5 V) XX = 18 (1.8 V) D2PAK XX = AJ (Adj. Voltage) XX = 50 (5.0 V) http://onsemi.com 20 NCV4276, NCV4276A ORDERING INFORMATION Device NCV4276DT50RK NCV4276DT50RKG NCV4276DS50 NCV4276DS50G NCV4276DS50R4 NCV4276DS50R4G NCV4276DT33RK NCV4276DT33RKG NCV4276DS33 NCV4276DS33G NCV4276DS33R4 NCV4276DS33R4G NCV4276DS25 NCV4276DS25G NCV4276DS25R4 NCV4276DS25R4G NCV4276DS18 NCV4276DS18G NCV4276DS18R4 NCV4276DS18R4G NCV4276DTADJRKG NCV4276DSADJG NCV4276DSADJR4G NCV4276ADT33RKG NCV4276ADT50RKG NCV4276ADS50G NCV4276ADS50R4G NCV4276ADTADJRKG NCV4276ADSADJG NCV4276ADSADJR4G Adjustable 2% 5.0 V 3.3 V Adjustable 1.8 V 2.5 V 4% 3.3 V 5.0 V Output Voltage Accuracy Output Voltage Package DPAK, 5−Pin DPAK, 5−Pin (Pb−Free) D2PAK, 5−Pin D2PAK, 5−Pin (Pb−Free) D2PAK, 5−Pin D2PAK, 5−Pin (Pb−Free) DPAK, 5−Pin DPAK, 5−Pin (Pb−Free) D2PAK, 5−Pin D2PAK, 5−Pin (Pb−Free) Shipping† 2500 / Tape & Reel 2500 / Tape & Reel 50 Units / Rail 50 Units / Rail 800 / Tape & Reel 800 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel 50 Units / Rail 50 Units / Rail 800 / Tape & Reel 800 / Tape & Reel 50 Units / Rail 50 Units / Rail 800 / Tape & Reel 800 / Tape & Reel 50 Units / Rail 50 Units / Rail 800 / Tape & Reel 800 / Tape & Reel 2500 / Tape & Reel 50 Units / Rail 800 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel 50 Units / Rail 800 / Tape & Reel 2500 / Tape & Reel 50 Units / Rail 800 / Tape & Reel D2PAK, 5−Pin D2PAK, 5−Pin (Pb−Free) D2PAK, 5−Pin D2PAK, 5−Pin (Pb−Free) D2PAK, 5−Pin D2PAK, 5−Pin (Pb−Free) D2PAK, 5−Pin D2PAK, 5−Pin (Pb−Free) D2PAK, 5−Pin D2PAK, 5−Pin (Pb−Free) DPAK, 5−Pin (Pb−Free) D2PAK, 5−Pin (Pb−Free) DPAK, 5−Pin (Pb−Free) DPAK, 5−Pin (Pb−Free) D2PAK, 5−Pin (Pb−Free) DPAK, 5−Pin (Pb−Free) D2PAK, 5−Pin (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 21 NCV4276, NCV4276A PACKAGE DIMENSIONS DPAK 5, CENTER LEAD CROP DT SUFFIX CASE 175AA−01 ISSUE A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.020 0.028 0.018 0.023 0.024 0.032 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.045 BSC 0.170 0.190 0.185 0.210 0.025 0.040 0.020 −−− 0.035 0.050 0.155 0.170 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.51 0.71 0.46 0.58 0.61 0.81 4.56 BSC 0.87 1.01 0.46 0.58 2.60 2.89 1.14 BSC 4.32 4.83 4.70 5.33 0.63 1.01 0.51 −−− 0.89 1.27 3.93 4.32 −T− B V R C E SEATING PLANE R1 Z U S A 1234 5 K F L D G 5 PL J H 0.13 (0.005) M DIM A B C D E F G H J K L R R1 S U V Z T SOLDERING FOOTPRINT* 6.4 0.252 2.2 0.086 5.8 0.228 0.34 5.36 0.013 0.217 10.6 0.417 0.8 0.031 SCALE 4:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 22 NCV4276, NCV4276A PACKAGE DIMENSIONS D2PAK 5 LEAD DS SUFFIX CASE 936A−02 ISSUE C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A AND K. 4. DIMENSIONS U AND V ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 6. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAXIMUM. INCHES MIN MAX 0.386 0.403 0.356 0.368 0.170 0.180 0.026 0.036 0.045 0.055 0.067 BSC 0.539 0.579 0.050 REF 0.000 0.010 0.088 0.102 0.018 0.026 0.058 0.078 5 _ REF 0.116 REF 0.200 MIN 0.250 MIN MILLIMETERS MIN MAX 9.804 10.236 9.042 9.347 4.318 4.572 0.660 0.914 1.143 1.397 1.702 BSC 13.691 14.707 1.270 REF 0.000 0.254 2.235 2.591 0.457 0.660 1.473 1.981 5 _ REF 2.946 REF 5.080 MIN 6.350 MIN −T− A K B 12345 OPTIONAL CHAMFER TERMINAL 6 E V U S H M N G R L D 0.010 (0.254) M T P C SOLDERING FOOTPRINT* 8.38 0.33 1.702 0.067 10.66 0.42 DIM A B C D E G H K L M N P R S U V 16.02 0.63 3.05 0.12 1.016 0.04 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 23 NCV4276/D