NCV4276DS50R4

NCV4276 Low−Drop Voltage Regulator This industry standard linear regulator has the capability to drive loads up to 400 mA at 5.0, 3.3, 2.5 and 1.8 V. Package options include DPAK and D2PAK. This device is pin−for−pin compatible with the Infineon part number TLE4276. Features http://onsemi.com MARKING DIAGRAMS DPAK 5−PIN DT SUFFIX CASE 175AA 4276 ALYWW x • • • • • • 5.0, 3.3, 2.5 and 1.8 V; ±4%; Output Voltage at 400 mA 500 mV (max) Dropout Voltage Inhibit Input Very Low Current Consumption Fault Protection ♦ +45 V Peak Transient Voltage ♦ −42 V Reverse Voltage ♦ Short Circuit ♦ Thermal Overload NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes 1 5 1 1 5 D2PAK 5−PIN DS SUFFIX CASE 936A NCV4276 AWLYYWW I Error Amplifier − + Current Limit and Saturation Sense Q Pin 1. I 1 2. INH Tab, 3. GND* 4. NC 5. Q * Tab is connected to Pin 3 on all packages. Bandgap Reference Thermal Shutdown A WL, L YY, Y WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the ordering information section on page 9 of this data sheet. INH GND NC Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2004 1 August, 2004 − Rev. 7 Publication Order Number: NCV4276/D NCV4276 PIN FUNCTION DESCRIPTION Pin No. 1 2 3 4 5 Symbol I Input; Battery Supply Input Voltage. Inhibit; Set low−to inhibit. Description ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ Ñ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ Ñ Ñ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ Ñ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ Ñ ÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ Ñ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ Ñ INH GND NC Q Ground; Pin 3 internally connected to heatsink. Not Connected for fixed voltage versions. Output; ±4.0%, 400 mA output. Use 22 mF, ESR < 2.0 W at 10 kHz to ground. See Figure 3. MAXIMUM RATINGS† Input [I (DC)] Rating Min Max 45 − 45 40 100 40 − − 150 150 Unit V V V V mA V kV V °C °C °C °C −42 − −42 −1.0 − Q + 0.5 4.0 200 −40 −50 Reflow (SMD styles only) Note 1 Wave Solder (through hole styles only) Note 2 − − Input [I (Peak Transient Voltage)] Inhibit INH Output (Q) Ground (GND) Operating Range (I) ESD Susceptibility (Human Body Model) (Machine Model) Junction Temperature Storage Temperature Lead Temperature Soldering 240 Peak (Note 3) 260 Peak Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. THERMAL CHARACTERISTICS Parameter DPAK 5−PIN PACKAGE Min Pad Board (Note 4) Junction−to−T (psi−JLx, yJLx) ab Junction−to−Ambient (RqJA, qJA) D2PAK 5−PIN PACKAGE 0.4 sq. in. Spreader Board (Note 6) Junction−to−T (psi−JLx, yJLx) ab Junction−to−Ambient (RqJA, qJA) 3.8 74.8 1.2 sq. in. Spreader Board (Note 7) 4.0 41.6 C/W C/W 4.2 100.9 1″ Pad Board (Note 5) 4.7 46.8 C/W C/W Test Conditions (Typical Value) Unit 1. 10 seconds max. 2. 60 seconds max above 183°C. 3. −5°C/+0°C allowable conditions. 4. 1 oz. copper, 0.26 inch2 (168 mm2) copper area, 0.62″ thick FR4. 5. 1 oz. copper, 1.14 inch2 (736 mm2) copper area, 0.62″ thick FR4. 6. 1 oz. copper, 0.373 inch2 (241 mm2) copper area, 0.62″ thick FR4. 7. 1 oz. copper, 1.222 inch2 (788 mm2) copper area, 0.62″ thick FR4. †During the voltage range which exceeds the maximum tested voltage of I, operation is assured, but not specified. Wider limits may apply. Thermal dissipation must be observed closely. http://onsemi.com 2 NCV4276 ELECTRICAL CHARACTERISTICS (VI = 13.5 V; −40°C < TJ < 150°C; unless otherwise noted) Characteristic Output Output Voltage, 5.0 V Version Output Voltage, 5.0 V Version Output Voltage, 3.3 V Version Output Voltage, 3.3 V Version Output Voltage, 2.5 V Version Output Voltage, 2.5 V Version Output Voltage, 1.8 V Version Output Voltage, 1.8 V Version Output Current Limitation Output Current Limitation (Sleep Mode) Iq = II − IQ Quiescent Current, Iq = II − IQ Quiescent Current, Iq = II − IQ Quiescent Current, Iq = II − IQ Dropout Voltage, 5.0 V Version 3.3 V Version 2.5 V Version 1.8 V Version Load Regulation Line Regulation Power Supply Ripple Rejection Temperature Output Voltage Drift Inhibit Inhibit On Voltage Inhibit Off Voltage Input Current VQ w 4.8 V VQ v 0.1 V VINH = 5.0 V II Input CI1 100 mF CI2 100 nF INH IINH 2 − 0.5 5.0 2.8 1.7 10 3.5 − 20 Output V V mA 5.0 mA < IQ < 400 mA, 6.0 V < VI < 28 V 5.0 mA < IQ < 200 mA, 6.0 V < VI < 40 V 5.0 mA < IQ < 400 mA, 6.0 V < VI < 28 V 5.0 mA < IQ < 200 mA, 6.0 V < VI < 40 V 5.0 mA < IQ < 400 mA, 6.0 V < VI < 28 V 5.0 mA < IQ < 200 mA, 6.0 V < VI < 40 V 5.0 mA < IQ < 400 mA, 6.0 V < VI < 28 V 5.0 mA < IQ < 200 mA, 6.0 V < VI < 40 V − INH = 0 V, TJ < 100°C IQ = 1.0 mA IQ = 250 mA IQ = 400 mA IQ = 250 mA, Vdr = VI − VQ 4.8 4.8 3.168 3.168 2.4 2.4 1.728 1.728 400 − − − − − − − − −35 −25 − − 5.0 5.0 3.300 3.300 2.5 2.5 1.800 1.800 630 0.5 130 10 20 250 − − − 10 2.5 60 0.5 5.2 5.2 3.432 3.432 2.6 2.6 1.872 1.872 1100 10 220 15 35 500 1.2 2.0 2.7 35 25 − − V V V V V V V V mA mA mA mA mA mV V V V mV mV dB mV/K Test Conditions Min Typ Max Unit IQ = 5.0 mA to 400 mA ∆V = 12 V to 32 V, IQ = 5.0 mA fr = 100 Hz, Vr = 0.5 Vpp − I1 5Q CQ NCV4276 3 GND 4 NC IQ RL Figure 2. Measuring Circuit http://onsemi.com 3 NCV4276 TYPICAL PERFORMANCE CHARACTERISTICS 1000 Unstable ESR Region for CVout = 1 mF − 22 mF 100 ESR (W) 10 1 Maximum ESR for CVout = 1 mF − 22 mF Stable ESR Region 0.01 0 50 100 150 200 250 300 350 400 450 OUTPUT CURRENT (mA) 0.1 Figure 3. Output Stability with Output Capacitor ESR Circuit Description The error amplifier compares a temperature−stable reference voltage to a voltage that is proportional to the output voltage (Q) (generated from a resistor divider) and drives the base of a series transistor via a buffer. Saturation control as a function of the load current prevents any oversaturation of the output power device preventing excessive substrate current (quiescent current). Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 4) is: PD(max) + [VI(max) * VQ(min)] IQ(max) ) VI(max)Iq (1) II VI SMART REGULATOR® IQ VQ } Control Features Iq Figure 4. Single Output Regulator with Key Performance Parameters Labeled where VI(max) VQ(min) IQ(max) Iq is the maximum input voltage, is the minimum output voltage, is the maximum output current for the application, is the quiescent current the regulator consumes at IQ(max). Heat Sinks A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA: RqJA + RqJC ) RqCS ) RqSA (3) where RqJC is the junction−to−case thermal resistance, RqCS is the case−to−heatsink thermal resistance, RqSA is the heatsink−to−ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in data sheets of heat sink manufacturers. Thermal, mounting, and heatsinking considerations are discussed in the ON Semiconductor application note AN1040/D. Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: T RqJA + 150°C * A PD (2) The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA less than the calculated value in Equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. http://onsemi.com 4 NCV4276 Table 1. DPAK 5−Lead Thermal RC Network Models Drain Copper Area (1 oz thick) (SPICE Deck Format) 168 C_C1 C_C2 C_C3 C_C4 C_C5 C_C6 C_C7 C_C8 C_C9 C_C10 Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd 168 mm2 mm2 736 mm2 mm2 168 mm2 736 mm2 Cauer Network 736 Units W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C R’s C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W 0.0123 0.0585 0.0304 0.3997 3.115 3.571 12.851 35.471 46.741 R’s 0.0123 0.0585 0.0287 0.3772 2.68 1.38 5.92 7.39 28.94 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Tau 1.36E−08 7.41E−07 1.04E−05 3.91E−05 1.80E−03 3.77E−01 3.79E+00 2.65E+01 8.71E+01 Foster Network Tau 1.361E−08 7.411E−07 1.029E−05 3.737E−05 1.376E−03 2.851E−02 9.475E−01 1.173E+01 8.59E+01 Units sec sec sec sec sec sec sec sec sec sec 1.00E−06 1.00E−05 6.00E−05 1.00E−04 4.36E−04 6.77E−02 1.51E−01 4.80E−01 3.740 10.322 168 mm2 1.00E−06 1.00E−05 6.00E−05 1.00E−04 3.64E−04 1.92E−02 1.27E−01 1.018 2.955 0.438 736 mm2 R_R1 R_R2 R_R3 R_R4 R_R5 R_R6 R_R7 R_R8 R_R9 R_R10 NOTE: Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 node1 node2 node3 node4 node5 node6 node7 node8 node9 Gnd 0.015 0.08 0.4 0.2 2.97519 8.2971 25.9805 46.5192 17.7808 0.1 0.015 0.08 0.4 0.2 2.6171 1.6778 7.4246 14.9320 19.2560 0.1758 Bold face items represent the package without the external thermal system. http://onsemi.com 5 NCV4276 Table 2. D2PAK 5−Lead Thermal RC Network Models Drain Copper Area (1 oz thick) (SPICE Deck Format) 241 C_C1 C_C2 C_C3 C_C4 C_C5 C_C6 C_C7 C_C8 C_C9 C_C10 Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd 241 mm2 mm2 788 mm2 mm2 241 mm2 788 mm2 Cauer Network 653 Units W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C R’s C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W 0.0123 0.0585 0.0257 0.3413 1.77 1.54 4.13 6.27 60.80 R’s 0.0123 0.0585 0.0260 0.3438 1.81 1.52 3.46 5.03 29.30 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Tau 1.361E−08 7.411E−07 1.005E−05 3.460E−05 7.868E−04 7.431E−03 2.786E+00 2.014E+01 1.134E+02 Foster Network Tau 1.361E−08 7.411E−07 1.007E−05 3.480E−05 8.107E−04 7.830E−03 2.012E+00 2.601E+01 1.218E+02 Units sec sec sec sec sec sec sec sec sec sec 1.00E−06 1.00E−05 6.00E−05 1.00E−04 2.82E−04 5.58E−03 4.25E−01 9.22E−01 1.73 7.12 241 mm2 1.00E−06 1.00E−05 6.00E−05 1.00E−04 2.87E−04 5.95E−03 4.61E−01 2.05 4.88 1.31 653 mm2 R_R1 R_R2 R_R3 R_R4 R_R5 R_R6 R_R7 R_R8 R_R9 R_R10 NOTE: Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 node1 node2 node3 node4 node5 node6 node7 node8 node9 gnd 0.015 0.08 0.4 0.2 1.85638 1.23672 9.81541 33.1868 27.0263 1.13944 0.0150 0.0800 0.4000 0.2000 1.8839 1.2272 5.3383 18.9591 13.3369 0.1191 Bold face items represent the package without the external thermal system. The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: R(t) + S Ri 1−e−t taui i+1 n http://onsemi.com 6 NCV4276 110 100 90 qJA (C°/W) qJA (C°/W) 80 70 60 50 40 30 150 200 250 300 350 400 450 500 550 600 650 700 750 COPPER AREA (mm2) 2 oz 1 oz 110 100 90 80 70 60 50 40 30 150 200 250 300 350 400 450 500 550 600 650 700 750 COPPER AREA (mm2) 2 oz 1 oz Figure 5. qJA vs. Copper Spreader Area, DPAK 5−Lead Figure 6. qJA vs. Copper Spreader Area, D2PAK 5−Lead 100 Cu Area 167 mm2 10 R(t) C°/W Cu Area 736 mm2 1.0 sqrt(t) 0.1 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 TIME (sec) 0.1 1.0 10 100 1000 Figure 7. Single−Pulse Heating Curves, DPAK 5−Lead 100 Cu Area 167 mm2 10 R(t) C°/W Cu Area 736 mm2 1.0 0.1 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 TIME (sec) 0.1 1.0 10 100 1000 Figure 8. Single−Pulse Heating Curves, D2PAK 5−Lead http://onsemi.com 7 NCV4276 100 50% Duty Cycle 20% RqJA 736 mm2 C°/W 10 10% 5% 2% 1% 1.0 0.1 Non−normalized Response 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 PULSE WIDTH (sec) Figure 9. Duty Cycle for 1” Spreader Boards, DPAK 5−Lead 100 50% Duty Cycle RqJA 788 mm2 C°/W 10 20% 10% 5% 1.0 2% 1% 0.1 Non−normalized Response 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 PULSE WIDTH (sec) Figure 10. Duty Cycle for 1” Spreader Boards, D2PAK 5−Lead Junction R1 R2 R3 Rn C1 C2 C3 Cn Ambient (thermal ground) Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values. Figure 11. Grounded Capacitor Thermal Network (“Cauer” Ladder) R1 R2 R3 Rn Junction C1 C2 C3 Cn Each rung is exactly characterized by its RC−product time constant; amplitudes are the resistances. Ambient (thermal ground) Figure 12. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder) http://onsemi.com 8 NCV4276 ORDERING INFORMATION Device NCV4276DT50RK NCV4276DS50 NCV4276DS50R4 NCV4276DT33RK NCV4276DS33 NCV4276DS33R4 NCV4276DT25RK NCV4276DS25 NCV4276DS25R4 NCV4276DT18RK NCV4276DS18 NCV4276DS18R4 1.8 V 2.5 V 3.3 V 5.0 V Output Voltage Package DPAK, 5−Pin D2PAK 5 Pin PAK, 5−Pin DPAK, 5−Pin D2PAK 5 Pin PAK, 5−Pin DPAK, 5−Pin D2PAK 5 Pin PAK, 5−Pin DPAK, 5−Pin D2PAK 5 Pin PAK, 5−Pin Shipping 2500 Tape & Reel 50 Units / Rail 800 Tape & Reel 2500 Tape & Reel 50 Units / Rail 800 Tape & Reel 2500 Tape & Reel 50 Units / Rail 800 Tape & Reel 2500 Tape & Reel 50 Units / Rail 800 Tape & Reel http://onsemi.com 9 NCV4276 PACKAGE DIMENSIONS DPAK 5 CENTER LEAD CROP DT SUFFIX CASE 175AA−01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.020 0.028 0.018 0.023 0.024 0.032 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.045 BSC 0.170 0.190 0.185 0.210 0.025 0.040 0.020 −−− 0.035 0.050 0.155 0.170 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.51 0.71 0.46 0.58 0.61 0.81 4.56 BSC 0.87 1.01 0.46 0.58 2.60 2.89 1.14 BSC 4.32 4.83 4.70 5.33 0.63 1.01 0.51 −−− 0.89 1.27 3.93 4.32 −T− B V R C E SEATING PLANE R1 S A 1234 5 Z U K F L D G 5 PL J H 0.13 (0.005) M DIM A B C D E F G H J K L R R1 S U V Z T http://onsemi.com 10 NCV4276 PACKAGE DIMENSIONS D2PAK 5 LEAD DS SUFFIX CASE 936A−02 ISSUE B −T− A K B 12345 OPTIONAL CHAMFER TERMINAL 6 E U V S H M L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A AND K. 4. DIMENSIONS U AND V ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 6. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAXIMUM. DIM A B C D E G H K L M N P R S U V INCHES MIN MAX 0.386 0.403 0.356 0.368 0.170 0.180 0.026 0.036 0.045 0.055 0.067 BSC 0.539 0.579 0.050 REF 0.000 0.010 0.088 0.102 0.018 0.026 0.058 0.078 5 _ REF 0.116 REF 0.200 MIN 0.250 MIN MILLIMETERS MIN MAX 9.804 10.236 9.042 9.347 4.318 4.572 0.660 0.914 1.143 1.397 1.702 BSC 13.691 14.707 1.270 REF 0.000 0.254 2.235 2.591 0.457 0.660 1.473 1.981 5 _ REF 2.946 REF 5.080 MIN 6.350 MIN D 0.010 (0.254) M T N G R P C http://onsemi.com 11 NCV4276 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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