NCV4279

NCV4279 5.0 V Micropower 150 mA LDO Linear Regulator with DELAY, Adjustable RESET, and Sense Output The NCV4279 is a 5.0 V precision micropower voltage regulator with an output current capability of 150 mA. The output voltage is accurate within ±2.0% with a maximum dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature drawing only 150 mA with a 1.0 mA load. This part is ideal for any and all battery operated microprocessor equipment. Microprocessor control logic includes an active reset output RO with delay and a SI/SO monitor which can be used to provide an early warning signal to the microprocessor of a potential impending reset signal. The use of the SI/SO monitor allows the microprocessor to finish any signal processing before the reset shuts the microprocessor down. The active Reset circuit operates correctly at an output voltage as low as 1.0 V. The Reset function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits. The reset threshold voltage can be decreased by the connection of an external resistor divider to the RADJ lead. The regulator is protected against reverse battery, short circuit, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments. The device has also been optimized for EMC conditions. If the application requires pullup resistors at the logic outputs Reset and Sense Out, the NCV4269 with integrated resistors can be used. Features http://onsemi.com MARKING DIAGRAMS 8 8 1 SO−8 D SUFFIX CASE 751 1 14 14 1 SO−14 D SUFFIX CASE 751A 1 A WL, L YY, Y WW, W G, G = Assembly Location = Wafer Lot = Year = Work Week = Lead Free Indicators NCV4279 AWLYWWG 4279 ALYW G ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. • • • • • • • • • • • • 5.0 V ± 2.0% Output Low 150 mA Quiescent Current Active Reset Output Low Down to VQ = 1.0 V Adjustable Reset Threshold 150 mA Output Current Capability Fault Protection ♦ +60 V Peak Transient Voltage ♦ −40 V Reverse Voltage ♦ Short Circuit ♦ Thermal Overload Early Warning through SI/SO Leads Internally Fused Leads in SO−14 Package Very Low Dropout Voltage Electrical Parameters Guaranteed Over Entire Temperature Range Pb−Free Packages are Available NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes © Semiconductor Components Industries, LLC, 2005 1 December, 2005 − Rev. 3 Publication Order Number: NCV4279/D NCV4279 I Reference and Trim Q Current and Saturation Control Error Amplifier D RO or Reference SO RADJ SI + − GND Figure 1. Block Diagram PIN CONNECTIONS 1 I SI RADJ D 1 8 Q SO RO GND RADJ D GND GND GND GND RO SO−14 14 SI I GND GND GND Q SO SO−8 PACKAGE PIN DESCRIPTION Package Pin Number SO−8 3 4 5 6 7 8 1 2 SO−14 1 2 3, 4, 5, 6, 10, 11, 12 7 8 9 13 14 Pin Symbol RADJ D GND RO SO Q I SI Function Reset Threshold Adjust; if not used to connect to GND. Reset Delay; To Set Time Delay, Connect to GND with a Capacitor Ground Reset Output; This is an Open−Collector Output. Leave Open if Not Used. Sense Output; This is an Open−Collector Output. If not used, keep open. 5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 10 W. Input; Connect to GND Directly at the IC with a Ceramic Capacitor. Sense Input; If not used, Connect to Q. http://onsemi.com 2 NCV4279 MAXIMUM RATINGS (TJ = −40°C to 150°C) Parameter Input to Regulator Input Peak Transient Voltage Sense Input Reset Threshold Adjust Reset Delay Ground Reset Output Sense Output Regulated Output Junction Temperature Storage Temperature Input Voltage Operating Range Junction Temperature Operating Range Junction−to−Ambient Thermal Resistance Junction−to−Pin 4, all GND Pins Grounded. Lead Temperature Soldering and MSL Parameter MSL, 8−Lead, 14−Lead, LS Temperature 260°C Peak (Notes 3, 4) Symbol MSL Value 1 Unit − SO−8 SO−14 SO−14 Symbol VI II VI VSI ISI VRADJ IRADJ VD ID Iq VRO IRO VSO ISO VQ IQ TJ TSTG VI TJ RqJA RqJP Min −40 Internally Limited − −40 −1 −0.3 −10 −0.3 Internally Limited 50 −0.3 Internally Limited −0.3 Internally Limited −0.5 −10 − −50 − −40 − − Max 45 Internally Limited 60 45 1 7 10 7 Internally Limited − 7 Internally Limited 7 Internally Limited 7.0 − 150 150 45 150 200 70 30 Unit V V V mA V mA V mA V V V mA °C °C V °C k/W k/W Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series incorporates ESD protection and exceeds the following ratings: Human Body Model (HBM) ≤ 2.0 kV per JEDEC standard: JESD22–A114. Machine Model (MM) ≤ 200 V per JEDEC standard: JESD22–A115. 2. Latchup Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78. 3. Lead free: 60−150 Sec above 217°C, 40 Sec Max at Peak, 265°C Peak. 4. Leaded; 60−150 Sec above 183°C, 30 Sec Max at Peak, 240°C Peak. http://onsemi.com 3 NCV4279 ELECTRICAL CHARACTERISTICS (TJ = −40°C ≤ TJ ≤ 125°C, VI = 13.5 V unless otherwise specified) Characteristic REGULATOR Output Voltage Current Limit Current Consumption; Iq = II – IQ Current Consumption; Iq = II – IQ Current Consumption; Iq = II – IQ Dropout Voltage Load Regulation Line Regulation RESET GENERATOR Reset Switching Threshold Reset Adjust Switching Threshold Reset Output Saturation Voltage Upper Delay Switching Threshold Lower Delay Switching Threshold Saturation Voltage on Delay Capacitor Charge Current Delay Time L ³ H Delay Time H ³ L INPUT VOLTAGE SENSE Sense Threshold High Sense Threshold Low Sense Output Saturation Voltage Sense Input Current VSI, High VSI, Low VSO, Low ISI − − VSI < 1.20 V; VQ > 3 V; RSO = 20 kW − 1.24 1.16 − −1.0 1.31 1.20 0.1 0.1 1.38 1.28 0.4 1.0 V V V mA VRT VRAD,JTH VRO,SAT VUD VLD VD,SAT ID td tt − VQ > 3.5 V VQ < VRT, RRO = 20 kW − − VQ < VRT VD = 1 V CD = 100 nF CD = 100 nF 4.50 1.26 − 1.4 0.3 − 3.0 17 − 4.65 1.35 0.1 1.8 0.45 − 6.5 28 1.0 4.80 1.44 0.4 2.2 0.60 0.1 9.5 − − V V V V V V mA ms ms VQ IQ Iq Iq Iq Vdr DVQ DVQ 1 mA v IQ v 100 mA; 6 V v VI v 16 V − IQ = 1 mA, RO, SO High IQ = 10 mA, RO, SO High IQ = 50 mA, RO, SO High IQ = 100 mA (Note 5) IQ = 5 mA to 100 mA VI = 6 V to 26 V; IQ = 1 mA 4.90 150 − − − − − − 5.00 200 150 250 2.0 0.25 10 10 5.10 500 250 450 3.0 0.5 20 30 V mA mA mA mA V mV mV Symbol Test Conditions Min Typ Max Unit 5. Dropout voltage = VI − VQ measured when the output voltage has dropped 100 mV from the nominal value obtained at 13.5 V input. http://onsemi.com 4 NCV4279 II IQ CQ 22 mF RSO ISI VI SI D RADJ SO IRADJ VQ RRO I CI 470 nF Q 1000 mF RADJ1 GND RO VSI ID Iq VRO VSO VRADJ CD 100 nF VD RADJ2 Figure 2. Measuring Circuit VI t < tRR VQ VRT t VD VUD VLD t td VRO VRO,SAT t Power−on−Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output tRR dV I +D dt CD Figure 3. Reset Timing Diagram http://onsemi.com 5 NCV4279 Sense Input Voltage VSLHIGH VSLLOW t Sense Output Voltage tPDSOLH tPDSOHL HIGH LOW t Figure 4. Sense Timing Diagram http://onsemi.com 6 NCV4279 TYPICAL PERFORMANCE CHARACTERISTICS 16 14 12 ID,C. (mA) 10 8 6 4 2 0 −40 VD, (V) VI = 13.5 V VD = 1.0 V 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 40 TJ (°C) 80 120 160 0 −40 0 40 TJ (°C) 80 120 160 VLD VUD VI = 13.5 V Figure 5. Charge Current ID,c vs. Temperature TJ Figure 6. Switching Voltage VUD and VLD vs. Temperature TJ 1.7 1.6 500 400 TJ = 125°C VDRADJ,TH, (V) 150 180 VDR (mV) 300 TJ = 25°C 1.5 1.4 1.3 1.2 1.1 200 TJ = −40°C 100 1.0 0 0 30 60 90 IQ (mA) 120 0.9 −40 0 40 TJ (°C) 80 120 160 Figure 7. Drop Voltage VDR vs. Output Current IQ 35 30 25 VQ, (V) Iq (mA) 20 15 10 5 0 0 RL = 50 W RL = 100 W 10 20 VI (V) 30 RL = 200 W RL = 33 W 12 10 8 6 4 2 0 40 50 0 Figure 8. Reset Adjust Switching Threshold VRADJ,TH vs. Temperature TJ RL = 50 W 2 4 VI (V) 6 8 10 Figure 9. Current Consumption Iq vs. Input Voltage VI Figure 10. Output Voltage VQ vs. Input Voltage VI http://onsemi.com 7 NCV4279 TYPICAL PERFORMANCE CHARACTERISTICS 1.6 VI = 13.5 V 1.5 1.4 VSI, (V) 1.3 Sense Output Low 1.2 1.1 1.0 −40 2.1 5.0 VQ, (V) Sense Output High 4.9 4.8 4.7 4.6 −40 5.2 VI = 13.5 V 0 40 TJ (°C) 80 120 160 0 40 TJ (°C) 80 120 160 Figure 11. Sense Threshold VSI vs. Temperature TJ Figure 12. Output Voltage VQ vs. Temperature TJ 350 300 250 TJ = 25°C IQ (mV) 200 150 100 50 0 0 TJ = 125°C 10 20 VI (V) 30 40 50 Figure 13. Output Current IQ vs. Input Voltage VI http://onsemi.com 8 NCV4279 TYPICAL PERFORMANCE CHARACTERISTICS 12 10 8 Iq, (mA) Iq, (mA) 1.0 0.8 0.6 0.4 2 0 0 20 40 60 IQ (mA) 80 100 120 0.2 0 0 10 20 IQ (mA) 30 40 50 VI = 13.5 V TJ = 25°C 6 4 VI = 13.5 V TJ = 25°C 1.6 1.4 1.2 Figure 14. Current Consumption Iq vs. Output Current IQ Figure 15. Current Consumption Iq vs. Output Current IQ 7 6 TJ = 25°C 250 TJ = 25°C IQ = 100 mA 200 5 Iq, (mA) 4 3 2 1 0 6 8 10 12 14 IQ = 50 mA 50 IQ = 10 mA 16 VI (V) 18 20 22 24 26 0 6 8 10 12 IQ = 100 mA Iq, (mA) 150 100 14 16 VI (V) 18 20 22 24 26 Figure 16. Current Consumption Iq vs. Input Voltage VI Figure 17. Current Consumption Iq vs. Input Voltage VI http://onsemi.com 9 NCV4279 APPLICATION DESCRIPTION OUTPUT REGULATOR The output is controlled by a precision trimmed reference. The PNP output has drive quiescent current control for regulation while the input voltage is low, preventing over saturation. Current limit and voltage monitors complement the regulator design to give safe operating signals to the processor and control circuits. RESET OUTPUT (RO) If the reset adjust option is not needed, the RADJ pin should be connected to GND causing the reset threshold to go to its default value (typically 4.65 V). RESET DELAY (D) A reset signal, Reset Output, RO, (low voltage) is generated as the IC powers up. After the output voltage VQ increases above the reset threshold voltage VRT, the delay timer D is started. When the voltage on the delay timer VD passes VUD, the reset signal RO goes high. A discharge of the delay timer VD is started when VQ drops and stays below the reset threshold voltage VRT. When the voltage of the delay timer VD drops below the lower threshold voltage VLD the reset output voltage VRO is brought low to reset the processor. The reset output RO is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC, thereby guaranteeing that RO is valid for VQ as low as 1.0 V. RESET ADJUST (RADJ) The reset delay circuit provides a delay (programmable by capacitor CD) on the reset output lead RO. The delay lead D provides charge current ID (typically 6.5 mA) to the external delay capacitor CD during the following times: 1. During Powerup (once the regulation threshold has been exceeded). 2. After a reset event has occurred and the device is back in regulation. The delay capacitor is set to discharge when the regulation (VRT, reset threshold voltage) has been violated. When the delay capacitor discharges to VLD, the reset signal RO pulls low. SETTING THE DELAY TIME The delay time is set by the delay capacitor CD and the charge current ID. The time is measured by the delay capacitor voltage charging from the low level of VDSAT to the higher level VUD. The time delay follows the equation: td + [CD (VUD * VDSAT)] ID (eq. 2) The reset threshold VRT can be decreased from a typical value of 4.65 V to as low as 3.5 V by using an external voltage divider connected from the Q lead to the pin RADJ, as shown in Figure 18. The resistor divider keeps the voltage above the VRADJ,TH (typical 1.35 V) for the desired input voltages, and overrides the internal threshold detector. Adjust the voltage divider according to the following relationship: VRT + VRADJ, TH @ (RADJ1 ) RADJ2) RADJ2 (eq. 1) Example: Using CD = 100 nF. Use the typical value for VDSAT = 0.1 V. Use the typical value for VUD = 1.8 V. Use the typical value for Delay Charge Current ID = 6.5 mA. td + [100 nF (1.8 * 0.1 V)] 6.5 mA + 26.2 ms (eq. 3) VBAT CI* 0.1 mF I Q RADJ1 RADJ RADJ2 CQ** 10 mF RSI1 RRO RSI2 RSO VDD NCV4279 D CD SI SO GND RO I/O *CI required if regulator is located far from the power supply filter. ** CQ required for Stability. Cap must operate at minimum temperature expected. Figure 18. Application Diagram http://onsemi.com 10 Microprocessor I/O NCV4279 SENSE INPUT (SI) / SENSE OUTPUT (SO) VOLTAGE MONITOR An on−chip comparator is available to provide early warning to the microprocessor of a possible reset signal. The output is from an open collector driver. The reset signal typically turns the microprocessor off instantaneously. This can cause unpredictable results with the microprocessor. The signal received from the SO pin will allow the microprocessor time to complete its present task before shutting down. This function is performed by a comparator referenced to the band gap voltage. The actual trip point can be programmed externally using a resistor divider to the input monitor SI (Figure 18). The values for RSI1 and RSI2 are selected for a typical threshold of 1.20 V on the SI Pin. SIGNAL OUTPUT expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet usually provides this information. The value for the output capacitor CQ shown in Figure 18 should work for most applications; however, it is not necessarily the optimized solution. Stability is guaranteed at values CQ = 10 mF and an ESR = 10 W within the operating temperature range. Actual limits are shown in a graph in the typical data section. CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR The maximum power dissipation for a single output regulator (Figure 18) is: PD(max) + [VI(max) * VQ(min)] IQ(max) ) VI(max) Iq (eq. 4) Figure 19 shows the SO Monitor timing waveforms as a result of the circuit depicted in Figure 18. As the output voltage (VQ) falls, the monitor threshold (VSILOW), is crossed. This causes the voltage on the SO output to go low sending a warning signal to the microprocessor that a reset signal may occur in a short period of time. TWARNING is the time the microprocessor has to complete the function it is currently working on and get ready for the reset shutdown signal. VQ where: VI(max) is the maximum input voltage, VQ(min) is the minimum output voltage, IQ(max) is the maximum output current for the application, and Iq is the quiescent current the regulator consumes at IQ(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: RqJA = (150°C – TA) / PD (eq. 5) SI VSILOW VRO The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. The current flow and voltages are shown in the Measurement Circuit Diagram. HEATSINKS SO TWARNING Figure 19. SO Warning Waveform Time Diagram STABILITY CONSIDERATIONS A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA: RqJA + RqJC ) RqCS ) RqSA (eq. 6) The input capacitor CI in Figure 18 is necessary for compensating input line reactance. Possible oscillations caused by input inductance and input capacitance can be damped by using a resistor of approximately 1.0 W in series with CI. The output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least where: RqJC = the junction−to−case thermal resistance, RqCS = the case−to−heat sink thermal resistance, and RqSA = the heat sink−to−ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in data sheets of heatsink manufacturers. Thermal, mounting, and heatsinking considerations are discussed in the ON Semiconductor application note AN1040/D, available on the ON Semiconductor website. http://onsemi.com 11 NCV4279 ORDERING INFORMATION Device NCV4279D1 NCV4279D1G NCV4279D1R2 NCV4279D1R2G NCV4279D2 NCV4279D2G NCV4279D2R2 NCV4279D2R2G 5.0 V Output Voltage Package SO−8 SO−8 (Pb−Free) SO−8 SO−8 (Pb−Free) SO−14 SO−14 (Pb−Free) SO−14 SO−14 (Pb−Free) 2500 Tape & Reel 55 Units/Rail 2500 Tape & Reel 98 Units/Rail Shipping† †For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 12 NCV4279 PACKAGE DIMENSIONS SO−8 D SUFFIX CASE 751−07 ISSUE AF −X− A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 B 1 4 S 0.25 (0.010) M Y M −Y− G C −Z− H D 0.25 (0.010) M SEATING PLANE K N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 13 NCV4279 PACKAGE DIMENSIONS SO−14 D SUFFIX CASE 751A−03 ISSUE G −A− 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −B− 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 _ F −T− SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 14 NCV4279/D