NCV4299C
Voltage Regulator Low-Dropout
150 mA
The NCV4299C is a family of precision micropower voltage
regulators with an output current capability of 150 mA. It is available in
5.0 V or 3.3 V output voltage.
The output voltage is accurate within ±2% with a maximum dropout
voltage of 0.5 V at 100 mA. Low Quiescent current is a feature
drawing only 80 mA with a 100 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
The device features microprocessor interfaces including an
adjustable reset output and adjustable system monitor to provide
shutdown early warning. An inhibit function is available. With inhibit
active, the regulator turns off and the device consumes less than
1.0 mA of quiescent current.
The part can withstand load dump transients making it suitable for
use in automotive environments.
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MARKING
DIAGRAMS
8
SO−8
D1 SUFFIX
CASE 751
8
1
299Cx
ALYW
G
1
14
SO−14
D2 SUFFIX
CASE 751A
14
1
V4299CxxG
AWLYWW
1
Features
• 5.0 V, 3.3 V ±2%, 150 mA
• Extremely Low Current Consumption
x, xx
80 mA (Typ) in the ON Mode
t1.0 mA in the Off Mode
Early Warning
Reset Output Low Down to VQ = 1.0 V
Adjustable Reset Threshold
Wide Temperature Range
Fault Protection
♦ 60 V Peak Transient Voltage
♦ −40 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload
Internally Fused Leads on SO−14 Package
Inhibit Function with 1 mA Current Consumption in the Off Mode
AEC−Q100 Grade 1 Qualified and PPAP Capable
These are Pb−Free Devices
= 3 or 33 (3.3 V Version)
= 5 or 50 (5.0 V Version)
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
♦
•
•
•
•
•
•
•
•
•
♦
(Note: Microdot may be in either location)
PIN CONNECTIONS
I
SI
RADJ
D
RADJ
D
1
8
Q
GND
SO
GND
RO
GND GND
INH
SOIC−8
RO
1
14
SI
I
GND
GND
GND
Q
SO
SOIC−14
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
October, 2019 − Rev. 0
1
Publication Order Number:
NCV4299C/D
NCV4299C
Q
I
Bandgap
Reference
Current Limit and
Saturation Sense
+
RSO
RRO
SO
1.36 V
+
−
SI
7.1 mA
+
+
-
RADJ
RO
+
1.85 V
D
GND
Figure 1. SO−8 Simplified Block Diagram
PIN FUNCTION DESCRIPTION − SO−8 PACKAGE
Pin
Symbol
Description
1
I
2
SI
3
RADJ
4
D
5
GND
6
RO
Reset Output. NPN collector output with internal 20 kW pullup to Q. Notifies user of out of regulation
condition. Leave open if not used.
7
SO
Sense Output. NPN collector output with internal 20 kW pullup to Q. Can be used to provide early warning
of an impending reset condition. Leave open if not used.
8
Q
Input. Battery Supply Input Voltage. Bypass directly to GND with ceramic capacitor.
Sense Input. Can provide an early warning signal of an impending reset condition when used with SO.
Connect to Q if not used.
Reset Adjust. Use resistor divider to Q to adjust reset threshold lower. Connect to GND if not used.
Reset Delay. Connect external capacitor to ground to set delay time.
Ground.
5.0 V, 3.3 V, ±2%, 150 mA output. Use 22 mF, ESR t 4 W to ground.
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2
NCV4299C
Q
I
Bandgap
Reference
Current Limit and
Saturation Sense
+
RSO
RRO
INH
SO
1.36 V
+
−
SI
7.1 mA
+
+
-
RADJ
RO
+
1.85 V
D
Figure 2. Simplified Block Diagram
GND
PIN FUNCTION DESCRIPTION
Pin No.
SOIC−14
Symbol
1
RADJ
2
D
3
GND
Ground
4
GND
Ground
5
GND
Ground
6
INH
Inhibit. Connect to I if not needed. A high turns the regulator on. Use a low pass filter if transients with slew rate in
excess of 10 V/ms may be present on this pin during operation. See Figure 34 for details.
7
RO
Reset Output. NPN collector output with internal 20 kW pullup to Q. Notifies user of out of regulation condition.
8
SO
Sense Output. NPN collector output with internal 20 kW pullup to Q. Can be used to provide early warning of an
impending reset condition.
9
Q
10
GND
Ground
11
GND
Ground
12
GND
Ground
13
I
14
SI
Description
Reset Adjust. Use resistor divider to Q to adjust reset threshold lower. Connect to GND if not used.
Reset Delay. Connect external capacitor to ground to set delay time.
5.0 V, 3.3 V, "2%, 150 mA output. Use 22 mF, ESR t 4 W to ground.
Input. Battery Supply Input Voltage.
Sense Input. Can provide an early warning signal of an impending reset condition when used with SO.
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3
NCV4299C
MAXIMUM RATINGS
Rating
Symbol
Min
Max
Unit
Input Voltage to Regulator (DC)
VI
−40
45
V
Input Peak Transient Voltage to Regulator wrt GND (Note 1)
−
−
60
V
VINH
−40
45
V
Inhibit (INH)
Sense Input (SI)
VSI
−40
45
V
Sense Input (SI)
ISI
−1.0
1.0
mA
Reset Threshold (RADJ)
VRADJ
−0.3
7.0
V
Reset Threshold (RADJ)
IRADJ
−10
10
mA
Reset Delay (D)
VD
−0.3
7.0
V
Reset Output (RO)
VRO
−0.3
7.0
V
Reset Output (RO)
IRO
−20
20
mA
Sense Output (SO)
VSO
−0.3
7.0
V
Output (Q)
VQ
−0.3
16
V
Output (Q)
IQ
−5.0
−
mA
ESDHB
2.0
−
kV
ESD Capability, Machine Model (Note 3)
ESDMM
200
−
V
ESD Capability, Charged Device Model (Note 3)
ESDCDM
1.0
−
kV
Junction Temperature
TJ
−
150
°C
Storage Temperature
Tstg
−50
150
°C
ESD Capability, Human Body Model (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING RANGE
Input Voltage
5.0 V Version
3.3 V Version
Junction Temperature
VI
5.5
4.4
45
45
V
TJ
−40
150
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
LEAD TEMPERATURE SOLDERING REFLOW (Note 2)
Reflow (SMD styles only), lead free 60 s−150 sec above 217, 40 sec max at peak
TSLD
Moisture Sensitivity Level
MSL
SO−8
SO−14
−
265 Pk
°C
Level 1
Level 1
1. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class C according to ISO16750−1
2. Per IPC / JEDEC J−STD−020C.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (JS−001−2010)
ESD MM tested per AEC−Q100−003 (EIA/JESD22−A115)
ESD CDM tested per AEC−Q100−011 (EIA/JESD22−C101).
THERMAL CHARACTERISTICS
Test Conditions (Typical Value)
Characteristic
Note 4
Note 5
Note 6
Unit
Thermal Characteristics, SO−8
Junction−to−Lead (yJLx, qJLx)
Junction−to−Ambient (RθJA, qJA)
72
198
58
150.7
58.3
124.5
°C/W
Thermal Characteristics, SO−14
Junction−to−Lead (yJLx, qJLx)
Junction−to−Ambient (RθJA, qJA)
15.1
142.7
19.9
101.2
19.3
86.1
°C/W
Thermal Characteristics, TSSOP−14 EP
Junction−to−Tab (yJLx, qJLx)
Junction−to−Ambient (RθJA, qJA)
9.7
111.6
11.4
78.7
11.7
53.7
°C/W
4. 2 oz Copper, 50 mm sq Copper area, 1.5 mm thick FR4.
5. 2 oz Copper, 150 mm sq Copper area, 1.5 mm thick FR4.
6. 2 oz Copper, 500 mm sq Copper area, 1.5 mm thick FR4.
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4
NCV4299C
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C; VI = 13.5 V unless otherwise noted.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
OUTPUT Q
Output Voltage (5.0 V Version)
VQ
1.0 mA < IQ < 150 mA, 6.0 V < VI < 16 V
4.9
5.0
5.1
V
Output Voltage (3.3 V Version)
VQ
1.0 mA < IQ < 150 mA, 5.5 V < VI < 16 V
3.23
3.3
3.37
V
Current Limit
IQ
VQ = 90% of VQnom
250
430
500
mA
Quiescent Current (Iq = II – IQ)
Iq
INH ON, IQ < 100 mA, TJ = 25°C
−
80
90
mA
Quiescent Current (Iq = II – IQ)
Iq
INH ON, IQ < 100 mA, TJ ≤ 125°C
−
80
95
mA
Quiescent Current (Iq = II – IQ)
Iq
INH ON, IQ = 10 mA
−
200
500
mA
Quiescent Current (Iq = II – IQ)
Iq
INH ON, IQ = 50 mA
−
0.8
2.0
mA
Quiescent Current (Iq = II – IQ)
Iq
INH = 0 V, TJ = 25°C
−
−
1.0
mA
IQ = 100 mA
−
0.26
0.50
V
Dropout Voltage (Note 7)
Vdr
Load Regulation
DVQ
IQ = 1.0 mA to 100 mA
−
1.0
30
mV
Line Regulation
DVQ
VI = 6.0 V to 28 V, IQ = 1.0 mA
−
2.0
25
mV
ƒr = 100 Hz, Vr = 1.0 Vpp, IQ = 100 mA
−
66
−
dB
VQ < 0.1 V
−
−
0.8
V
VQ > 4.9 V
VQ > 3.23 V
3.5
3.5
−
−
−
−
−
−
3.8
0.01
10
2.0
4.50
2.96
4.67
3.07
4.80
3.16
10
20
40
−
−
0.05
0.05
0.40
0.40
5.6
−
−
kW
Power Supply Ripple Rejection
PSRR
INHIBIT (INH)
Inhibit Off Voltage
VINHOFF
Inhibit On Voltage
5.0 V Version
3.3 V Version
VINHON
Input Current
IINHON
IINHOFF
INH = 5 V
INH = 0 V
V
mA
RESET (RO)
Switching Threshold
5.0 V Version
3.3 V Version
VRT
−
Output Resistance
RRO
−
Reset Output Low Voltage
5.0 V Version
3.3 V Version
VRO
Allowable External Reset Pullup Resistor
VROext
VQ = 4.5 V, Internal RRO, IRO = −1.0 mA
VQ = 2.96 V, Internal RRO, IRO = −1.0 mA
External Resistor to Q
V
kW
V
Delay Upper Threshold
VUD
−
1.5
1.85
2.2
V
Delay Lower Threshold
VLD
−
0.4
0.5
0.6
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Only for 5 V version. Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5 V.
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5
NCV4299C
ELECTRICAL CHARACTERISTICS (continued) (−40°C < TJ < 150°C; VI = 13.5 V unless otherwise noted.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
−
−
−
0.017
0.1
0.1
Unit
RESET (RO)
VD,sat
Delay Output Low Voltage
5.0 V Version
3.3 V Version
VQ = 4.5 V, Internal RRO
VQ = 2.96 V, Internal RRO
V
Delay Charge Current
ID
VD = 1.0 V
4.0
7.1
12
mA
Power On Reset Delay Time
td
CD = 100 nF
17
28
35
ms
tRR
CD = 100 nF
0.5
1.6
4.0
ms
VQ = 3.5 V
VQ = 2.3 V
1.26
1.26
1.36
1.36
1.44
1.44
Reset Reaction Time
Reset Adjust Switching Threshold
5.0 V Version
3.3 V Version
VRADJ,TH
V
INPUT VOLTAGE SENSE (SI and SO)
Sense Input Threshold High
VSI,High
−
1.34
1.45
1.54
V
Sense Input Threshold Low
VSI,Low
−
1.26
1.36
1.44
V
50
90
130
mV
−1.0
0.1
1.0
mA
10
20
40
kW
−
0.1
0.4
V
5.6
−
−
kW
Sense Input Hysteresis
−
(Sense Threshold High) −
(Sense Threshold Low)
Sense Input Current
ISI
VSI = 1.2 V
Sense Output Resistance
RSO
Sense Output Low Voltage
VSO
−
VSI = 1.2 V, VI = 5.5 V, ISO = 0 mA
Allowable External Sense Out
Pullup Resistor
RSOext
−
SI High to SO High Reaction Time
tPSOLH
RSOext = 5.6 kW
−
1.3
8.0
ms
SI Low to SO Low Reaction Time
tPSOHL
RSOext = 5.6 kW
−
2.2
5.0
ms
150
−
200
°C
THERMAL SHUTDOWN
TSD
Thermal Shutdown Temperature (Note 8)
Iout = 1 mA
8. Values based on design and/or characterization.
II
VI
I
IINH
Q
INH
NCV4299C
VINH
IQ
D
CD
100 nF
VRADJ
VSI
IRADJ
ISI
ID
RADJ
SI
RO
VRO
SO
VSO
GND
Iq
Figure 3. Measurement Circuit
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6
VQ
NCV4299C
TYPICAL PERFORMANCE CHARACTERISTICS − 5.0 V OPTION
6
VI = 13.5 V
IQ = 100 mA
VQ, OUTPUT VOLTAGE (V)
VQ, OUTPUT VOLTAGE (V)
5.1
5.0
4.9
−40 −20
0
20
40
60
80
5
4
3
2
0
0
100 120 140 160
TJ, JUNCTION TEMPERATURE (°C)
7.6
14
12
TJ = 150°C
7.2
6.8
6.4
6.0
−40 −20
400
TJ = −40°C
200
100
0
0
20 40
60 80 100 120 140 160
TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C
300
0
Figure 6. Charge Current vs. Junction
Temperature
3.2
VI = 13.5 V
2.4
2.0
1.6
1.2
0.8
0.4
0
40
120
80
TJ, JUNCTION TEMPERATURE (°C)
100
50
IQ, OUTPUT CURRENT (mA)
150
Figure 7. Drop Voltage vs. Output Current
VRADJ,TH, RESET ADJUST SWITCHING
THRESHOLD (V)
VUD, VLD, SWITCHING VOLTAGE (V)
10
4
6
8
VI, INPUT VOLTAGE (V)
500
VI = 13.5 V
VD = 1 V
IQ = 100 mA
Vdr, DROP VOLTAGE (mV)
ID, CHARGE CURRENT (mA)
8.0
0
−40
2
Figure 5. Output Voltage vs. Input Voltage
Figure 4. Output Voltage vs. Junction Temperature
2.8
IQ = 100 mA
TJ = 25°C
1
160
Figure 8. Switching Voltage vs. Junction
Temperature
1.5
VI = 13.5 V
1.4
1.3
1.2
1.1
1.0
0.9
−40
0
40
120
80
TJ, JUNCTION TEMPERATURE (°C)
160
Figure 9. Reset Adjust Switching Threshold vs.
Junction Temperature
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NCV4299C
400
1.5
IQ, OUTPUT CURRENT (mA)
VSI, SENSE LIMIT THRESHOLD (V)
1.6
VSI,Low
1.4
VSI,High
1.3
1.2
1.1
1.0
−40
0
40
120
80
TJ, JUNCTION TEMPERATURE (°C)
350
TJ = 25°C
250
200
150
100
50
0
160
TJ = 125°C
300
VQ = 0 V
0
40
4.0
1000
VI = 13.5 V
IQ = 100 mA
Iq, CURRENT CONSUMPTION (mA)
Iq, CURRENT CONSUMPTION (mA)
20
30
VI, INPUT VOLTAGE (V)
Figure 11. Output Current vs. Input Voltage
Figure 10. Sense Threshold vs. Junction
Temperature
100
10
1
−40 −20
0
20
40
60
80
3.0
2.5
2.0
1.5
1.0
0.5
0
100 120 140 160
VI = 13.5 V
TJ = 25°C
3.5
0
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Current Consumption vs. Junction
Temperature
120
40
80
IQ, OUTPUT CURRENT (mA)
160
Figure 13. Current Consumption vs. Output
Current
16
Iq, CURRENT CONSUMPTION (mA)
40
RRO, RSO, RESISTANCE (kW)
10
35
30
25
20
15
10
−40
0
40
80
120
14
12
10
IQ = 25 mA
8
IQ = 50 mA
IQ = 150 mA
IQ = 100 mA
6
4
2
0
160
TJ = 25°C
0
10
20
30
VI, INPUT VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 14. RRO, RSO Resistance vs. Junction
Temperature
Figure 15. Current Consumption vs. Input
Voltage
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8
40
110
Iq, CURRENT CONSUMPTION (mA)
120
TJ = 25°C
100
90
IQ = 100 mA
80
70
60
50
40
6
8
10
12 14 16 18 20
VI, INPUT VOLTAGE (V)
22
24
3.0
TJ = 25°C
2.5
2.0
1.5
1.0
IQ = 50 mA
0.5
0
26
IQ = 100 mA
IQ = 10 mA
8
6
10
14 16 18
20
12
VI, INPUT VOLTAGE (V)
100
VI = 13.5 V
TJ = 25°C
Unstable Region
10
1
1 mF to 100 mF
0.1
0.01
Stable Region
0
25
22
24
Figure 17. Current Consumption vs. Input
Voltage
Figure 16. Current Consumption vs. Input
Voltage
OUTPUT CAPACITOR ESR (W)
Iq, CURRENT CONSUMPTION (mA)
NCV4299C
50
75
100
125
IQ, OUTPUT CURRENT (mA)
Figure 18. Output Stability vs. Output Capacitor
ESR
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9
150
26
NCV4299C
TYPICAL PERFORMANCE CHARACTERISTICS − 3.3 V OPTION
5
VI = 13.5 V
IQ = 100 mA
Iq, QUIESCENT CURRENT (mA)
Iq, CURRENT CONSUMPTION (mA)
1000
100
10
1
−40 −20
0
20
40
60
80
TJ = −40°C
2
1
0
20
40
60
80
100
Figure 20. Current Consumption vs. Output
Current
3.40
10
IQ = 150 mA
8
IQ = 100 mA
6
IQ = 50 mA
IQ = 25 mA
4
2
0
10
20
30
VI = 13.5 V
IQ = 100 mA
3.35
3.30
3.25
3.20
−40 −20
40
0
20
40
60
80
100 120 140 160
VI, INPUT VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Current Consumption vs. Input
Voltage
Figure 22. Output Voltage vs. Junction
Temperature
400
3.0
IQ, OUTPUT CURRENT (mA)
TJ = 25°C
2.5
2.0
IQ = 100 mA
1.5
1.0
IQ = 50 mA
0.5
0
140 160
Figure 19. Current Consumption vs. Junction
Temperature
TJ = 25°C
0
120
IQ, OUTPUT CURRENT (mA)
VQ, OUTPUT VOLTAGE (V)
Iq, CURRENT CONSUMPTION (mA)
TJ = 25°C
TJ, JUNCTION TEMPERATURE (°C)
12
Iq, CURRENT CONSUMPTION (mA)
TJ = 150°C
3
0
100 120 140 160
VI = 13.5 V
4
IQ = 10 mA
6
8
10
12
14
16
18
20
22
24
350
TJ = 25°C
250
200
150
100
VQ = 0 V
50
0
26
TJ = 125°C
300
0
10
20
30
VI, INPUT VOLTAGE (V)
VI, INPUT VOLTAGE (V)
Figure 23. Current Consumption vs. Input
Voltage
Figure 24. Output Current vs. Input Voltage
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40
NCV4299C
TYPICAL PERFORMANCE CHARACTERISTICS − 3.3 V OPTION
85
3
2
1
0
2
4
6
8
10
12
80
IQ = 100 mA
75
70
6
8
10
12
14
16
18
20
22
26
24
VI, INPUT VOLTAGE (V)
VI, INPUT VOLTAGE (V)
Figure 25. Output Voltage vs. Input Voltage
Figure 26. Current Consumption vs. Input
Voltage
3.20
1.6
VI = 13.5 V
3.15
3.10
3.05
3.00
2.95
2.90
−40 −20
0
20
40
60
80
100 120 140 160
1.5
VSI,High
1.4
VSI,Low
1.3
1.2
VI = 13.5 V
IQ = 100 mA
1.1
1.0
−40
0
40
80
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 27. Reset Trigger Threshold vs.
Junction Temperature
Figure 28. Sense Threshold vs. Junction
Temperature
3.2
160
1.5
2.8
VI = 13.5 V
2.4
2.0
1.6
1.2
0.8
0.4
0
−40
TJ = 25°C
65
14
VSI, SENSE THRESHOLD (V)
VRT, RESET TRIGGER THRESHOLD (V)
Iq, CURRENT CONSUMPTION (mA)
4
0
VUD, VLD, SWITCHING VOLTAGE (V)
VI = 13.5 V
TJ = 25°C
5
0
40
80
120
VRADJ,TH, RESET ADJUST
SWITCHING THRESHOLD (V)
VQ, OUTPUT VOLTAGE (V)
6
160
VI = 13.5 V
1.4
1.3
1.2
1.1
1.0
0.9
−40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 29. Switching Voltage vs. Junction
Temperature
Figure 30. Reset Adjust Switching Threshold
vs. Junction Temperature
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11
NCV4299C
TYPICAL PERFORMANCE CHARACTERISTICS − 3.3 V OPTION
ID, CHARGE CURRENT (mA)
8.0
30
20
10
−40
0
40
80
120
160
VI = 13.5 V
VD = 1 V
IQ = 100 mA
7.6
7.2
6.8
6.4
6.0
−40
0
40
80
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 31. Resistance vs. Junction
Temperature
Figure 32. Charge Current vs. Junction
Temperature
100
OUTPUT CAPACITOR ESR (W)
RRO, RSO, RESISTANCE (kW)
40
VI = 13.5 V
TJ = 25°C
Unstable Region
10
1
2.2 mF to 100 mF
Stable Region
0.1
0.01
0
20
40
60
80
100
120
140
IQ, OUTPUT CURRENT (mA)
Figure 33. Output Capacitor ESR vs. Output
Current
www.onsemi.com
12
160
160
NCV4299C
APPLICATION DESCRIPTION
NCV4299C
Other features of the regulator include an undervoltage
reset function and a sense circuit. The reset function has an
adjustable time delay and an adjustable threshold level. The
sense circuit trip level is adjustable and can be used as an
early warning signal to the controller. An inhibit function
that turns off the regulator and reduces the current
consumption to less than 1.0 mA is a feature available in the
14 pin package.
The NCV4299C is a family of precision micropower
voltage regulators with an output current capability of
150 mA at 5.0 V and 3.3 V.
The output voltage is accurate within "2% with a
maximum dropout voltage of 0.5 V at 100 mA. Low
quiescent current is a feature drawing only 80 mA with a
100 mA load. This part is ideal for any and all battery
operated microprocessor equipment.
Microprocessor control logic includes an active reset
output RO (with delay), and a SI/SO monitor which can be
used to provide an early warning signal to the
microprocessor of a potential impending reset signal. The
use of the SI/SO monitor allows the microprocessor to finish
any signal processing before the reset shuts the
microprocessor down. Internal output resistors on the RO
and SO pins pulling up to the output pin Q reduce external
component count. An inhibit function is available on the
14−lead part. With inhibit active, the regulator turns off and
the device consumes less that 1.0 mA of quiescent current.
The active reset circuit operates correctly at an output
voltage as low as 1.0 V. The reset function is activated
during the powerup sequence or during normal operation if
the output voltage drops outside the regulation limits.
The reset threshold voltage can be decreased by the
connection of an external resistor divider to the RADJ lead.
The regulator is protected against reverse battery, short
circuit, and thermal overload conditions. The device can
withstand load dump transients making it suitable for use in
automotive environments.
Output Regulator
The output is controlled by a precision trimmed reference.
The PNP output has saturation control for regulation while
the input voltage is low, preventing oversaturation. Current
limit and voltage monitors complement the regulator design
to give safe operating signals to the processor and control
circuits.
Stability Considerations
The input capacitor CI is necessary for compensating
input line reactance. Possible oscillations caused by input
inductance and input capacitance can be damped by using a
resistor of approximately 1.0 W in series with CI.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay,
load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturer’s data sheet usually provides this information.
The value for the output capacitor CQ shown in Figure 34
should work for most applications, however, it is not
necessarily the optimized solution. Stability is guaranteed at
values CQ ≥ 22 mF and an ESR ≤ 4 W within the operating
temperature range. Actual limits are shown in a graph in the
typical performance characteristics section.
NCV4299C Circuit Description
The low dropout regulator in the NCV4299C uses a PNP
pass transistor to give the lowest possible dropout voltage
capability. The current is internally monitored to prevent
oversaturation of the device and to limit current during over
current conditions. Additional circuitry is provided to
protect the device during overtemperature operation.
The regulator provides an output regulated to 2%.
www.onsemi.com
13
NCV4299C
I
CI*
Q
RRADJ1
0.1 mF
SI
RS12
INH
RINH***
51kW
RRADJ2
NCV4299C
CD
CQ**
22 mF
RADJ
D
RS11
VDD
Microprocessor
VBAT
INH
CINH***
0.01 mF
SO
GND
I/O
RO
I/O
*CI required if regulator is located far from the power supply filter.
**CQ required for stability. Cap must operate at minimum temperature expected.
***This RC filter is only required when transients with slew rate in excess of 10 V/ms may be present on the INH
voltage source during operation. The filter is not required when INH is connected to a noise−free DC voltage.
Figure 34. Test and Application Circuit Showing all Compensation and Sense Elements
I
CI*
Q
0.1 mF
SI
RS12
SO
RRADJ2
NCV4299C
CD
CQ**
22 mF
RADJ
D
RS11
VDD
RRADJ1
Microprocessor
VBAT
GND
I/O
RO
I/O
*CI required if regulator is located far from the power supply filter.
**CQ required for stability. Cap must operate at minimum temperature expected.
Figure 35. Test and Application Circuit Showing all Compensation and Sense Elements for 8 Pin Package Part
www.onsemi.com
14
NCV4299C
Reset Output (RO)
threshold voltage VRT. When the voltage of the delay timer
(VD) drops below the lower threshold voltage VLD, the reset
output voltage VRO is brought low to reset the processor.
The reset output RO is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
guaranteeing that RO is valid for VQ as low as 1.0 V.
A reset signal, Reset Output (RO, low voltage) is
generated as the IC powers up. After the output voltage VQ
increases above the reset threshold voltage VRT, the delay
timer D is started. When the voltage on the delay timer VD
passes VUD, the reset signal RO goes high. D pin voltage in
steady state is typically 2.5 V. A discharge of the delay timer
(VD) is started when VQ drops and stays below the reset
VI
t
< tRR
VQ
VRT
t
dV
I
+ D
dt
CD
VD
VUD
VLD
td
t
tRR
VRO
VRO,SAT
Power−on−Reset
t
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Secondary
Spike
Overload
at Output
Figure 36. Reset Timing Diagram
Reset Adjust (RADJ)
Reset Delay (D)
The reset threshold VRT can be decreased from a typical
value of 4.67 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figure 34. The resistor divider keeps the voltage
above the VRADJ,TH, (typ. 1.36 V), for the desired input
voltages and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
The reset delay circuit provides a delay (programmable by
capacitor CD) on the reset output RO lead. The delay lead D
provides charge current ID (typically 7.1 mA) to the external
delay capacitor CD during the following times:
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device
is back in regulation. The delay capacitor is
set to discharge when the regulation (VRT, reset
threshold voltage) has been violated. When
the delay capacitor discharges to down to VLD,
the reset signal RO pulls low.
VTHRES + VRADJ, TH · (RADJ1 ) RADJ2)ńRADJ2
(eq. 1)
If the reset adjust option is not needed, the RADJ−pin
should be connected to GND causing the reset threshold to
go to its default value (typ. 4.67 V).
www.onsemi.com
15
NCV4299C
VQ
Setting the Delay Time
The delay time is set by the delay capacitor CD and the
charge current ID. The time is measured by the delay
capacitor voltage charging from the low level of VD,sat to the
higher level VUD. The time delay follows the equation:
td + [CD (VUD−VD, sat)]ńID
VSI
VSI,Low
(eq. 2)
VRO
Example:
Using CD = 100 nF.
Use the typical value for VD,sat = 0.1 V.
Use the typical value for VUD = 1.85 V.
Use the typical value for Delay Charge Current ID = 7.1 mA.
td + [100 nF(1.85−0.1 V)]ń7.1 mA + 24.6 ms
VSO
TWARNING
(eq. 3)
When the output voltage VQ drops below the reset
threshold voltage VRT, the voltage on the delay capacitor VD
starts to drop. The time it takes to drop below the lower
threshold voltage of VLD is the reset reaction time, tRR. This
time is typically 1.6 ms for a delay capacitor of 0.1 mF. The
reset reaction time can be estimated from the following
relationship:
tRR + 16 nsńnF
CD
Figure 37. SO Warning Timing Waveform
Sense
Input
Voltage
VSI,High
(eq. 4)
VSI,Low
Sense Input (SI)/Sense Output (SO) Voltage Monitor
An on−chip comparator is available to provide early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the SO pin will
allow the microprocessor time to complete its present task
before shutting down. This function is performed by a
comparator referenced to the band gap voltage. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (SI) (Figure 34). The typical
threshold is 1.36 V on the SI Pin.
Sense
Output
t
tPSOLH
tPSOHL
High
Low
t
Figure 38. Sense Timing Diagram
Signal Output
Calculating Power Dissipation in a Single Output
Linear Regulator
Figure 37 shows the SO Monitor waveforms as a result of
the circuits depicted in Figure 34. As the output voltage VQ
falls, the monitor threshold VSI,Low is crossed. This causes the
voltage on the SO output to go low sending a warning signal
to the microprocessor that a reset signal may occur in a short
period of time. TWARNING is the time the microprocessor has
to complete the function it is currently working on and get
ready for the reset shutdown signal. When the voltage on the
SO goes low and the RO stays high the current consumption
is typically 400 mA.
The maximum power dissipation for a single output
regulator is:
PD(max) + [VI(max)−VQ(min)] IQ(max) ) VI(max)Iq
(eq. 5)
where:
VI(max) is the maximum input voltage,
VQ(min) is the minimum output voltage,
IQ(max) is the maximum output current for the application,
and
Iq is the quiescent current the regulator consumes at IQ(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
RqJA + (150° C−TA)ńPD
www.onsemi.com
16
(eq. 6)
NCV4299C
Heatsinks
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA’s less than the calculated value in Equation 6 will keep
the die temperature below 150°C. In some cases, none of the
packages will be sufficient to dissipate the heat generated by
the IC, and an external heatsink will be required. Thermal
Resistance RqJA vs. Copper Area is shown in Figure 39.
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
THERMAL RESISTANCE, JUNCTION−
TO−AMBIENT, RqJA, (°C/W)
250
RqJA + RqJC ) RqCS ) RqSA
where:
1 oz SO−8
2 oz SO−8
200
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heatsink thermal resistance, and
RqSA = the heatsink−to−ambient thermal resistance.
2 oz SO−14
150
1 oz SO−14
RqJC appears in the package section of the data sheet. Like
RqJA, it too is a function of package type. RqCS and RqSA are
functions of the package type, heatsink and the interface
between them. These values appear in heatsink data sheets of
heatsink manufacturers. Thermal, mounting, and heatsinking
are discussed in the ON Semiconductor application note
AN1040/D, available on the ON Semiconductor website.
100
50
0
0
(eq. 7)
100
200
300
400
500
600
COPPER HEAT SPREADER AREA (mm2)
700
Figure 39. Thermal Resistance RqJA vs. Copper Area
ORDERING INFORMATION
Package
Shipping†
NCV4299CD133R2G
SO−8
(Pb−Free)
2500 / Tape & Reel
NCV4299CD150R2G
SO−8
(Pb−Free)
2500 / Tape & Reel
NCV4299CD233R2G
SO−14
(Pb−Free)
2500 / Tape & Reel
NCV4299CD250R2G
SO−14
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
17
NCV4299C
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
18
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCV4299C
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
D
A
B
14
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
e
DETAIL A
h
A
X 45 _
M
A1
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Phone: 81−3−5817−1050
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19
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCV4299C/D
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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