NCV459MNWTBG

NCV459 4 A Single Load Switch for Low Voltage Rail The NCV459 is a power load switch with very low Ron NMOSFET controlled by external logic pin, allowing optimization of battery life, and portable device autonomy. Indeed, thanks to a best in class current consumption optimization with NMOS structure, leakage currents are drastically decreased. Offering optimized leakages isolation on the ICs connected on the battery. Output discharge path is proposed to eliminate residual voltages on the external components connected on output pin. Proposed in wide input voltage range from 0.75 V to 5.5 V, and a very small DFNW8 3x3 mm, 0.65 pitch package. www.onsemi.com MARKING DIAGRAM 1 1 Features • • • • • • • 45A ALYWG G DFNW8 CASE 507AB 45A = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) 0.75 V − 5.5 V Operating Range 23 mW N−MOSFET Vbias Rail Input DC Current up to 4 A Output Auto−Discharge Option Active High EN Pin DFNW8, 3 x 3 mm, 0.65 pitch PINOUT DIAGRAM GATE Typical Applications • ADAS System • Camera Module • Power Management EN OUT IN EPAD OUT IN GND VBIAS (Top View) ORDERING INFORMATION See detailed ordering and shipping information on page 10 of this data sheet. Figure 1. Typical Application Schematic © Semiconductor Components Industries, LLC, 2017 August, 2018 − Rev. 0 1 Publication Order Number: NCV459/D NCV459 Figure 2. Application Schematic with Vbias Connected to IN PIN FUNCTION DESCRIPTION Pin Name Pin Number Type Description GATE 1 INPUT OUT 2, 3 POWER Load−switch output pin. GND 4 POWER Ground connection. VBIAS 5 POWER External supply voltage input. IN 6, 7 POWER Load−switch input pin. EN 8 INPUT EPAD 9 POWER OUT pin slew rate control (trise). Enable input, logic high turns on power switch. Exposed pad, connect to ground potential. www.onsemi.com 2 NCV459 BLOCK DIAGRAMS IN: 6, 7 OUT : 2, 3 GATE : 1 Control logic & Charge Pump Gate driver GND : 4 VBIAS : 5 EN : 8 Figure 3. NCV459 Block Diagram www.onsemi.com 3 NCV459 MAXIMUM RATINGS Rating Symbol Value Unit VEN, VIN , VOUT, VBIAS, VGATE −0.3 to +6.5 V From IN to OUT Pins: Input/Output (Note 1) VIN , VOUT 0 to + 6.5 V Human Body Model (HBM) ESD Rating are (Note 2) ESD HBM 2000 V TJ −40 to + 125 °C Storage Temperature Range TSTG −40 to + 150 °C Moisture Sensitivity (Note 3) MSL Level 1 IN, OUT, EN, VBIAS, GATE Pins: (Note 1) Maximum Junction Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. According to JEDEC standard JESD22−A108. 2. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins. 3. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020. OPERATING CONDITIONS Symbol Parameter Max Unit 0.75 5.5 V 0 5.5 V Bias voltage (VBIAS ≥ best of VIN, VOUT) 1.2 5.5 V TA Ambient Temperature Range −40 CIN Decoupling input capacitor 100 nF COUT Decoupling output capacitor 100 nF RqJA Thermal Resistance Junction to Air IOUT DC current VIN Operational Power Supply VEN Enable Voltage VBIAS Conditions DFNW8 (Note 4) Min Typ 25 4 AC current 100 ms spike 4.5 A 5 A 15 Power Dissipation Rating (Note 5) 0.18 °C °C/W 106 AC current 1 ms @ 217 Hz PD +105 A W Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 4. Value based on 1s0p board with copper 650 mm2 (or 1 in2) of 1 oz thickness and FR4 PCB substrate 5. The maximum power dissipation (PD) is given by the following formula: PD + T JMAX * T A R qJA www.onsemi.com 4 NCV459 ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ between −40°C to +125°C for VIN between 0.75 V and 5.5 V, and VBIAS between 1.2 V and 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C, VIN = 3.3 V and VBIAS = 5 V (Unless otherwise noted). Parameter Symbol Conditions Min Typ Max 23 60 Unit POWER SWITCH IOUT = 200 mA, TA = 25°C VIN = VBIAS = 5.5 V TJ = 125°C IOUT = 200 mA, TA = 25°C VIN = VBIAS = 3.3 V TJ = 125°C IOUT = 200 mA, TA = 25°C VIN = VBIAS = 1.8 V RDS(on) Static drain−source on−state resistance for each rail IOUT = 200 mA, TA = 25°C VIN = VBIAS = 1.5 V 23 IOUT = 200 mA, TA = 25°C VIN = 0.8 V VBIAS = 1.2 V IOUT = 200 mA, TA = 25°C 24 mW 60 80 24 TJ = 125°C 60 80 24 60 EN = low 230 300 No cap on GATE pin 0.26 TJ = 125°C Output discharge path 60 80 TJ = 125°C VIN = 1.0 V VBIAS = 1.2 V 60 80 TJ = 125°C IOUT = 200 mA, TA = 25°C 60 80 23 TJ = 125°C VIN = VBIAS = 1.2 V RDIS 80 23 80 W TIMINGS (Note 6) TR Output rise time From 10% to 90% of VOUT Ten Enable time From En Vih to 10% of VOUT TF Fall Time. From 90% to 10% of VOUT Tdis TR VIN = 5 V CLOAD = 1 mF, RLOAD = 25 W Gate capacitor = 1 nF 1.5 Gate capacitor = 10 nF 15 Without Cgate 10 ms With 1 nF on Gate 60 ms 50 ms ms Disable time From EN to 90% Vout 75 No cap on GATE pin 0.25 Output rise time From 10% to 90% of VOUT Gate capacitor = 1 nF 1 Gate capacitor = 10 nF 10 Without Cgate 20 With 1 nF on Gate 114 Ten Enable time From En Vih to 10% of VOUT TF Output fall time From 90% to 10% of VOUT TR Output rise time From 10% to 90% of VOUT Ten Enable time From En Vih to 10% of VOUT TF Output fall time From 90% to 10% of VOUT VIN = 3.3 V CLOAD = 1 mF, RLOAD = 25 W 60 VIN = 1.8 V CLOAD = 1 mF, RLOAD = 25 W ms 0.5 ms 50 ms ms 120 ms No cap on GATE pin 0.12 Gate capacitor = 1 nF 0.6 Gate capacitor = 10 nF 5.5 Without Cgate 15 ms With 1 nF on Gate 85 ms 35 ms ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground www.onsemi.com 5 NCV459 ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ between −40°C to +125°C for VIN between 0.75 V and 5.5 V, and VBIAS between 1.2 V and 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C, VIN = 3.3 V and VBIAS = 5 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit TIMINGS (Note 6) Output rise time From 10% to 90% of VOUT TR Ten Enable time From En Vih to 10% of VOUT TF Output fall time No cap on GATE pin VIN = 1 V CLOAD = 1 mF, RLOAD = 25 W VIN = 1 V CLOAD = 1 mF, RLOAD = 25 W 0.01 Gate capacitor = 1 nF 1 Gate capacitor = 10 nF 13 ms Without Cgate 10 ms With 1 nF on Gate 0.4 ms 20 ms Logic VIH High−level input voltage VIL Low−level input voltage REN Pull down resistor 0.9 V 3 0.4 V 7 MW QUIESCENT CURRENT IVBIAS VBIAS = 3.3 V, EN = high 1.3 5 mA EN = high 0.01 0.3 mA EN = low, IN standby current, VIN = 3.3 V, with discharge path, TA = −40°C to 85°C 0.01 0.5 mA VBIAS = 3.3 V EN = low, TA = −40°C to 85°C 0.4 1.5 mA VBIAS Quiescent current IINQ IN Quiescent current ISTBIN Standby current IN ISTDVbias Standby current VBIAS Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground TIMINGS VIN EN VIH VIL VOUT 90% Vout 10% Vout TEN TR TDIS TON TOFF Figure 4. Enable, Rise and Fall Time www.onsemi.com 6 TF NCV459 TYPICAL CHARACTERISTICS 35 6.0 IOUT = 200 mA 5.8 30 5.6 20 15 −40°C 25°C 85°C 125°C 10 5 0 1 5.2 25°C 5.0 4.8 85°C 4.6 125°C 4.4 4.2 4.0 0 2 3 4 5 6 0 1 2 3 5 4 6 VIN (V) VEN (V) Figure 5. RDS(on) vs. VIN, Multi Junction Temperature Figure 6. Pull Down Resistor vs. VEN, Multi Junction Temperature 340 600 300 ISTD_BIAS (nA) 500 260 220 180 −40°C 25°C 85°C 125°C 140 400 300 200 −40°C 25°C 85°C 125°C 100 0 100 0 1 2 3 4 5 6 0 1 2 VIN (V) 4 5 Figure 8. BIAS Standby Current vs. VBIAS, Multi Junction Temperature 6 5 4 3 2 −40°C 25°C 85°C 125°C 1 0 0 3 VBIAS (V) Figure 7. Output Discharge Resistor vs. VIN, Multi Junction Temperature IQ_BIAS (mA) RDIS (W) −40°C 5.4 REN (MW) RDS(on) (mW) 25 1 2 3 4 5 VBIAS (V) Figure 9. BIAS Quiescent Current vs. VBIAS, Multi Junction Temperature www.onsemi.com 7 6 6 NCV459 TYPICAL CHARACTERISTICS 10k 10 TR (ms) 1k TEN (ms) −40°C 25°C 85°C 125°C −40°C 25°C 85°C 125°C 100 1.0 10 1 0.8 1.3 1.8 2.3 2.8 3.3 VIN (V) 3.8 4.3 4.8 0.1 0.8 5.3 Figure 10. Enable Time vs. VIN, Multi Junction Temperature (without Cgate) 1.3 1.8 2.3 2.8 3.3 VIN (V) 3.8 4.3 4.8 5.3 Figure 11. Rise Time vs. VIN, Multi Junction Temperature (without Cgate) 10k 1k 1k TF (ms) TDIS (ms) 100 100 10 −40°C 25°C 85°C 125°C 10 1 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 −40°C 25°C 85°C 125°C 1 0.8 5.3 VIN (V) 1.3 1.8 2.3 2.8 3.3 VIN (V) 3.8 4.3 4.8 Figure 13. Fall Time vs. VIN, Multi Junction Temperature, VBIAS and VIN Tied Together Rload 25 W Figure 12. Disable Time vs. VIN, Multi Junction Temperature, VBIAS and VIN Tied Together www.onsemi.com 8 5.3 NCV459 FUNCTIONAL DESCRIPTION Overview consumption is used on IN pin, allowing to improve power saving of the rail that must be isolated by the power switch. If Vbias rail is not available or used, Vbias pin and Vin pin can be connected together as close as possible the DUT. A minimum of 1.2 V is necessary to control the IC. It is recommended to connect external capacitor 10 mF due to better EMC immunity. The NCV459 are high side N channel MOSFET power distribution switch designed to isolate ICs connected on the LDO or DCDC supplies in order to save energy. The part can be used with a wide range of supply from 0.75 V to 5.5 V. Enable Input Enable pin is an active high. The path is opened when EN pin is tied low (disable), forcing NMOS switch off. The IN/OUT path is activated with a minimum of VBIAS min, Vin min and EN forced to high level. Output rise time − Gate control The NMOS is control with internal charge pump and driver. A minimum gate slew rate is internally set to avoid huge inrush current when EN is set from low to high. The default gate slew rate depends on Vin level. The higher Vin level, the longer rise time. In addition, an external capacitor can be connected between Gate pin and GND in order to slow down the gate rising. See electrical table for more details. Auto Discharge NMOS FET is placed between the output pin and GND, in order to discharge the application capacitor connected on OUT pin. The auto−discharge is activated when EN pin is set to low level (disable state). The discharge path ( Pull down NMOS) stays activated as long as EN pin is set at low level. In order to limit the current across the internal discharge Nmosfet, the typical value is set at RDIS value. Cin and Cout Capacitors 100 nF external capacitors must be connected as close as possible the DUT for noise immunity and better stability. In case of input hot plug (input voltage connected with fast slew rate − few ms − it’s strongly recommended to avoid big capacitor connected on the input. That allows to avoid input over voltage transients. Vbias Rail The core of the IC is supplied thanks to Vbias supply rail (common +5 V, 3.3 V, 1.8 V, 1.2 V). Indeed, no current www.onsemi.com 9 NCV459 APPLICATION INFORMATION Power Dissipation PD RDS(on) IOUT Main contributor in term of junction temperature is the power dissipation of the power MOSFET. Assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: P D + R DS(on) ǒIOUTǓ 2 = Power dissipation (W) = Power MOSFET on resistance (W) = Output current (A) TJ + PD TJ RqJA TA (eq. 1) R qJA ) T A (eq. 2) = Junction temperature (°C = Package thermal resistance (°C/W) = Ambient temperature (°C) ORDERING INFORMATION Device NCV459NMWTBG Marking Option Package Shipping† 45A Auto Discharge 230 W DFNW8 3 x 3 mm (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFNW8 3x3, 0.65P CASE 507AB ISSUE E 1 SCALE 2:1 DATE 02 JUL 2021 GENERIC MARKING DIAGRAM* 1 XXXXXX XXXXXX ALYWG G XXXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON14978G DFNW8 3x3, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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