NCV47821
LDO Regulator - Dual,
Adjustable Current Limit,
Diagnostic Features
3.3 V to 20 V
The NCV47821 dual channel LDO regulator with 200 mA per
channel is designed for use in harsh automotive environments. The
device has a high peak input voltage tolerance and reverse input voltage,
reverse bias, overcurrent and overtemperature protections. The
integrated current sense feature (adjustable by resistor connected to
CSO pin for each channel) provides diagnosis and system protection
functionality. The CSO pin output current creates voltage drop across
CSO resistor which is proportional to output current of each channel.
Extended diagnostic features in OFF state are also available and
controlled by dedicated input and output pins.
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MARKING
DIAGRAM
14
14
1
1
Features
•
•
•
•
•
•
•
•
Adjustable Outputs: 3.3 V to 20 V ±3% Output Voltage
Output Current per Channel: up to 200 mA
Two Independent Enable Inputs (3.3 V Logic Compatible)
Adjustable Current Limits: up to 300 mA
Protection Features:
♦ Current Limitation
♦ Thermal Shutdown
♦ Reverse Input Voltage and Reverse Bias Voltage
Diagnostic Features:
♦ Short To Battery (STB) and Open Load (OL) in OFF State
♦ Internal Components for OFF State Diagnostics
♦ Open Collector Flag Output
AEC−Q100 Grade 1 Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
NCV4
7821
ALYWG
G
TSSOP−14
Exposed Pad
CASE 948AW
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
Typical Applications
• Audio and Infotainment System
• Active Safety System
Cin
Vout1
Vin
R11
1 μF
ADJ1
CSO1
EN1
C CSO1
Diagnostic Enable Input
DE
Diagnostic Channel Select Input
NCV47821
(Dual LDO )
To A /D
R CSO1
Cout1
10 μF
R12
1 μF
Error Flag Output (Open Collector)
EF
CS
Cb1*
Vout2
R21
ADJ2
CSO2
EN2
GND
C CSO2
Cb2*
To A /D
R CSO2
Cout2
10 μF
R22
1 μF
C b1* and Cb2* are optional for stability with ceramic output capacitors
Figure 1. Application Schematic
(See Application Section for More Details)
© Semiconductor Components Industries, LLC, 2017
September, 2019 − Rev. 2
1
Publication Order Number:
NCV47821/D
NCV47821
IPU1 10 mA
IPU1_ON
Vin
Vout1
VOLTAGE
REFERENCE
EN1
RPD_EN1
780 kΩ
ENABLE
VREF 1
VREF 2
VREF _OFF
EN1
ICSO1 = Iout1 / 100
PASS DEVICE 1
AND
CURRENT MIRROR
VREF 2
2.55 V
+
−
SATURATION
PROTECTION
CSO1
+
THERMAL
SHUTDOWN
OC1_ON
−
PD1_ON
0.95x
V REF 2
RPD11
500 kΩ
+
STB1_OL1_OFF
DE
CS
RPD_CS
780 kΩ
IPU1_ON
IPU2_ON
EN1
EN2
RPD_DE
780 kΩ DIAGNOSTIC
CONTROL
LOGIC
PD1_ON
PD2_ON
EA1
−
RPD12
100 kΩ
VREF_OFF
+
VREF 1
1.265 V
−
ADJ1
EF
OC1_ON
OC2_ON
STB1_OL1_OFF
STB2_OL2_OFF
IPU2 10 mA
IPU2_ON
Vin
Vout2
ICSO2 = Iout2 / 100
EN2
RPD_EN2
780 kΩ
ENABLE
EN2
+
PASS DEVICE 2
AND
CURRENT MIRROR
VREF 2
2.55 V
−
SATURATION
PROTECTION
CSO2
+
THERMAL
SHUTDOWN
OC2_ON
−
PD2_ON
0.95x
V REF 2
RPD21
500 kΩ
+
STB2_OL2_OFF
GND
EA2
Figure 2. Simplified Block Diagram
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2
−
RPD22
100 kΩ
VREF_OFF
+
VREF 1
1.265 V
−
ADJ2
NCV47821
1
14
V in
V out1
CSO1
ADJ1
CS
EN1
EPAD
GND
EF
DE
EN2
ADJ2
CSO2
V in
V out2
TSSOP−14 EPAD
(Top View)
Figure 3. Pin Connections
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
TSSOP−14
EPAD
Pin Name
1
Vin
2
CSO1
3
EN1
Enable Input 1; low level disables the Channel 1. (Used also for OFF state diagnostics control for
Channel 1)
4
GND
Power Supply Ground.
5
EN2
Enable Input 2; low level disables the Channel 2. (Used also for OFF state diagnostics control for
Channel 2)
6
CSO2
Description
Power Supply Input for Channel 1 and supply of control circuits of whole chip. At least 4.4 V power
supply must be used for proper IC functionality.
Current Sense Output 1, Current Limit setting and Output Current value information. See Application
Section for more details.
Current Sense Output 2, Current Limit setting and Output Current value information. See Application
Section for more details.
7
Vin
8
Vout2
Power Supply Input for Channel 2. Connect to pin 1 or different power supply rail.
Regulated Output Voltage 2.
9
ADJ2
Adjustable Voltage Setting Input 2. See Application Section for more details.
10
DE
Diagnostic Enable Input.
11
EF
Error Flag (Open Collector) Output. Active Low.
12
CS
Channel Select Input for OFF state diagnostics. Set CS = Low for OFF state diagnostics of Channel 1. Set CS = High for OFF state diagnostics of Channel 2. Corresponding EN pin has to be used
for diagnostics control (see Application Information section for more details).
13
ADJ1
Adjustable Voltage Setting Input 1. See Application Section for more details.
14
Vout1
Regulated Output Voltage 1.
EPAD
EPAD
Exposed Pad is connected to Ground. Connect to GND plane on PCB.
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NCV47821
Table 2. MAXIMUM RATINGS
Rating
Symbol
Min
Max
Unit
Input Voltage DC
Vin
−42
45
V
Input Voltage (Note 1)
Load Dump − Suppressed
Us*
−
60
V
Enable Input Voltage
VEN1,2
−42
45
V
ADJ Input Voltage
VADJ1,2
−0.3
10
V
CSO Voltage
VCSO1,2
−0.3
7
V
VDE, VCS VEF
−0.3
7
V
Vout1,2
−1
40
V
Junction Temperature
TJ
−40
150
°C
Storage Temperature
TSTG
−55
150
°C
DE, CS and EF Voltages
Output Voltage
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class C according to ISO16750−1.
Table 3. ESD CAPABILITY (Note 2)
Rating
ESD Capability, Human Body Model
Symbol
Min
Max
Unit
ESDHBM
−2
2
kV
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010)
Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes < 50 mm2 due
to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current waveform
characteristic defined in JEDEC JS−002−2014.
Table 4. LEAD SOLDERING TEMPERATURE AND MSL (Note 3)
Symbol
Rating
Moisture Sensitivity Level
Min
MSL
Max
1
Unit
−
3. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS (Note 4)
Symbol
Rating
Value
Thermal Characteristics (single layer PCB)
Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Lead (Note 5)
RθJA
RψJL
52
9.0
Thermal Characteristics (4 layers PCB)
Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Lead (Note 5)
RθJA
RψJL
31
10
Unit
°C/W
°C/W
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. Single layer − according to JEDEC51.3,
4 layers − according to JEDEC51.7
Table 5. RECOMMENDED OPERATING RANGES
Rating
Input Voltage (Note 6)
Nominal Output Voltages
Output Current Limit (Note 7)
Junction Temperature
Current Sense Output (CSO) Capacitor
Symbol
Min
Max
Unit
Vin
4.4
40
V
Vout_nom1,2
3.3
20
V
ILIM1,2
10
300
mA
TJ
−40
150
°C
CCSO1,2
1
4.7
mF
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Minimum Vin = 4.4 V or (Vout1,2 + 0.5 V), whichever is higher.
7. Corresponding RCSO1,2 is in range from 25.5 kW down to 850 W.
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4
NCV47821
Table 6. ELECTRICAL CHARACTERISTICS Vin = 13.5 V, VEN1,2 = 3.3 V, VDE = 0 V, RCSO1,2 = 0 W, CCSO1,2 = 1 mF, Cin = 1 mF,
Cout1,2 = 10 mF, Min and Max values are valid for temperature range −40°C v TJ v +150°C unless noted otherwise and are guaranteed
by test, design or statistical correlation. Typical values are referenced to TJ = 25°C (Note 8)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
−3
−
+3
−
0.1
1.0
−
0.4
1.4
VDO1,2
−
250
500
mV
IDIS
−
0.1
10
mA
REGULATOR OUTPUTS
Output Voltage (Accuracy %) (Note 9)
Vin = Vin_min to 40 V
Iout1,2 = 5 mA to 200 mA
Vout1,2
Line Regulation (Note 9)
Vin = Vin_min to (Vout_nom1,2 + 20 V)
Iout1,2 = 5 mA
Regline1,2
Load Regulation
Vin = (Vout_nom1,2 + 8.5 V)
Iout1,2 = 5 mA to 200 mA
Regload1,2
Dropout Voltage (Note 10)
Vout_nom1,2 = 5 V, Iout1,2 = 200 mA
VDO1,2 = Vin − Vout1,2
%
%
%
DISABLE AND QUIESCENT CURRENTS
Disable Current
VEN1,2 = 0 V, Vout_nom1,2 = 5 V,
−40°C v TJ v +125°C
Quiescent Current, Iq = Iin − (Iout1 +Iout2)
Iout1 = Iout2 = 500 mA, Vin = (Vout_nom + 8.5 V)
Iq
−
0.6
1.0
mA
Quiescent Current, Iq = Iin – (Iout1 +Iout2)
Iout1 = Iout2 = 200 mA, Vin = (Vout_nom + 8.5 V)
Iq
−
15.5
25
mA
ILIM1,2
300
−
−
mA
PSRR1,2
−
75
−
dB
Vn1,2
−
137
−
mVrms
0.99
−
1.8
1.9
−
2.31
2
8
20
−
1.7
−
2.448
(−4%)
2.55
2.652
(+4%)
−
−
3.3
CURRENT LIMIT PROTECTION
Current Limit
Vout1,2 = 0.9 x Vout_nom1,2
Vin = (Vout_nom1,2 + 8.5 V)
PSRR & NOISE
Power Supply Ripple Rejection (Note 11) f = 100 Hz, 0.5 Vp−p1,2
Output Noise Voltage (Note 11)
f = 10 Hz to 100 kHz, Cb1,2 = 10 nF
ENABLE
Enable Input Threshold Voltage
Logic Low (OFF)
Logic High (ON)
Vout1,2 v 0.1 V
Vout1,2 w 0.9 x Vout_nom1,2 (Vout_nom1,2 = 5 V)
Enable Input Current
VEN1,2 = 3.3 V, Vout_nom1,2 = 5 V
Turn On Time
from Enable ON to 90 % of Vout
Iout1,2 = 100 mA, Cb1,2 = 10 nF,
Rn1 = 82 kW, Rn2 = 27 kW
Vth(EN1,2)
IEN1,2
ton
V
mA
ms
OUTPUT CURRENT SENSE
CSO Voltage Level at Current Limit
Vout1,2 = 0.9 x Vout_nom1,2,
(Vout_nom1,2 = 5 V) RCSO1,2 = 1 kW
VCSO_Ilim1,2
V
CSO Transient Voltage Level
CCSO1,2 = 4.7 mF, RCSO1,2 = 1 kW
Iout1,2 pulse from 10 mA to 300 mA, tr = 1 ms
VCSO1,2
Output Current to CSO Current Ratio
(Note 11, 12)
VCSO1,2 = 2 V, Iout1,2 = 1 mA to 10 mA
(Vout_nom1,2 = 5 V)
Iout1,2/
ICSO1,2
−
(−5%)
98
−
(+5%)
−
Output Current to CSO Current Ratio
(Note 12)
VCSO1,2 = 2 V, Iout1,2 = 10 mA to 300 mA
(Vout_nom1,2 = 5 V)
Iout1,2/
ICSO1,2
−
(−5%)
100
−
(+5%)
−
CSO Current at no Load Current
VCSO1,2 = 0 V, Iout1,2 = 0 mA,
(Vout_nom1,2 = 5 V)
ICSO_off1,2
−
−
10
mA
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [ TJ. Low duty
cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
9. Minimum input voltage Vin_min is 4.4 V or (Vout_nom1,2 + 1 V) whichever is higher. Vout_nom1,2 measured at ADJ1,2 pin due to excluding
Rn1 and Rn2 accuracy.
10. Measured when the output voltage Vout1,2 has dropped by 2% of Vout_nom1,2 from the nominal valued obtained at Vin = Vout1,2 + 8.5 V.
11. Values based on design and/or characterization.
12. Not guaranteed in dropout.
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NCV47821
Table 6. ELECTRICAL CHARACTERISTICS Vin = 13.5 V, VEN1,2 = 3.3 V, VDE = 0 V, RCSO1,2 = 0 W, CCSO1,2 = 1 mF, Cin = 1 mF,
Cout1,2 = 10 mF, Min and Max values are valid for temperature range −40°C v TJ v +150°C unless noted otherwise and are guaranteed
by test, design or statistical correlation. Typical values are referenced to TJ = 25°C (Note 8)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VOC1,2
92
95
98
% of
VCSO_
DIAGNOSTICS
Overcurrent Voltage Level Threshold
Vout_nom1,2 = 5 V, RCSO1,2 = 1 kW
Ilim1,2
Short To Battery (STB) Voltage
Threshold in OFF state
Vin = 4.4 V to 18 V, Iout1 = Iout2 = 0 mA,
VDE = 3.3 V
Open Load (OL) Current Threshold
in OFF state
Vin = 4.4 V to 18 V, VDE = 3.3 V
VSTB1,2
2
3
4
V
IOL1,2
5.0
10
25
mA
0.99
−
1.8
1.9
−
2.31
0.99
−
1.8
1.9
−
2.31
VEF_Low
−
0.04
0.4
V
TSD1,2
150
175
195
°C
Diagnostics Enable Threshold Voltage
Logic Low
Logic High
Vth(DE)
Channel Select Threshold Voltage
Logic Low
Logic High
Vth(CS)
Error Flag Low Voltage
IEF = −1 mA
V
V
THERMAL SHUTDOWN
Thermal Shutdown Temperature
(Note 11)
Iout1 = Iout2 = 5 mA, Vout_nom1,2 = 5 V,
each channel measured separately
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [ TJ. Low duty
cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
9. Minimum input voltage Vin_min is 4.4 V or (Vout_nom1,2 + 1 V) whichever is higher. Vout_nom1,2 measured at ADJ1,2 pin due to excluding
Rn1 and Rn2 accuracy.
10. Measured when the output voltage Vout1,2 has dropped by 2% of Vout_nom1,2 from the nominal valued obtained at Vin = Vout1,2 + 8.5 V.
11. Values based on design and/or characterization.
12. Not guaranteed in dropout.
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NCV47821
TYPICAL CHARACTERISTICS
800
Vin = 13.5 V
Iout1,2 = 5 mA
1.29
Iq, QUIESCENT CURRENT (mA)
VREF1, REFERENCE VOLTAGE (V)
1.30
1.28
1.27
1.26
1.25
1.24
1.23
−40 −20
0
20
40
60
80
300
TJ = 25°C
Iout1,2 = 500 mA
Vout_nom1,2 = 5 V
200
100
0
5
10
15
20
25
30
35
40
VIN, INPUT VOLTAGE (V)
Figure 4. Reference Voltage vs. Temperature
Figure 5. Quiescent Current vs. Input Voltage
TJ = 25°C
Iout1,2 = 5 mA
Iin, INPUT CURRENT (mA)
VREF1, REFERENCE VOLTAGE (V)
400
TJ, JUNCTION TEMPERATURE (°C)
1.0
0.8
0.6
0.4
0.2
0
1
2
3
4
−3
−4
−5
−35
−30
−25
−20
−15
−10
Figure 6. Reference Voltage vs. Input Voltage
Figure 7. Input Current vs. Input Voltage
(Reverse Input Voltage)
ILIM1,2, OUTPUT CURRENT LIMIT (A)
TJ = 150°C
300
TJ = 25°C
250
200
TJ = −40°C
150
100
50
50
100
150
200
250
300
350
1.15
Vout_nom1,2 = 3.3 V
Vout1,2 = 90% of Vout_nom1,2 V
1.10
1.05
TJ = 25°C
TJ = −40°C
1.00
0.95
TJ = 150°C
0.90
0.85
0.80
0.75
0.70
0
5
10
15
20
25
30
35
40
Iout1,2, OUTPUT CURRENT (mA)
VIN, INPUT VOLTAGE (V)
Figure 8. Dropout Voltage vs. Output Current
Figure 9. Output Current Limit vs. Input
Voltage
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0
−5
VIN, INPUT VOLTAGE (V)
350
0
−2
VIN, INPUT VOLTAGE (V)
Vout_nom1,2 = 5 V
400
TJ = 25°C
Rout1,2 = 3.3 kW
Vout_nom1,2 = 3.3 V
−1
−6
−45 −40
5
450
VDO1,2, DROPOUT VOLTAGE (mV)
500
0
1.2
0
600
0
100 120 140 160
1.4
0
700
45
NCV47821
350
3.0
Vout1,2 = 3.3 V to 20 V
300
250
200
150
100
50
0
0
2
4
6
8
2.0
1.5
1.0
0.5
0
10 12 14 16 18 20 22 24 26
20
30
40
50
60
70
80
90 100 110
Figure 10. Output Current Limit vs. RCSO
Figure 11. Output Current (% of ILIM) vs. CSO
Voltage
30
Iq, QUIESCENT CURRENT (mA)
1.5
1.0
0.5
0
2.5
112
110
5.0
7.5
10.0
12.5
15.0
17.5
20
15
10
5
0
20.0
0
40
80
120
160
200
240
280
Iout1,2, OUTPUT CURRENT (mA)
Iout1,2, OUTPUT CURRENT (mA)
Figure 12. Quiescent Current vs. Output
Current (Low Load)
Figure 13. Quiescent Current vs. Output
Current (High Load)
100
TJ = 25°C
Vin = Vout_nom1,2 + 8.5 V
108
106
104
102
100
98
96
94
92
90
88
TJ = 25°C
Vin = Vout_nom1,2 + 8.5 V
25
Iout1,2/ICSO1,2, OUTPUT CURRENT
TO CSO CURRENT RATIO (−)
Iq, QUIESCENT CURRENT (mA)
10
Iout1,2, OUTPUT CURRENT (% of ILIM1,2)
TJ = 25°C
Vin = Vout_nom1,2 + 8.5 V
Iout1,2/ICSO1,2, OUTPUT CURRENT
TO CSO CURRENT RATIO (−)
0
RCSO1,2 (kW)
2.0
0
Vout1,2 = 3.3 V to 20 V
TJ = −40°C to 150°C
ILIM1,2, = 10 mA to 300 mA
2.5
VCSO1,2, CSO VOLTAGE (V)
ILIM1,2, OUTPUT CURRENT LIMIT (mA)
TYPICAL CHARACTERISTICS
1
10
100
1000
95
90
85
80
75
70
65
TJ = 25°C
Vin = 4.5 V
Vout_nom1,2 = 5 V
60
55
50
1
10
100
1000
Iout1,2, OUTPUT CURRENT (mA)
Iout1,2, OUTPUT CURRENT (mA)
Figure 14. Output Current to CSO Current
Ratio vs. Output Current
Figure 15. Output Current to CSO Current
Ratio vs. Output Current (in dropout)
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NCV47821
TYPICAL CHARACTERISTICS
100
3000
Vn1,2, NOISE DENSITY (nV/Hz1/2)
Unstable Region
(Area above curves)
Vout_nom1,2 = 20 V
10
Vout_nom1,2 = 3.3 V
1
TJ = 25°C
Vin = Vout_nom1,2 + 8.5 V
Cout1,2 = 10 mF − 100 mF
Cb1,2 = none
0.1
0.01
0
50
Stable Region
(Area under curves)
100
150
2500
2000
1500
1000
500
0
200
TJ = 25°C
Vin = 12 V
Cb1,2 = 10 nF
Iout1,2 = 5 mA
10
100
1000
10,000
Iout1,2, OUTPUT CURRENT (mA)
FREQUENCY (Hz)
Figure 16. Output Capacitor Stability Region
vs. Output Current
Figure 17. Noise vs. Frequency
100
90
Iout1,2 = 5 mA
80
PSRR1,2 (dB)
ESR (W)
Vout_nom1,2 = 5 V
f = 10 Hz − 100 kHz
Vn1,2 = 182 mV
70
Iout1,2 = 200 mA
60
50
40
30
20
TA = 25°C
Vin = 13.5 V DC + 0.5 VPP AC
Vout_nom1,2 = 5 V
10
100
1000
10,000
FREQUENCY (Hz)
Figure 18. PSRR vs. Frequency
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100,000
100,000
NCV47821
DEFINITIONS
General
Current Limit
All measurements are performed using short pulse low
duty cycle techniques to maintain junction temperature as
close as possible to ambient temperature.
Current Limit is value of output current by which output
voltage drops below 90% of its nominal value.
PSRR
Power Supply Rejection Ratio is defined as ratio of output
voltage and input voltage ripple. It is measured in decibels
(dB).
Output voltage
The output voltage parameter is defined for specific
temperature, input voltage and output current values or
specified over Line, Load and Temperature ranges.
Line Transient Response
Typical output voltage overshoot and undershoot
response when the input voltage is excited with a given
slope.
Line Regulation
The change in output voltage for a change in input voltage
measured for specific output current over operating ambient
temperature range.
Load Transient Response
Typical output voltage overshoot and undershoot
response when the output current is excited with a given
slope between low-load and high-load conditions.
Load Regulation
The change in output voltage for a change in output
current measured for specific input voltage over operating
ambient temperature range.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 175°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.
Dropout Voltage
The input to output differential at which the regulator
output no longer maintains regulation against further
reductions in input voltage. It is measured when the output
drops 2% of Vout_nom below its nominal value. The junction
temperature, load current, and minimum input supply
requirements affect the dropout level.
Maximum Package Power Dissipation
The power dissipation level is maximum allowed power
dissipation for particular package or power dissipation at
which the junction temperature reaches its maximum
operating value, whichever is lower.
Quiescent and Disable Currents
Quiescent Current (Iq) is the difference between the input
current (measured through the LDO input pin) and the
output load current. If Enable pin is set to LOW the regulator
reduces its internal bias and shuts off the output, this term is
called the disable current (IDIS).
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10
NCV47821
APPLICATIONS INFORMATION
Circuit Description
to maintain junction temperature close to ambient
temperature.
The NCV47821 is an integrated dual low dropout
regulator that provides a regulated voltage at 200 mA to each
output. It is enabled with an input to the enable pin. The
regulator voltage is provided by a PNP pass transistor
controlled by an error amplifier with a bandgap reference,
which gives it the lowest possible dropout voltage. The
output current capability of the LDO is 200 mA per output
and the base drive quiescent current is controlled to prevent
oversaturation when the input voltage is low or when the
output is overloaded. The integrated current sense feature
provides diagnosis and system protection functionality. The
current limit of the device is adjustable by resistor connected
to CSO pin. Voltage on CSO pin is proportional to output
current. The regulator is protected by both current limit and
thermal shutdown. Thermal shutdown occurs above 150°C
to protect the IC during overloads and extreme ambient
temperatures.
Calculating Bypass Capacitor
If improved stability (reducing output voltage ringing
during transients) is demanded, connect the bypass
capacitor Cb1,2 between Adjustable Input pin and Vout1,2 pin
according to Applications circuit at Figure 1. Parallel
combination of bypass capacitor Cb1,2 with the feedback
resistor Rn1 contributes in the device transfer function as an
additional zero and affects the device loop stability,
therefore its value must be optimized. Attention to the
Output Capacitor value and its ESR must be paid. See also
Stability in High Speed Linear LDO Regulators Application
Note, AND8037/D for more information. Optimal value of
bypass capacitor is given by following expression
C bn +
2
p
1
fz
R n1
(F)
(eq. 1)
where
Rn1
fz
Regulator
the upper feedback resistor
the frequency of the zero added into the device
transfer function by Rn1 and Cb1 external
components.
Set the Rn1 resistor according to output voltage requirement.
Chose the fz with regard on the output capacitance Cout1,2,
refer to the table below.
The error amplifier compares the reference voltage to a
sample of the output voltage (Vout1,2) and drives the base of
a PNP series pass transistor via a buffer. The reference is a
bandgap design to give it a temperature stable output.
Saturation control of the PNP is a function of the load current
and input voltage. Oversaturation of the output power
device is prevented, and quiescent current in the ground pin
is minimized.
Regulator Stability Considerations
The input capacitor (Cin) is necessary to stabilize the input
impedance to avoid voltage line influences. The output
capacitor (Cout1,2) helps determine three main
characteristics of a linear regulator: startup delay, load
transient response and loop stability. The capacitor value
and type should be based on cost, availability, size and
temperature constraints. The aluminum electrolytic
capacitor is the least expensive solution, but, if the circuit
operates at low temperatures (−25°C to −40°C), both the
value and ESR of the capacitor will vary considerably. The
capacitor manufacturer’s data sheet usually provides this
information. The value for the output capacitor Cout1,2,
shown in Figure 1 should work for most applications; see
also Figure 16 for output stability at various load and Output
Capacitor ESR conditions. Stable region of ESR in
Figure 16 shows ESR values at which the LDO output
voltage does not have any permanent oscillations at any
dynamic changes of output load current. Marginal ESR is
the value at which the output voltage waving is fully damped
during four periods after the load change and no oscillation
is further observable.
ESR characteristics were measured with ceramic
capacitors and additional series resistors to emulate ESR.
Low duty cycle pulse load current technique has been used
Cout1,2 (mF)
10
22
47
100
fZ range (kHz)
max 19
max 19
N/A*
N/A*
NOTE:
* For Cout1,2 = 47 mF and higher, Cb1,2 capacitors are not
needed for stability improvement. Cb1,2 capacitors are
useful for reduction start up overshoot and noise
reduction. See electrical characteristic table.
Ceramic capacitors and its part numbers listed bellow
have been used as low ESR output capacitors Cout1,2 from
the table above to define the frequency ranges of additional
zero required for stability:
GRM31CR71C106KAC7 (10 mF, 16 V, X7R, 1206)
GRM32ER71C226KE18 (22 mF, 16 V, X7R, 1210)
GRM32ER61C476ME15 (47 mF, 16 V, X5R, 1210)
GRM32ER60J107ME20 (100 mF, 6.3 V, X5R, 1210)
Enable Inputs
An enable pin is used to turn a channel on or off. By
holding the pin down to a voltage less than 0.99 V, the output
of the channel will be turned off. When the voltage on the
enable pin is greater than 2.31 V, the output of the channel
will be enabled to power its output to the regulated output
voltage. The enable pins may be connected directly to the
input pin to give constant enable to the output channel.
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11
NCV47821
Setting the Output Voltage
RATIOmax − maximum value of Output Current to
CSO Current Ratio from electrical
characteristics table and particular output
current range
VCSO1,2_min minimum value of CSO Voltage Level at
Current Limit from electrical characteristics
table
VCSO1,2_max maximum value of CSO Voltage Level at
Current Limit from electrical characteristics
table
RCSO1,2_min − minimum value of RCSO1,2 with respect
its accuracy
RCSO1,2_max − maximum value of RCSO1,2 with respect
its accuracy
Designers should consider the tolerance of RCSO1,2
during the design phase.
The output voltage range can be set between 3.3 V and
20 V. This is accomplished with an external resistor divider
feeding back the voltage to the IC back to the error amplifier
by the voltage adjust pin ADJ. The internal reference voltage
is set to a temperature stable reference (VREF1) of 1.265 V.
The output voltage is calculated from the following formula.
Ignoring the bias current into the ADJ pin:
ǒ
V out_nom_n + V REF1 1 )
Ǔ
R n1
R n2
(eq. 2)
Use Rn2 < 50 kW to avoid significant voltage output errors
due to ADJ bias current.
Designers should consider the tolerance of Rn1 and Rn2
during the design phase.
Setting the Output Current Limit
The output current limit can be set up to 300 mA by
external resistor RCSO1,2 (see Figure 1). Capacitor CCSO of
1 mF in parallel with RCSO is required for stability of current
limit control circuitry (see Figure 1).
ǒ
V CSO1,2 + I out1,2 R CSO1,2
I LIM1,2 + 100
1
Ǔ
1
100
The NCV47821 contains also circuitry for OFF state
diagnostics for Short to Battery (STB) and Open Load (OL).
There are internal current sources, Pull−Up and Pull Down
resistors which provide additional cost savings for overall
application by excluding external components and their
assembly cost and saving PCB space and safe control IOs of
a Microcontroller Unit (MCU).
Simplified functional schematic and truth table is shown
in Figure 19 and related flowchart in Figure 20.
(eq. 3)
2.55
R CSO1,2
(eq. 4)
2.55
I LIM1,2
(eq. 5)
R CSO1,2 + 100
1
Diagnostic in OFF State
where
RCSO1,2 − current limit setting resistor
VCSO1,2 voltage at CSO pin proportional to Iout1,2
ILIM1,2 − current limit value
Iout1,2 − output current actual value
CSO pin provides information about output current actual
value. The CSO voltage is proportional to output current
according to Equation 3.
Once output current reaches its limit value (ILIM1,2) set by
external resistor RCSO than voltage at CSO pin is typically
2.55 V. Calculations of ILIM1,2 or RCSO1,2 values can be
done using Equation 4 and Equation 5, respectively.
Minimum and maximum value of Output Current Limit can
be calculated according Equation 6 and 7.
I LIM1,2_min + RATIO min
I LIM1,2_max + RATIO max
V CSO1,2_min
R CSO1,2_max
V CSO1,2_max
R CSO1,2_min
I PU
Current source enabled via EN and DE pins
PASS DEVICE is OFF in Diagnostics
Mode in OFF state
Vin
Vout
RPD1
+
EN
Comparator active only in Diagnostic
state (DE = H).
− VREF_OFF
RPD2
DE
EF
Digital Diagnostics:
to MCU’s digital input
with pull−up resistor
to MCU’s DIO supply rail
EN – Enable (Logic Input)
DE – Diagnostics Enable(Logic Input)
EF – Error Flag Output (Open Collector Output)
EN
L
L
(eq. 6)
DE IPU EF
Vout
L OFF HZ Unknown
H OFF L V out > Vout_OFF
Diagnostic Status/Action
None (Diagnostics OFF)
Short to Battery (STB)
Check for Open Load (OL)
L
H
OFF HZ V out < Vout_OFF
H
H
ON
H
H
ON
L
V out > Vout_OFF
Open Load (OL)
HZ V out < Vout_OFF No Failure (V out close to 0 V)
Figure 19. Simplified Functional Diagram of OFF
State Diagnostics (STB and OL)
(eq. 7)
where
RATIOmin − minimum value of Output Current to
CSO Current Ratio from electrical
characteristics table and particular output
current range
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12
NCV47821
The diagnostics in OFF state shall be performed for each
channel separately. For diagnostics of Channel 1 the input
CS pin has to be put logic low, for diagnostics of Channel 2
the input CS pin has to be put logic high. Corresponding EN
pin has to be used for control (EN1 for Channel 1 and EN2
for Channel 2). For detailed information see Diagnostic
Features Truth Table in Figure 21.
Start
Diag. OFF. Set
EN = L & DE = L
Diag. ON. Set
EN = L & DE = H
Diagnostic in ON State
HZ
EF = ?
Diagnostic in ON State provides information about
Overcurrent or Short to Ground failures, during which the
EF output is in logic low state. The diagnostics in ON state
shall be performed for each channel separately. For
diagnostics of Channel 1 the input CS pin has to be put logic
low, for diagnostics of Channel 2 the input CS pin has to be
put logic high. For detailed information see Diagnostic
Features Truth Table in Figure 21.
L
IPU ON. Set
EN = H & DE = H
HZ
No Failure
EF = ?
L
Open Load
Short to Battery
Figure 20. Flowchart for Diagnostics in OFF State
Figure 21. Diagnostic Features Truth Table
13. State of EN pin of appropriate channel
14. CS = L means CH1 diagnostics and CS = H means CH2 diagnostics in OFF state (DE = H) via EF output, appropriate EN pin is used for
turning internal switch ON and OFF (e.g. when DE = H and CS = L and EN1 = L then IPU1 is OFF, when DE = H and CS = L and EN1 =
H then IPU1 is ON)
15. Internal current source turned OFF (between Vout and Vin of appropriate channel)
16. Internal current source turned ON (between Vout and Vin of appropriate channel)
17. CS = L means CH1 diagnostics and CS = H means CH2 diagnostics in ON state (e.g. when CS = L and EF = L then CH1 has Overcurrent
or Short to Ground failure, when CS = H and EF = L then CH1 has Overcurrent or Short to Ground failure)
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13
NCV47821
Thermal Considerations
As power in the device increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the device has good thermal conductivity through the PCB,
the junction temperature will be relatively low with high
power applications. The maximum dissipation the device
can handle is given by:
R qJA
RqJA, THERMAL RESISTANCE (°C/W)
P D(MAX) +
ƪTJ(MAX) * TAƫ
130
120
(eq. 8)
Since TJ is not recommended to exceed 150°C, then the
device soldered on 645 mm2, 1 oz copper area, FR4 can
dissipate up to 2.38 W when the ambient temperature (TA)
is 25°C. See Figure 22 for RqJA versus PCB area. The power
dissipated by the device can be calculated from the
following equations:
70
60
2 oz, Single Layer
50
40
1 oz, 4 Layer
30
20
2 oz, 4 Layer
0
100
200
300
400
500
600
700
Hints
Vin and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator
to malfunction. Place external components, especially the
output capacitor, as close as possible to the device and make
traces as short as possible.
or
V in(MAX) [
1 oz, Single Layer
80
Figure 22. Thermal Resistance vs. PCB Copper Area
(eq. 9)
I out1Ǔ ) ǒV out2
90
COPPER HEAT SPREADER AREA (mm2)
P D [ V inǒI q@I out1,2Ǔ ) I out1ǒV in−V out1Ǔ ) I out2ǒV in−V out2Ǔ
P D(MAX) ) ǒV out1
110
100
(eq.
Ǔ
I out210)
I out1 ) I out2 ) I q
ORDERING INFORMATION
Device
NCV47821PAAJR2G
Output Voltage
Marking
Package
Shipping†
Adjustable
Line1: NCV4
Line2: 7821
TSSOP−14 Exposed Pad
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D
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14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 EP
CASE 948AW
ISSUE C
14
1
SCALE 1:1
B
NOTE 6
14
DATE 09 OCT 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.07 mm MAX. AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD IS 0.07.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 mm PER SIDE. DIMENSION D IS DETERMINED AT
DATUM H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.25 mm PER
SIDE. DIMENSION E1 IS DETERMINED AT DATUM H.
6. DATUMS A AND B ARE DETERMINED AT DATUM H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM
THE SEATING PLANE TO THE LOWEST POINT ON THE
PACKAGE BODY.
8. SECTION B−B TO BE DETERMINED AT 0.10 TO 0.25 mm
FROM THE LEAD TIP.
b
8
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉ
b1
E1
c1
E
NOTE 5
SECTION B−B
c
PIN 1
REFERENCE
1
7
0.20 C B A
e
2X 14 TIPS
TOP VIEW
NOTE 6
A
D
A2
NOTE 4
0.05 C
0.10 C
A
0.10 C B
S
A
S
DETAIL A
B
14X b
14X
NOTE 8
C
M
SEATING
PLANE c
B
NOTE 3
END VIEW
SIDE VIEW
D2
H
E2
L2
A1
L
NOTE 7
C
DETAIL A
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
3.40
14X
1.15
GAUGE
PLANE
DIM
A
A1
A2
b
b1
c
c1
D
D2
E
E1
E2
e
L
L2
M
MILLIMETERS
MIN
MAX
−−−−
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.19
0.25
0.09
0.20
0.09
0.16
4.90
5.10
3.09
3.62
6.40 BSC
4.30
4.50
2.69
3.22
0.65 BSC
0.45
0.75
0.25 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
14
XXXX
XXXX
ALYWG
G
1
3.06
6.70
1
0.65
PITCH
14X
0.42
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON66474E
TSSOP−14 EP, 5.0X4.4
XXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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