NCV4949CDR2G

NCV4949C Voltage Regulator - Low Dropout, Reset, Sense 100 mA, 5.0 V The NCV4949C is a monolithic integrated 5.0 V voltage regulator with a very low dropout and additional functions such as reset and an uncommitted voltage sense comparator. It is designed for supplying microcontroller/microprocessor controlled systems particularly in automotive applications. The NCV4949C has improved reset behavior for lower input and output voltage levels. www.onsemi.com MARKING DIAGRAMS 8 Features • • • • • • • • • • SOIC−8 D SUFFIX CASE 751−07 8 Operating DC Supply Voltage Range 5.5 V to 40 V High Precision Output Voltage 5.0 V ±1% Output Current Capability Up to 100 mA Very Low Dropout Voltage Less Than 0.4 V Reset Circuit Sensing The Output Voltage Programmable Reset Pulse Delay Voltage Sense Comparator Fault Protection, +60 V Peak Transient Voltage, −40 V Reverse Voltage, Short Circuit, Thermal Overload NCV Prefix for Automotive and Other Applications Requiring Site and Change Control These are Pb−Free Devices Output Voltage (Vout) 8 NC 3 1 V4949C ALYW G 1 8 SOIC−8 EP PD SUFFIX CASE 751AC 8 1 V4949C ALYWG G 1 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Device (Note: Microdot may be in either location) PIN CONNECTIONS CT 4 Supply Voltage (VCC) 1 2.0 mA Reset VCC 1 8 Vout Si 2 7 So NC 3 6 Reset CT 4 5 GND 6 Regulator Sense Output (So) Reset Sense Input (Si) 7 2 Vref (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. 1.25 V 2.0 V Sense 5 GND Figure 1. Representative Block Diagram © Semiconductor Components Industries, LLC, 2017 October, 2019 − Rev. 2 1 Publication Order Number: NCV4949C/D NCV4949C PIN FUNCTION DESCRIPTION SO−8 Pin# SO−8 EP Symbol Description 1 1 VCC 2 2 Si Input of Sense Comparator 4 4 CT Reset Delay Capacitor 5 5 GND Ground 6 6 Reset Output of Reset Comparator 7 7 SO Output of Sense Comparator 8 8 Vout Main Regulator Output 3 3 NC No Connect − EPAD EPAD Supply Voltage Connect to Ground potential or leave unconnected MAXIMUM RATINGS Rating Symbol Min Max Unit DC Operating Supply Voltage VCC 5.5 40 V Input to Regulator VCC −40 45 V VCC TR − 60 V Output Vout Iout −0.5 −10 20 Internally Limited V mA Sense Input VSI ISI −40 −1.0 45 1.0 V mA Sense Output VSO ISO −0.3 −5.0 7.0 5.0 V mA Reset Output VReset IReset −0.3 −5.0 7.0 5.0 V mA Reset Delay VCT ICT −0.3 Internally Limited 7.0 Internally Limited V mA − − − 4000 400 V TJ −40 +150 °C TSTG −50 +150 °C Transient Supply Voltage (Note 1) ESD Protection at any pin Human Body Model Machine Model Operating Junction Temperature Range Storage Temperature Range Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Load Dump Test B (with centralized load dump suppression) according to ISO16750-2 standard. Guaranteed by design. Not tested in production. Passed Class C according to ISO16750-1. THERMAL CHARACTERISTICS Characteristic Test Conditions (Typical Values) Note 2 Note 3 Note 4 Unit SOIC−8 Junction−to−Lead (YJLx6 qJL6) Junction−to−Ambient (RqJA, qJA) 65.6 169.4 62 147.6 61 127.2 °C/W SOIC−8 EP Junction−to−Lead (YJL6, qJL6) Junction−to−Ambient (RqJA, qJA) 36.1 109.2 32.1 91.1 27.4 71.9 °C/W Symbol Min Max Unit Reflow (SMD styles only) lead free 60 − 150 sec above 217, 40 sec max at peak Tsld − 260 °C Moisture Sensitivity Level (SOIC−8) MSL Level 1 Moisture Sensitivity Level (SOIC−8EP) MSL Level 2 2. 1 oz. Copper, 100 mm sq. Copper area, 1.5 mm thick FR−4. 3. 1 oz. Copper, 200 mm sq. Copper area, 1.5 mm thick FR−4. 4. 1 oz. Copper, 500 mm sq. Copper area, 1.5 mm thick FR−4. LEAD TEMPERATURE SOLDERING REFLOW (Note 5) Rating 5. Per IPC / JEDEC J−STD−020C. www.onsemi.com 2 NCV4949C ELECTRICAL CHARACTERISTICS (VCC = 14 V, −40°C < TJ < 150°C, unless otherwise specified.) Symbol Min Typ Max Unit Output Voltage (TJ = 25°C, Iout = 1.0 mA) Vout 4.95 5.0 5.05 V Output Voltage (6.0 V < VCC < 28 V, 1.0 mA < Iout < 50 mA) Vout 4.9 5.0 5.1 V Output Voltage (VCC = 35 V, t < 1.0 s, 1.0 mA < Iout < 50 mA) Vout 4.9 5.0 5.1 V Dropout Voltage Vdrop Iout = 10 mA − 0.08 0.25 Iout = 50 mA − 0.18 0.40 Iout = 100 mA − 0.22 0.50 VIO − 0.12 0.4 V Line Regulation (6.0 V < VCC < 28 V, Iout = 1.0 mA) Regline − 1.0 20 mV Load Regulation (1.0 mA < Iout < 100 mA) Regload − 1.0 30 mV Characteristic Input to Output Voltage Difference in Undervoltage Condition V (VCC = 4.0 V, Iout = 35 mA) Current Limit ILim Vout = 4.5 V 105 320 400 − 220 − IQSE − 120 260 mA IQ − − 5.0 mA VResth − 4.5 − V Vout = 0 V Quiescent Current (Iout = 0.3 mA, TJ < 100°C) Quiescent Current (Iout = 100 mA) mA RESET Reset Threshold Voltage Reset Threshold Hysteresis VResth,hys mV @ TJ = 25°C 50 100 200 @ TJ = −40 to +125°C 50 − 300 Reset Pulse Delay (CT = 100 nF, tR ≥ 100 ms) tResD 55 100 180 ms Reset Reaction Time (CT = 100 nF) tResR − 5.0 30 ms Reset Output Low Voltage (RReset = 10 kW to Vout, VCC ≥ 3.0 V) VResL − − 0.3 V Reset Output High Leakage Current (VReset = 5.0 V) IResH − − 1.0 mA Delay Comparator Threshold VCTth − 2.0 − V VCTth, hys − 100 − mV VSOth 1.16 1.25 1.35 V VSOth,hys 20 100 200 mV Sense Output Low Voltage (VSI ≤ 1.16 V, VCC ≥ 3.0 V, RSO = 10 kW to Vout) VSOL − − 0.4 V Sense Output Leakage (VSO = 5.0 V, VSI ≥ 1.5 V) ISOH − − 1.0 mA ISI −1.0 0.1 1.0 mA TSD 150 − 200 °C Delay Comparator Threshold Hysteresis SENSE Sense Low Threshold (VSI Decreasing = 1.5 V to 1.0 V) Sense Threshold Hysteresis Sense Input Current THERMAL SHUTDOWN Thermal Shutdown Temperature (Iout = 1 mA) (Note 6) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Values based on design and/or characterization. www.onsemi.com 3 NCV4949C TYPICAL CHARACTERISTICS 100 1 VOUT, OUTPUT VOLTAGE (V) 10 ESR (W) 5.04 Unstable Region VIN = 14 V COUT = 2.2 − 100 mF Stable Region 0.1 0.01 0 25 50 75 5.00 4.99 4.98 4.97 0 40 80 120 TJ, JUNCTION TEMPERATURE (°C) Figure 2. ESR Stability Border vs. Output Current Figure 3. Output Voltage vs. Junction Temperature 160 400 VDROP, DROPOUT VOLTAGE (mV) VOUT, OUTPUT VOLTAGE (V) 5.01 IOUT, OUTPUT CURRENT (mA) TJ = 25°C 5 4 RL = 5 kW 3 2 RL = 100 W 1 1 2 4 3 5 6 7 8 9 300 TJ = 125°C 250 TJ = 25°C 200 150 100 50 0 20 40 60 80 100 VCC, SUPPLY VOLTAGE (V) IOUT, OUTPUT CURRENT (mA) Figure 4. Output Voltage vs. Supply Voltage Figure 5. Dropout Voltage vs. Output Current 2.5 250 IQ, QUIESCENT CURRENT (mA) IOUT = 100 mA 300 IOUT = 50 mA 200 150 IOUT = 10 mA 100 50 0 −40 350 0 10 350 VDROP, DROPOUT VOLTAGE (mV) 5.02 4.96 −40 100 6 0 VCC = 14 V IOUT = 1.0 mA 5.03 0 40 80 2.0 1.5 1.0 0.5 0 120 VCC = 14 V TJ = 25°C 0.1 1 10 TJ, JUNCTION TEMPERATURE (°C) IOUT, OUTPUT CURRENT (mA) Figure 6. Dropout Voltage vs. Junction Temperature Figure 7. Quiescent Current vs. Output Current www.onsemi.com 4 100 NCV4949C TYPICAL CHARACTERISTICS VCTth, RESET DELAY THRESHOLD (V) TJ = 25°C 7 6 5 4 3 2 RL = 100 W 1 0 RL = 5 kW 0 5 10 15 20 25 30 35 40 1 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 1.88 1.86 1.84 1.82 VCC = 14 V 1.80 −40 0 40 80 120 160 4.80 VCC = 14 V 4.75 4.70 Upper Threshold 4.65 4.60 Lower Threshold 4.55 4.50 4.45 4.40 −40 0 40 80 120 VOUT, OUTPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C) Figure 10. Reset Output vs. Regulator Output Voltage Figure 11. Reset Thresholds vs. Junction Temperature 160 1.40 6 VSI, SENSE INPUT VOLTAGE (V) VRESET, RESET OUTPUT (V) VSO, SENSE OUTPUT VOLTAGE (V) Resistor 10 kW from Reset Output to 5.0 V 2 VCC = 14 V TJ = 25°C 5 4 Resistor 10 kW from Reset Output to 5.0 V 3 2 1 0 1.90 Figure 9. Reset Delay Threshold vs. Junction Temperature 4 0 1.92 Figure 8. Quiescent Current vs. Supply Voltage VCC = 14 V TJ = 25°C 3 1.94 TJ, JUNCTION TEMPERATURE (°C) 6 5 1.96 VCC, SUPPLY VOLTAGE (V) VRESET, RESET THRESHOLD VOLTAGE (V) IQ, QUIESCENT CURRENT (mA) 8 1.0 1.1 1.2 1.3 1.4 Upper Threshold 1.35 1.30 Lower Threshold 1.25 1.20 VCC = 14 V 1.15 −40 1.5 0 40 80 120 VSI, SENSE INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C) Figure 12. Sense Output vs. Sense Input Voltage Figure 13. Sense Thresholds vs. Junction Temperature www.onsemi.com 5 160 NCV4949C APPLICATION INFORMATION CO Vout CCT NC 8 Vbat 3 CT 4 VCC 1 Cs 2.0 mA Reset 6 RReset 10 kW RSI1 Vout Regulator Reset RSO 10 kW So Si 7 2 RSI2 CSI 1.25 V 2.0 V Vref Sense 5 GND NOTE: 1. For good dynamic performance: Cs ≥ 1.0 mF, CO ≥ 4.7 mF, ESR < 4.5 W at 10 kHz Figure 14. Application Schematic VBAT VCC Vout Cs VDD Co VCC CT RESET CCT RReset NCV4949C RSI1 I/O Voltage Supervisor RSO Microprocessor (e.g. NCV30X, NCV809) GND SI RSI2 CSI Reset I/O SO I/O GND NOTE: The NCV4949C is not developed in compliance with ISO26262 standard. If application is safety critical then the above application diagram shown in Figure 15 can be used. Figure 15. Application Diagram www.onsemi.com 6 NCV4949C OPERATING DESCRIPTION The NCV4949C is a monolithic integrated low dropout voltage regulator. Several outstanding features and auxiliary functions are implemented to meet the requirements of supplying microprocessor systems in automotive applications. It is also suitable in other applications where the included functions are required. The modular approach of this device allows the use of other features and functions independently when required. Vout Vout 5.0 V Voltage Regulator The voltage regulator uses a lateral PNP transistor as a regulating element. With this structure, very low dropout voltage at currents up to 100 mA is obtained. The dropout operation of the standby regulator is maintained typically down to 2.5 V input supply voltage. A typical curve showing the standby output voltage as a function of the input supply voltage is shown in Figure 17. The current consumption of the device (quiescent current) is less than 200 mA. To reduce the quiescent current peak in the undervoltage region and to improve the transient response in this region, the dropout voltage is controlled. The quiescent current as a function of the supply input voltage is shown in Figure 18. 0V 35 V Figure 17. Output Voltage vs. Supply Voltage IQ, QUIESCENT CURRENT (mA) 8 The maximum output current is internally limited. In case of short circuit, the output current is foldback current limited as described in Figure 16. 6 VOUT, OUTPUT VOLTAGE (V) 5.0 V VCC Short Circuit Protection: 7 TJ = 25°C 6 5 4 3 2 RL = 100 W 1 0 RL = 5 kW 0 5 5 10 15 20 25 30 35 VCC, SUPPLY VOLTAGE (V) Figure 18. Quiescent Current vs. Supply Voltage 4 3 2 VCC = 14 V TJ = 25°C 1 0 2.0 V 0 50 100 150 200 250 300 350 400 IOUT, OUTPUT CURRENT (mA) Figure 16. Foldback Characteristic of Vout www.onsemi.com 7 40 NCV4949C Reset Circuit Output voltage drops below the reset threshold only marginally longer than the reaction time results in a shorter reset delay time. The nominal reset delay time will be generated for output voltage drops longer than approximately 50 ms. The typical reset output waveforms are shown in Figure 20. The block circuit diagram of the reset circuit is shown in Figure 19. The reset circuit supervises the output voltage. The reset threshold of 4.5 V is defined by the internal reference voltage and standby output divider. The reset pulse delay time tRD, is defined by the charge time of an external capacitor CT: t RD + Vout C x 2.0 V T 2.0 mA Vout1 5.0 V VRT + 0.1 V VRT The reaction time of the reset circuit originates from the discharge time limitation of the reset capacitor CT and is proportional to the value of CT. The reaction time of the reset circuit increases the noise immunity. 3.0 V t tR Reset tRD 1.25 V Vref 22 k 40 V Vin tRD tRR 2.0 mA Switch On Reset Input Drop Dump Output Overload Switch Off Figure 20. Typical Reset Output Waveforms CT Out + - Sense Comparator The sense comparator compares an input signal with an internal voltage reference of typical 1.25 V. The use of an external voltage divider makes this comparator very flexible in the application. It can be used to supervise the input voltage either before or after a protection diode and to provide additional information to the microprocessor such as low voltage warnings. 2.0 V Reg Figure 19. Reset Circuit ORDERING INFORMATION Device NCV4949CDR2G NCV4949CPDR2G Package Shipping† SOIC−8 (Pb−Free) 2500 / Tape & Reel SOIC−8 EP (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 EP CASE 751AC ISSUE D 8 1 SCALE 1:1 DATE 02 APR 2019 GENERIC MARKING DIAGRAM* 8 XXXXX AYWWG G 1 DOCUMENT NUMBER: DESCRIPTION: XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package 98AON14029D SOIC−8 EP *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present and may be in either location. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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