DATA SHEET
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Isolated High Current
IGBT/MOSFET Gate Driver
8
1
SOIC−8 NB
CASE 751−07
NCx57080y, NCx57081y
(x = D or V, y = A, B or C)
NCx57080y, NCx57081y are high−current single channel
IGBT/MOSFET gate drivers with 3.75 kVrms internal galvanic
isolation, designed for high system efficiency and reliability in high
power applications. The devices accept complementary inputs and
depending on the pin configuration, offer options such as Active
Miller Clamp (version A), negative power supply (version B) and
separate high and low (OUTH and OUTL) driver outputs (version C)
for system design convenience. The driver accommodate wide range
of input bias voltage and signal levels from 3.3 V to 20 V and they
are available in narrow−body SOIC−8 package.
Features
• High Peak Output Current (+6.5 A/−6.5 A)
• Low Clamp Voltage Drop Eliminates the Need of Negative Power
•
•
•
•
•
•
•
•
•
•
•
•
Supply to Prevent Spurious Gate Turn−on (Version A)
Short Propagation Delays with Accurate Matching
IGBT/MOSFET Gate Clamping during Short Circuit
IGBT/MOSFET Gate Active Pull Down
Tight UVLO Thresholds for Bias Flexibility
Wide Bias Voltage Range including Negative VEE2 (Version B)
3.3 V, 5 V, and 15 V Logic Input
3.75 kVRMS VISO (I−O) (to meet UL1577 Requirements)
Safety and Regulatory Approvals:
♦ UL1577 Certified, 3750 VACRMS for 1 Minute
♦ DIN VDE V 0884−11 Certification Pending, 870 VPK Working
Insulation Voltage
High Transient Immunity
High Electromagnetic Immunity
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING DIAGRAM
8
5708zy
ALYW
G
1
5708zy
A
L
Y
W
G
= Specific Device Code
z = 0/1
y = A/B/C
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
See detailed pin connection information on page 2 of this
data sheet.
ORDERING INFORMATION
See detailed ordering and shipping information on page 21 of
this data sheet.
Typical Applications
•
•
•
•
•
•
Motor Control
Uninterruptible Power Supplies (UPS)
Automotive Applications
Industrial Power Supplies
Solar Inverters
HVAC
© Semiconductor Components Industries, LLC, 2021
August, 2021 − Rev. 3
1
Publication Order Number:
NCD57080/D
NCx57080y, NCx57081y
PIN CONNECTIONS
VDD1
IN+
IN−
GND1
GND2
CLAMP
OUT
VDD2
NCx57080A, NCx57081A
NOTE:
VEE2
GND2
OUT
VDD2
VDD1
IN+
IN−
GND1
VDD1
IN+
IN−
GND1
GND2
OUTL
OUTH
VDD2
NCx57080C, NCx57081C
NCx57080B, NCx57081B
x = D or V
Figure 1. Pin Connections
BLOCK DIAGRAM AND APPLICATION SCHEMATIC − NCx5708zA
VDD1
VDD2
UVLO1
UVLO2
VDD2
VDD1
IN−
OUT
IN+
Logic
Logic
2
GND1
1
+
VCLAMP−THR
−
CLAMP
2
Figure 2. Simplified Block Diagram, NCx5708zA
VDD2
VDD1
VDD1
VDD2
IN+
OUT
IN−
CLAMP
GND1
GND2
Figure 3. Simplified Application Schematics, NCx5708zA
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2
GND2
NCx57080y, NCx57081y
BLOCK DIAGRAM AND APPLICATION SCHEMATIC − NCx5708zB
VDD1
VDD2
UVLO1
UVLO2
VDD2
VDD1
IN−
OUT
IN+
Logic
VEE2
Logic
GND1
1
GND2
2
Figure 4. Simplified Block Diagram, NCx5708zB
VDD2
VDD1
VDD1
VDD2
IN+
OUT
IN−
GND2
GND1
VEE2
VEE2
Figure 5. Simplified Application Schematics, NCx5708zB
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NCx57080y, NCx57081y
BLOCK DIAGRAM AND APPLICATION SCHEMATIC − NCx5708zC
VDD1
VDD2
UVLO1
UVLO2
VDD2
VDD1
IN−
OUTH
OUTL
IN+
GND1
Logic
Logic
GND2
2
1
Figure 6. Simplified Block Diagram, NCx5708zC
VDD1
VDD2
VDD2
VDD1
IN+
OUTH
IN−
OUTL
GND1
GND2
Figure 7. Simplified Application Schematics, NCx5708zC
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NCx57080y, NCx57081y
Table 1. FUNCTION DESCRIPTION
Pin Name
No.
I/O
Description
VDD1
1
Power
Input side power supply. A good quality bypassing capacitor is required from this pin to GND1
and should be placed close to the pins for best results.
The under voltage lockout (UVLO) circuit enables the device to operate at power on when
a typical supply voltage higher than VUVLO1−OUT−ON is present.
Please see Figures 9A and 9B for more details.
IN+
2
I
Non inverted gate driver input. It is internally clamped to GND1 and has an equivalent
pull−down resistor of 125 kW to ensure that output is low in the absence of an input signal.
A minimum positive or negative pulse−width is required at IN+ before OUT or OUTH/OUTL
responds.
IN−
3
I
Inverted gate driver input. It is internally clamped to VDD1 and has an equivalent pull−up
resistor of 125 kW to ensure that output is low in the absence of an input signal. A minimum
positive or negative pulse−width is required at IN− before OUT or OUTH/OUTL responds.
GND1
4
Power
Input side ground reference.
VDD2
5
Power
Output side positive power supply. The operating range for this pin is from UVLO2 to its
maximum allowed value. A good quality bypassing capacitor is required from this pin to GND2
and should be placed close to the pins for best results.
The under voltage lockout (UVLO) circuit enables the device to operate at power on when
a typical supply voltage higher than VUVLO2−OUT−ON is present. Please see Figure 9C and 9D
for more details.
GND2
(NCx5708zA,
NCx5708zC)
8
Power
Output side gate drive reference connecting to IGBT emitter or MOSFET source.
GND2
(NCx5708zB)
7
OUT
(NCx5708zA,
NCx5708zB)
6
O
Driver output that provides the appropriate drive voltage and source/sink current to the IGBT/
MOSFET gate. OUT is actively pulled low during start−up.
OUTH
(NCx5708zC)
6
O
Driver high output that provides the appropriate drive voltage and source current to the IGBT/
MOSFET gate.
OUTL
(NCx5708zC)
7
O
Driver low output that provides the appropriate drive voltage and sink current to the IGBT/
MOSFET gate. OUTL is actively pulled low during start−up.
CLAMP
(NCx5708zA)
7
O
Provides clamping for the IGBT/MOSFET gate during the off period to protect it from parasitic
turn−on. Its internal N FET is turned on when the voltage of this pin falls below VCLAMP−THR.
It is to be tied directly to IGBT/MOSFET gate with minimum trace length for best results.
VEE2
(NCx5708zB)
8
Power
NOTE:
Output side negative power supply. A good quality bypassing capacitor is required from this pin
to GND2 and should be placed close to the pins for best results.
(x = D or V, z = 0 or 1)
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NCx57080y, NCx57081y
Table 2. SAFETY AND INSULATION RATINGS
Symbol
Parameter
Value
Installation Classifications per DIN VDE 0110/1.89
Table 1 Rated Mains
Voltage
CTI
< 150 VRMS
I − IV
< 300 VRMS
I − IV
< 450 VRMS
I − IV
< 600 VRMS
I − IV
< 1000 VRMS
I − III
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
600
Climatic Classification
40/125/21
Pollution Degree (DIN VDE 0110/1.89)
VPR
Unit
2
Input−to−Output Test Voltage, Method b, VIORM × 1.875 = VPR,
100% Production Test with tm = 1 s, Partial Discharge < 5 pC
2250
Vpk
VIORM
Maximum Repetitive Peak Voltage
1200
Vpk
VIOWM
Maximum Working Voltage
870
VRMS
VIOTM
Highest Allowable Over Voltage
6300
Vpk
ECR
External Creepage
4.0
mm
ECL
External Clearance
4.0
mm
DTI
Insulation Thickness
17.3
mm
Safety Limit Values – Maximum Values in Failure; Case Temperature
150
°C
Safety Limit Values – Maximum Values in Failure; Input Power
121
mW
Safety Limit Values – Maximum Values in Failure; Output Power
1194
mW
Insulation Resistance at TS, VIO = 500 V
109
W
TCase
PS,INPUT
PS,OUTPUT
RIO
Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1)
Over operating free−air temperature range unless otherwise noted.
Parameter
Symbol
Minimum
Maximum
Unit
22
V
VDD1−GND1
Supply Voltage, Input Side
−0.3
VDD2−GND2
Positive Power Supply, Output Side
−0.3
32
V
VEE2−GND2
Negative Power Supply, Output Side
−18
0.3
V
VDD2−VEE2
(VMAX2)
Differential Power Supply, Output Side (NCx5708zB)
0
36
V
VOUT−GND2
VOUTH−GND2
Gate−driver Output High Voltage
NCx5708zA/B
NCx5708zC
−
−
VDD2 + 0.3
−
VOUT−GND2
VOUTL−GND2
Gate−driver Output Low Voltage
NCx5708zA/B
NCx5708zC
−0.3
−
−
−
V
V
IPK−SRC
Gate−driver Output Sourcing Current
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%,
VDD2 = 15 V, VEE2 = 0 V)
−
6.5
A
IPK−SNK
Gate−driver Output Sinking Current
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%,
VDD2 = 15 V, VEE2 = 0 V)
−
6.5
A
IPK−CLAMP
Clamp Sinking Current
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%,
VCLAMP = 2.5 V)
−
2.5
A
tCLP
VLIM−GND1
VCLAMP−GND2
PD
Maximum Short Circuit Clamping Time (IOUT_CLAMP = 500 mA)
−
10
ms
Voltage at IN+, IN−
−0.3
VDD1 + 0.3
V
Clamp Voltage
−0.3
VDD2 + 0.3
V
−
1315
mW
Power Dissipation (SOIC−8 Narrow Package)
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NCx57080y, NCx57081y
Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1) (continued)
Over operating free−air temperature range unless otherwise noted.
Symbol
TJ(max)
TSTG
Parameter
Minimum
Maximum
Unit
Maximum Junction Temperature
−40
150
°C
Storage Temperature Range
−65
150
°C
ESDHBM
ESD Capability, Human Body Model (Note 2)
−
±2
kV
ESDCDM
ESD Capability, Charged Device Model (Note 2)
−
±2
kV
MSL
Moisture Sensitivity Level
−
1
−
TSLD
Lead Temperature Soldering Reflow, Pb−Free (Note 3)
−
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114).
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101).
Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard:
JESD78, 25°C (absolute maximum ratings for all tests)
JESD78, 125°C (limitation for IN+ test, VDD1 = IN+ = 12 V maximum)
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 4. THERMAL CHARACTERISTICS
Symbol
RqJA
Parameter
Thermal Characteristics, SOIC−8 narrow body (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
Value
Unit
95 (4−Layer)
175 (1−Layer)
°C/W
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 100 mm2 (or 0.16 in2) of 1 oz copper thickness and FR4 PCB substrate.
Table 5. OPERATING RANGES (Note 6)
Symbol
Parameter
Min
Max
Unit
VDD1−GND1
Supply Voltage, Input Side
UVLO1
20
V
VDD2−GND2
Positive Power Supply, Output Side
UVLO2
30
V
VEE2−GND2
Negative Power Supply, Output Side (NCx5708zB)
−15
0
V
Differential Power Supply, Output Side (NCx5708zB)
0
32
V
VIL
Low Level Input Voltage at IN+, IN− (Note 7)
0
0.3 × VDD1
V
VIH
High Level Input Voltage at IN+, IN− (Note 7)
0.7 × VDD1
VDD1
V
|dVISO/dt|
Common Mode Transient Immunity (Note 8)
100
−
kV/ms
Ambient Temperature
−40
125
°C
VDD2−VEE2 (VMAX2)
TA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
7. Table values are valid for 3.3 V and 5 V VDD1, for higher VDD1 voltages, the threshold values are maintained at the 5 V VDD1 levels.
8. Was tested by ±1500 V pulses up to 100 kV/ms.
Table 6. ISOLATION CHARACTERISTICS
Symbol
VISO, input−output
RISO
Parameter
Conditions
Value
Unit
Input−Output Isolation
Voltage
TA = 25°C, Relative Humidity < 50%,
t = 1.0 minute, II−O < 30 mA, 50 Hz
(Note 9, 10, 11)
3750
VRMS
Isolation Resistance
VI−O = 500 V (Note 9)
1011
W
9. Device is considered a two−terminal device: pins 1 to 4 are shorted together and pins 5 to 9 are shorted together.
10. 3750 VRMS for 1−minute duration is equivalent to 4500 VRMS for 1−second duration.
11. The input−output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input−output continuous voltage
rating. For the continuous working voltage rating, refer to equipment−level safety specification or DIN VDE V 0884−11 Safety and Insulation
Ratings Table.
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NCx57080y, NCx57081y
ELECTRICAL CHARACTERISTICS VDD1 = 5 V, VDD2 = 15 V, (VEE2 = 0 V for NCx5708zB).
For typical values TA = 25°C, for min/max values, TA is the operating ambient temperature range that applies, unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VOLTAGE SUPPLY
VUVLO1−OUT−ON
UVLO1 Output Enabled
−
−
3.1
V
VUVLO1−OUT−OFF
UVLO1 Output Disabled
2.4
−
−
V
UVLO1 Hysteresis
0.1
−
−
V
NCx57080y
12.4
12.9
13.4
V
NCx57081y
8.6
9
9.5
V
NCx57080y
11.5
12
12.5
V
NCx57081y
7.6
8
8.5
V
0.7
1
−
V
VUVLO1−HYST
VUVLO2−OUT−ON
VUVLO2−OUT−OFF
VUVLO2−HYST
IDD1−0−3.3
UVLO2 Output Enabled
UVLO2 Output Disabled
UVLO2 Hysteresis
Input Supply Quiescent Current
IN+ = Low, IN− = Low, VDD1 = 3.3 V
−
−
2
mA
IDD1−0−5
IN+ = Low, IN− = Low
−
−
2
mA
IDD1−0−15
IN+ = Low, IN− = Low, VDD1 = 15 V
−
−
2
mA
IDD1−100−5
IDD2−0
IDD2−100
IEE2−0
IN+ = High, IN− = Low
−
−
5.5
mA
Output Positive Supply
Quiescent Current
IN+ = Low, IN− = Low, no load
−
−
2
mA
IN+ = High, IN− = Low, no load
−
−
2
mA
Output Negative Supply
Quiescent Current (NCx5708zB)
IN+ = Low, IN− = Low, no load,
VEE2 = −8 V
−
−
2
mA
IN+ = High, IN− = Low, no load, VEE2
= −8 V
−
−
2
mA
IEE2−100
LOGIC INPUT AND OUTPUT
VIL
IN+, IN−, Low Input Voltage
Level scale for VDDI = 3.3 to 5 V
for VDDI > 5 V is the same as for
VDDI = 5 V
−
−
0.3 ×
VDD1
V
VIH
IN+, IN−, High Input Voltage
Level scale for VDDI = 3.3 to 5 V
for VDDI > 5 V is the same as for
VDDI = 5 V
0.7 ×
VDD1
−
−
V
VIN−HYST
Input Hysteresis Voltage
Level scale for VDDI = 3.3 to 5 V
for VDDI > 5 V is the same as for
VDDI = 5 V
−
0.15 ×
VDD1
−
V
IIN−L−3.3
IN− Input Current
VIN− = 0 V, VDD1 = 3.3 V
−
−
100
mA
IIN−L−5
VIN− = 0 V
−
−
100
mA
IIN−L−15
VIN− = 0 V, VDD1 = 15 V
−
−
100
mA
IIN−L−20
VIN− = 0 V, VDD1 = 20 V
−
−
100
mA
VIN+ = VDD1 = 3.3 V
−
−
100
mA
IIN+H−5
VIN+ = VDD1 = 5 V
−
−
100
mA
IIN+H−15
VIN+ = VDD1 = 15 V
−
−
100
mA
VIN+ = VDD1 = 20 V
IIN+H−3.3
IN+ Input Current
−
−
100
mA
tON−MIN1
IIN+H−20
Input Pulse Width of IN+, IN− for
Guaranteed No Response at
Output
−
−
10
ns
tON−MIN2
Input Pulse Width of IN+, IN− for
Guaranteed Response at Output
40
−
−
ns
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NCx57080y, NCx57081y
ELECTRICAL CHARACTERISTICS VDD1 = 5 V, VDD2 = 15 V, (VEE2 = 0 V for NCx5708zB).
For typical values TA = 25°C, for min/max values, TA is the operating ambient temperature range that applies, unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
DRIVER OUTPUT
VOUTL1
VOUTL2
VOUTH1
VOUTH2
Output Low State
(VOUT – GND2 for NCx5708zA)
(VOUT – VEE2 for NCx5708zB)
(VOUTL – GND2 for NCx5708zC)
ISINK = 200 mA
−
0.15
0.3
ISINK = 1.0 A, TA = 25°C (Note 12)
−
−
0.8
Output High State
(VDD2 – VOUT for NCx5708zA/B)
(VDD2 – VOUT for NCx5708zB)
(VDD2 – VOUTL for NCx5708zC)
ISRC = 200 mA
−
0.2
0.35
ISRC = 1.0 A, TA = 25°C (Note 12)
−
−
1.0
V
IPK−SNK1
Peak Driver Current, Sink
(Note 12)
−
6.5
−
A
IPK−SRC1
Peak Driver Current, Source
(Note 12)
−
6.5
−
A
V
MILLER CLAMP (NCx5708zA)
VCLAMP
VCLAMP−THR
Clamp Voltage
ICLAMP = 2.5 A, TA = 25°C
−
2
−
ICLAMP = 2.5 A,
TA = −40°C to 125°C
−
−
3.5
1.5
2
2.5
V
Clamp Activation Threshold
IGBT SHORT CIRCUIT CLAMPING
VCLAMP−OUTH
Clamping Voltage, Sourcing
(VOUT / VOUTH – VDD2)
IN+ = Low, IN− = High,
ICLAMP−OUT/OUTH = 500 mA,
(pulse test, tCLPmax = 10 ms)
−
0.7
1.3
V
VCLAMP−OUTL
Clamping Voltage, Sinking
(VOUTL − VDD2)
IN+ = High, IN− = Low,
ICLAMP−OUTL = 500 mA,
(pulse test, tCLPmax = 10 ms)
−
0.8
1.5
V
VCLAMP−CLAMP
Clamping Voltage, Clamp
(VCLAMP − VDD2)
(NCx5708zA)
IN+ = High, IN− = Low,
ICLAMP−CLAMP = 500 mA
(pulse test, tCLPmax = 10 ms)
−
1.1
1.7
V
CLOAD = 10 nF
VIH to 10% of output change
Pulse Width > 150 ns.
−
−
−
−
DYNAMIC CHARACTERISTIC
IN+, IN− to Output High
Propagation Delay
tPD−ON−3.3
VDD1 = VIN+ = 3.3V, VIN− = 0 V
40
60
90
ns
tPD−ON−5
VDD1 = VIN+ = 5 V, VIN− = 0 V
40
60
90
ns
tPD−ON−15
VDD1 = VIN+ = 15 V, VIN− = 0 V
40
60
90
ns
VDD1 = VIN+ = 20 V, VIN− = 0 V
40
60
90
ns
−
−
−
−
VDD1 = VIN+ = 3.3 V, VIN− = 0 V
40
60
90
ns
tPD−OFF−5
VDD1 = VIN+ = 5 V, VIN− = 0 V
40
60
90
ns
tPD−OFF−15
VDD1 = VIN+ = 15 V, VIN− = 0 V
40
60
90
ns
tPD−OFF−20
VDD1 = VIN+ = 20 V, VIN− = 0 V
40
60
90
ns
tPD−ON−20
IN+, IN− to Output Low
Propagation Delay
tPD−OFF−3.3
tDISTORT
CLOAD = 10 nF
VIH to 10% of output change
Pulse Width > 150 ns.
Propagation Delay Distortion
(= tPD−ON − tPD−OFF)
TA = 25°C, PW > 150 ns
−
0
−
ns
TA = −40°C to 125°C, PW > 150 ns
−25
−
25
ns
Prop Delay Distortion between
Parts
PW > 150 ns
−30
0
30
ns
tRISE
Rise Time (see Figure 8)
CLOAD = 1 nF,
10% to 90% of Output Change
−
13
−
ns
tFALL
Fall Time (see Figure 8)
CLOAD = 1 nF,
90% to 10% of Output Change
−
13
−
ns
tDISTORT_TOT
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NCx57080y, NCx57081y
ELECTRICAL CHARACTERISTICS VDD1 = 5 V, VDD2 = 15 V, (VEE2 = 0 V for NCx5708zB).
For typical values TA = 25°C, for min/max values, TA is the operating ambient temperature range that applies, unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
−
1500
−
ns
DYNAMIC CHARACTERISTIC
tUVF1
UVLO1 Fall Delay (Note 12)
tUVR1
UVLO1 Rise Delay (Note 12)
−
770
−
ns
tUVF2
UVLO2 Fall Delay (Note 12)
−
1000
−
ns
tUVR2
UVLO2 Rise Delay (Note 12)
−
1000
−
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
12. Values based on design and/or characterization.
VIH
VIL
IN+
tFALL
tRISE
tON−MIN2
tON−MIN1
90%
tPD−ON
tON−MIN1
tPD−OFF
OUT/OUTH
10%
Figure 8. Propagation Delay, Rise and Fall time
VDD2
VUVLO1−HYST
VUVLO1−OUT−ON
VUVLO1−OUT−OFF
VDD1
tUVR1
tUVF1
tUVR1
tUVF1
tUVR2
IN+
OUT/OUTH
Figure 9.
Output Ramp−up and Ramp−down Times during UVLO1
Figure 9A. UVLO1 and Associated Timing Waveforms
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tUVR1−spread
NCx57080y, NCx57081y
VDD2
VUVLO1−OUT−ON
VUVLO1−OUT−OFF
VDD1
tUVR1
tUVF1
tUVF1
tUVR1
tUVR1
tUVR1−spread
IN+
OUT/OUTH
VDD1 Glitch Filtering
Figure 9B. UVLO1 Waveforms Depicting VDD1 Glitch Filtering
VDD1
VUVLO2−HYST
VUVLO2−OUT−ON
VUVLO2−OUT−OFF
VDD2
tUVR2
tUVF2
tUVR2
tUVF2
tUVR2
IN+
OUT/OUTH
Output Ramp−up and Ramp−down Times during UVLO2
Figure 9C. UVLO2 and Associated Timing Waveforms
www.onsemi.com
11
tUVR2−spread
NCx57080y, NCx57081y
VDD1
VUVLO2−OUT−ON
VUVLO2−OUT−OFF
VDD2
tUVR2
tUVF2
tUVR2
tUVR2
tUVR2
IN+
OUT/OUTH
VDD2 Glitch Filtering
Figure 9D. UVLO2 Waveforms Depicting VDD2 Glitch Filtering
VDD1
Clamping
Circuit
IN+
VDD1 VDD1
IN−
Clamping
Circuit
Figure 10. Input Pin Structure
www.onsemi.com
12
tUVR2−spread
NCx57080y, NCx57081y
TYPICAL CHARACTERISTICS
6
4
(2)
3
2
(1)
3
(2)
2
(1)
1
1
0
(3)
4
Current [mA]
Current [mA]
5
5
(3)
−40 −20
0
20
40
60
80
Temperature [°C]
100
0
−40
120
−20
0
(1) IDD1−0−5
(2) IDD1−50−3.3, IN+ = 3.3 V/200 kHz/50%
(2) IDD1−50−5, IN+ = 5 V/200 kHz/50%
Figure 12. IDD1 Supply Current VDD1 = 5 V
20
5
(3)
(3)
Current [mA]
Current [mA]
4
(2)
2
0
(1)
−40 −20
0
20
40
60
80
Temperature [°C]
100
5
1
10
2
2
Current [mA]
Current [mA]
2.5
1.5
(2)
(1)
−40 −20
1000
Figure 14. IDD2 vs. Switching Frequency
2.5
0
100
Frequency [kHz]
(1) CG = 1 nF
(2) CG = 10 nF
(3) CG = 100 nF
Figure 13. IDD1 Supply Current VDD1 = 20 V
0.5
(1)
10
0
120
(2)
15
(1) IDD1−0−20
(2) IDD1−50−20, IN+ = 20 V/200 kHz/50%
(3) IDD1−100−20
1
120
(3) IDD1−100−5
Figure 11. IDD1 Supply Current VDD1 = 3.3 V
1
100
(1) IDD1−0−3.3
(3) IDD1−100−3.3
3
20
40
60
80
Temperature [°C]
(2)
1.5
1
(1)
0.5
0
20
40
60
80
100
0
120
−40 −20
Temperature [°C]
0
20
40
60
80
100
120
Temperature [°C]
(1) IDD2−0−15
(1) IDD2−0−30
(2) IDD2−100−15
(2) IDD2−100−30
Figure 15. IDD2 Supply Current VDD2 = 15 V
Figure 16. IDD2 Supply Current VDD2 = 30 V
www.onsemi.com
13
NCx57080y, NCx57081y
TYPICAL CHARACTERISTICS (continued)
1.5
2.9
2.8
Voltage [V]
Voltage [V]
1.4
(1)
2.7
(2)
2.6
−40 −20
1.3
(2)
1.2
1.1
1
(1)
0.9
0
20
40
60
80
100
0.8
−40 −20
120
0
Temperature [°C]
100
120
2.00
1.98
Voltage [V]
2.5
Voltage [V]
80
Figure 18. IGBT Short Circuit CLAMP
Voltage Drop
3
2
1.5
1.96
1.94
1.92
1
−40 −20
0
20
40
60
80
100
1.90
120
−40 −20
0
Temperature [°C]
20
40
60
80
100
120
Temperature [°C]
Figure 19a. Miller Clamp Voltage (2.5 A)
Figure 19b. Miller Clamp Activation
Voltage Threshold
13.5
9.5
(1)
9
Voltage [V]
Voltage [V]
60
(1) VCLAMP−OUTH
(2) VCLAMP−CLAMP
Figure 17. UVLO1 Threshold Voltage
12.5
12
40
Temperature [°C]
(1) VUVLO1−OUT−ON
(2) VUVLO1−OUT−OFF
13
20
(2)
11.5
−40 −20
(1)
8.5
(2)
8
0
20
40
60
80
100
7.5
−40 −20
120
Temperature [°C]
0
20
40
60
80
100
120
Temperature [°C]
(1) VUVLO2−OUT−ON
(2) VUVLO2−OUT−OFF
(1) VUVLO2−OUT−ON
(2) VUVLO2−OUT−OFF
Figure 20. NCx57080 UVLO2 Threshold Voltage
Figure 21. NCx57081 UVLO2 Threshold Voltage
www.onsemi.com
14
NCx57080y, NCx57081y
TYPICAL CHARACTERISTICS (continued)
72
71
Time [ns]
Time [ns]
70
68
66
64
(2)
69
(1)
67
(2)
(1)
62
−40 −20
0
20
40
60
80
100
65
120
−40 −20
0
Temperature [°C]
Time [ns]
Time [ns]
120
13
(1)
(1)
(2)
12
−40 −20
(2)
0
20
40
60
80
Temperature [°C]
100
12
120
−40 −20
0
(1) tRISE, IN+
(2) tRISE, IN−
20
40
60
Temperature [°C]
80
100
120
(1) tFALL, IN+
(2) tFALL, IN−
Figure 24. Rise Time, VDD1 = 5 V
Figure 25. Fall Time, VDD1 = 5 V
−35
50
−35
(3)
Current [mA]
Current [mA]
100
14
14
(4)
(2)
−40 −20
−40
(1)
(2)
−45
−50
(3)(4)
−55
(1)
20
80
Figure 23. Propagation Delay Turn−off
15
30
60
(1) tPD−OFF−5, IN+
(2) tPD−OFF−5, IN−
Figure 22. Propagation Delay Turn−on
40
40
Temperature [°C]
(1) tPD−ON−5, IN+
(2) tPD−ON−5, IN−
13
20
0
20
40
60
80
100
−60
−40 −20
120
0
20
40
60
80
100
120
Temperature [°C]
(1) IIN+H−3.3
(2) IIN+H−5
(3) IIN+H−15
(4) IIN+H−20
(1) IIN−L−3.3
(2) IIN−L−5
(3) IIN−L−15
(4) IIN−L−20
Figure 26. Input Current – Positive Input
Figure 27. Input Current – Negative Input
www.onsemi.com
15
NCx57080y, NCx57081y
Under Voltage Lockout (Refer to Figure 9x)
value of 2 W has to be used in order to avoid interference of
the high di/dt with internal circuitry (e.g. UVLO2).
After the power−on of the driver there has to be a rising
edge applied to the IN+ or falling edge to the IN− in order
for the output to start following the inputs. This serves as a
protection against producing partial pulses at the output if
the VDD1 or VDD2 is applied in the middle of the input PWM
pulse.
If the VDD2 rises over VUVLO2−OUT−ON level the PWM
will appear on the output after tUVR2 + tUVR2−spread. The
tUVR2−spread time is variable and is defined as a time from
end of tUVR2 to first rising edge on IN+ input. If the VDD2
is starting from 0 V the time until PWM is at the output of
the driver is longer than tUVR2 + tUVR2−spread. This is caused
by start up time of internal circuits of the driver.
UVLO ensures correct switching of IGBT/MOSFET
connected to the driver output.
• The IGBT/MOSFET is turned−off and the output is
disabled if the supply VDD1 drops below
VUVLO1−OUT−OFF or VDD2 drops below
VUVLO2−OUT−OFF.
• The driver output does not follow the input signal on
IN+ or IN− until the VDDX rises above the
VUVLOX−OUT−ON and the input signal rising edge is
applied to the IN+ or IN−
• VEE2 is not monitored (NCx5708zB)
With high loading gate capacitances over 10 nF it is
important to follow the decoupling capacitor routing
guidelines as shown on Figure 35. The decoupling capacitor
value should be at least 10 mF. Also gate resistor of minimal
www.onsemi.com
16
NCx57080y, NCx57081y
ACTIVE MILER CLAMP PROTECTION (CLAMP)
For operation with unipolar supply, typically,
VDD2 = 15 V with respect to GND2, and VEE2 = GND2. In
this case, the IGBT/MOSFET can turn on due to additional
charge from IGBT/MOSFET Miller capacitance caused by
a high voltage slew rate transition on the IGBT collector/
MOSFET drain. To prevent IGBT/MOSFET to turn on, the
CLAMP pin is connected directly to IGBT/MOSFET gate
and Miller current is sinked through a low impedance
CLAMP transistor. When the IGBT/MOSFET is turned−off
and the gate voltage transitions below VCLAMP, the CLAMP
output is activated.
NCx5708yB supports bipolar power supply to prevent
unintentional turning on.
For operation with bipolar supplies, the IGBT/MOSFET
is turned off with a negative voltage through OUT with
respect to its emitter. This prevents the IGBT/MOSFET
from unintentionally turning on because of current induced
from its collector to its gate due to Miller effect. Typical
values for bipolar operation are VDD2 = 15 V and VEE2 =
−5 V with respect to GND2.
Driver version A supports unipolar power supply with
active Miller clamp.
OUT/OUTH
OUT/OUTH
Figure 28. Current Path with Miler Clamp Protection
Figure 29. Current Path without Miler Clamp Protection
WARNING: When the application uses an independent or
separate power supply for the control unit and
the input side of the driver, all inputs should
be protected by a serial resistor (In case of
a power failure of the driver, the driver may
be damaged due to overloading of the input
protection circuits)
Non−inverting and Inverting Input Pin (IN+, IN−)
The driver has two possible input modes to control
IGBT/MOSFET. Both inputs have defined minimum input
pulse width to filter occasional glitches.
• Non−inverting input IN+ controls the driver output
while inverting input IN− is set to LOW
• Inverting input IN− controls the driver output while
non−inverting input IN+ is set to HIGH
www.onsemi.com
17
NCx57080y, NCx57081y
• In bipolar power supply the driver is typically supplied
The driver variant A and C are designed to support
unipolar power supply.
The driver variant B is designed to support bipolar power
supply.
Suitable external power capacitors are required for
reliable driving of IGBT/MOSFET gate with high current.
Parallel combination of 100 nF + 4.7 mF low ESR ceramic
capacitors is optimal for a wide range of applications using
IGBT/MOSFET. For reliable driving of IGBT modules
(containing several parallel IGBT’s) with a gate capacitance
over 10 nF a higher decoupling capacity is required
(typically 100 nF + 10 mF). Capacitors should be as close as
possible to the driver’s power pins. The recommended
layout is provided in the Figure 35.
VDD1
+
−
10 mF
100nF
•
VDD1
VEE2
IN+
GND2
IN−
OUT
GND1
VDD2
with a positive voltage of 15 V at VDD2 and negative
voltage −5 V at VEE2 (Figure 30). Negative power supply
prevents a dynamic turn on through the internal
IGBT/MOSFET input capacitance
In Unipolar power supply the driver is typically supplied
with a positive voltage of 15 V at VDD2. Unwanted
turn−on caused by the internal IGBT/MOSFET Miller
capacitance could be prevented by Active Miler Clamp
function (variant A). CLAMP output should be directly
connected to IGBT/MOSFET gate (Figure 28)
10 mF 100nF
+
−
Power Supply (VDD1, VDD2, VEE2)
10 mF 100nF
+
−
VDD2
Figure 30. Bipolar Power Supply (NCx5708zB)
VDD1
+
−
100nF
10 mF
VDD1
GND2
IN +
CLAMP
IN −
OUT
GND1
VDD2
10 mF
100nF
+
−
VDD2
Figure 31. Unipolar Power Supply (NCx5708zA)
VDD1
VDD1
+
−
100nF
10 mF
GND2
IN +
OUTL
IN −
OUTH
GND1
VDD2
10 mF 100nF
Figure 32. Unipolar Power Supply (NCx5708zC)
www.onsemi.com
18
+
−
VDD2
VEE2
NCx57080y, NCx57081y
Common Mode Transient Immunity (CMTI)
10μF
+
5V
+
-
VDD1
GND2
IN+
CLAMP
IN-
OUT
GND1
VDD2
S1
-
OUT must remain stable
15V
+
-
10μF
HV PULSE
FLOATING
10μF
5V
+
-
+
VDD1
GND2
IN+
OUTL
IN-
OUTH
GND1
VDD2
S1
-
OUT must remain stable
15V
+
-
10μF
HV PULSE
FLOATING
10μF
5V
+
-
+
VDD1
VEE2
IN+
GND2
S1
-
IN-
OUT
GND1
VDD2
OUT must remain stable
15V
10μF
+
-
HV PULSE
FLOATING
Figure 33. Common−Mode Transient Immunity Test Circuit
10 mils
0.25 mm
10 mils
0.25 mm
40 mils
1 mm
Keep this space free
10 mils
from traces, pads and
0.25 mm
vias
10 mils
0.25 mm
157 mils
(4 mm)
Figure 34. Recommended Layer Stack
19
Ground plane
40 mils
1 mm
10 mils
0.25 mm
www.onsemi.com
High−speed signals
Power plane
Low−speed signals
NCx57080y, NCx57081y
Figure 35. Recommended Layout for Version A/B/C
www.onsemi.com
20
NCx57080y, NCx57081y
ORDERING INFORMATION
Device
Qualification
Package
Shipping†
NCD57080ADR2G
Industrial
SOIC−8 Narrow Body
(Pb−Free)
2500 / Tape & Reel
Automotive
(AEC−Q100 Qualified and
PPAP Capable)
SOIC−8 Narrow Body
(Pb−Free)
2500 / Tape & Reel
Industrial
SOIC−8 Narrow Body
(Pb−Free)
2500 / Tape & Reel
Automotive
(AEC−Q100 Qualified and
PPAP Capable)
SOIC−8 Narrow Body
(Pb−Free)
2500 / Tape & Reel
NCD57080BDR2G
NCD57080CDR2G
NCV57080ADR2G*
NCV57080BDR2G*
NCV57080CDR2G*
NCD57081ADR2G
NCD57081BDR2G
NCD57081CDR2G
NCV57081ADR2G*
NCV57081BDR2G*
NCV57081CDR2G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
www.onsemi.com
21
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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