NCV68261MTWAITBG

DATA SHEET www.onsemi.com Ideal Diode and High Side Switch NMOS Controller WDFNW6 CASE 511DW NCV68261 The NCV68261 is a Reverse Polarity Protection and Ideal Diode NMOS Controller with optional High Side Switch function, intended as a lower loss and lower forward voltage replacement for power rectifier diodes and mechanical power switches. The controller operates in conjunction with one or two N−channel MOSFETs and sets the ON/OFF state of the transistors based on the state of the Enable pin and the Input−to−Drain differential voltage polarity. Depending on the Drain pin connection, both Ideal Diode and High Side Switch applications can operate in two different modes. With the Drain pin connected to the load, the applications are in Ideal Diode mode, whereas with the Drain pin connected to ground, the applications are merely in Reverse Polarity Protection mode. S 1 G 2 D 3 • • • • • • • 6 IN 5 GND 4 EN WDFNW6 (Top View) MARKING DIAGRAMS Features • • • • Thermal Pad PIN ASSIGNMENT V6MG Operating Voltage Range: up to 32 V G Immune to 60 V Load Dump Pulse Immune to −40 V Negative Transient V6 = Specific Device Code M = Month Code Overvoltage Protection G = Pb−Free Package ♦ Disconnects the load from battery at VIN = 35.6 V typ (Note: Microdot may be in either location) Enable Function (3.3 V Logic Compatible Thresholds) Ideal Diode Function ORDERING INFORMATION ♦ Protecting against Reverse Current Flow (from Output to Input) See detailed ordering and shipping information on page 15 of this data sheet. Reverse Polarity Protection (RPP) Function ♦ Protecting against Negative Supply Typical Applications High Side Switch with Ideal Diode • Automotive Battery Regulation High Side Switch with Reverse Polarity Protection • Industrial Power Supply NCV Prefix for Automotive and Other Applications • Rectifier Requiring Unique Site and Control Change Requirements; AEC−Q100 Grade 1 Qualified and • High Side Switch PPAP Capable • Vehicle Control Module These Devices are Pb−Free and are RoHS Compliant Battery Battery Protected Battery CIN S IN EN G D NCV68261 + CIN Cbulk EN Figure 1. NCV68261 Application Schematic (Ideal Diode) May, 2022 − Rev. 1 S IN GND © Semiconductor Components Industries, LLC, 2020 Protected Battery G NCV68261 D + Cbulk GND Figure 2. NCV68261 Application Schematic (Ideal Diode + High Side Switch) 1 Publication Order Number: NCV68261/D NCV68261 Battery Protected Battery G S CIN + D NCV68261 IN EN Battery Protected Battery G S CIN Cbulk IN Figure 3. NCV68261 Application Schematic (Reverse Polarity Protection) + NCV68261 EN GND D Cbulk GND Figure 4. NCV68261 Application Schematic (Reverse Polarity Protection + High Side Switch) S G 1 MW Pull-down Bulk IN Discharge Switch Prereg. References EN Enable Input/ Drain + - D Logic & && 1>=11 CP_OUT- DISCH OSC+CP UVLO CP_EN + DISCH_OUT CP_OUT+ OVLO + - GND Figure 5. NCV68261 Block Diagram Table 1. PIN FUNCTION DESCRIPTION Pin No. WDFNW6 Pin Name Description 6 IN Supply voltage input, Anode of the diode and Non−inverting input of the internal comparator. Bypass directly to GND with a ceramic capacitor. Connect to the Drain of the High Side Switch NMOS or to the Source pin (see the application schematics). 5 GND 4 EN 3 D Cathode of the diode and Inverting input of the internal comparator. Bypass directly to GND with a ceramic capacitor. Connect to the Drain of the Diode NMOS or to the GND (see the application schematics). 2 G Charge pump output with discharge function. Connect to the Gate of the external NMOS (see application schematics). 1 S Reference for the Charge pump output. Connect to the Source of the external NMOS (see application schematics). Ground potential. Enable Input. High Level enables the chip. Connect to IN if enable function is not required. www.onsemi.com 2 NCV68261 Table 2. MAXIMUM RATINGS Rating Symbol Min Max Unit Input and Source Voltage DC (Note 1) VS −18 45 V Input, Source, Drain, Gate and Enable Voltage (Note 2) Load Dump − Suppressed Us* − 60 Input, Source, Gate and Enable Voltage (Note 3) Test Pulse 1 Us −40 − Gate Voltage VG −18 45 V Gate−to−Source Voltage VGS −0.3 19 V Drain Voltage VD −5 45 V Input and Source−to−Drain Voltage DC VSD −45 45 V Input and Source−to−Drain Voltage transient (Test Pulse 1) VSD −60 − V Enable Voltage VEN −18 45 V TJ −40 150 °C TSTG −55 150 °C Operating Junction Temperature Storage Temperature V V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. Load Dump Test B (with centralized load dump suppression) according to ISO 16750−2 standard. Guaranteed by design. Not tested in production. Passed Class A according to ISO 16750−1. 3. Test Pulse 1 according to ISO 7637−2 standard. Guaranteed by design. Not tested in production. Passed Class A according to ISO 16750−1. More ISO 7637−2: 2011(E) PULSE TEST RESULTS are in Table 8. Table 3. ESD CAPABILITY (Note 4) Symbol Min Max Unit ESD Capability, Human Body Model ESDHBM −2 2 kV ESD Capability, Charged Device Model ESDCDM −1 1 kV Rating 4. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (JS−001−2017) Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes smaller than 2 × 2 mm due to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current waveform characteristic defined in JEDEC JS−002−2018. Table 4. LEAD SOLDERING TEMPERATURE AND MSL (Note 5) Symbol Rating Moisture Sensitivity Level Min MSL Max 1 Unit − 5. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Table 5. THERMAL CHARACTERISTICS (Note 6) Rating Thermal Characteristics, WDFNW−6 Thermal Resistance, Junction−to−Ambient Thermal Reference, Junction−to−Case Top Symbol Value RqJA ΨqJT 157.8 37.4 Unit °C/W 6. Mounted onto a 80 x 80 x 1.6 mm single layer FR4 board (645 sq mm, 1 oz. Cu, steady state). Table 6. RECOMMENDED OPERATING RANGES Rating Symbol Min Max Unit Input Voltage VIN 3 32 V Junction Temperature TJ −40 150 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 3 NCV68261 Table 7. ELECTRICAL CHARACTERISTICS VIN = 13.5 V, VEN = 5 V, CIN = 0.1 mF, Cbulk = 1 mF, Min and Max values are valid for temperature range −40°C ≤ TJ ≤ +150°C unless noted otherwise and are guaranteed by test, design or statistical correlation. Typical values are referenced to TJ = 25°C Parameter Test Conditions Symbol Min Typ Max Unit CHARGE PUMP OPERATION Undervoltage Lockout VIN rising VIN falling (Gate Discharge) VIN_UVLO − 3 3.4 3.25 3.65 − V Overvoltage Lockout VIN rising Hysteresis (VIN falling) VIN_OVLO 32 − 35.6 0.8 42 − V Gate−to−Source Charged Voltage VIN = 4 V VIN ≥ 8 V VGS 3 9 4 11.3 − 15 V 100 −40 140 −10 220 0 70 170 100 320 − − Input−to−Drain Voltage Threshold Gate Charge Gate Discharge Vth(IN−D) VIN−D rising VIN−D falling IG_Charge mV Gate Charge Current VGS = 0 V, VIN−D = 220 mV VIN = 4 V VIN = 13.5 V Gate Discharge Peak Current VGS = 10 V, VIN−D ≤ −100 mV IG_Disch − 1.65 − A Discharge Switch RDS(ON) VGS = 100 mV, VIN−D ≤ −100 mV RDS(on) 1 2.4 5 W Response Time (Time from Reverse Voltage Condition to VGS = 9 V) VGS = 10 V, VIN = 13.5 V, VIN−D = step from 250 mV to −150 mV trt_OFF − 0.2 0.6 − 1.1 − MW IDIS − − 5 mA Iq − 210 295 mA 0.99 − 1.7 1.8 − 2.31 − − − 11 3.2 0.010 − 5 1 − 0.9 4 Gate−to−Source Static Resistance mA ms DISABLE AND QUIESCENT CURRENTS Disable Current VEN = 0 V Quiescent Current IGS = 0 mA, VIN−D = 220 mV (CP active) ENABLE Vth(EN) Enable Input Threshold Voltage Logic Low Logic High VGS ≤ 0.1 V VGS ≥ 4.9 V Enable Input Current Logic High Logic High Logic Low VEN = 13.5 V VEN = 5 V VEN = 0 V Response Time (Time from EN High− to−Low to VGS = 9 V) VGS = 10 V, VIN = 13.5 V, VEN = step from 5 V to 0 V IEN_ON IEN_ON IEN_OFF trt_EN_OFF V mA ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 4 NCV68261 12.5 IG_Charge, GATE CHARGE CURRENT (mA) VGS, GATE−TO−SOURCE CHARGED VOLTAGE (V) TYPICAL CHARACTERISTICS TJ = 150°C 11.5 10.5 TJ = −40°C TJ = 25°C TJ = 125°C 9.5 8.5 7.5 6.5 5.5 4.5 3.5 2.5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 400 TJ = −40°C 350 300 TJ = 125°C 250 TJ = 150°C 200 150 100 50 2 Figure 7. Gate Charge Current vs. Input Voltage 0.4 RDS(on), DISCHARGE SWITCH ON RESISTANCE (W) VIN = 4 V VIN = 8 V to 32 V 2.0 1.5 1.0 −50 −30 −10 VIN−D = −100 mV VGS = 100 mV 10 30 50 70 90 trt_OFF, RESPONSE TIME IN REVERSE CONDITION (ms) 0.35 2.5 0.3 0.25 0.15 0.1 0.05 0 −50 −30 −10 110 130 150 1.4 VIN = 13.5 V VIN = 32 V 0.8 0.6 VIN = 4 V 0.4 0.2 20 40 60 80 30 50 70 90 110 130 150 100 Figure 9. Charge Pump Output Response Time in Reverse Condition (from VIN−D = 0 V to VGS = 9 V) vs. Temperature Vth(IN−D), INPUT−TO−DRAIN VOLTAGE THRESHOLDS (mV) tDisch, DISCHARGE TIME (ms) TJ = 25°C 1.0 10 TJ, JUNCTION TEMPERATURE (°C) Figure 8. Discharge Switch On Resistance vs. Temperature 1.2 VIN = 8 V to 32 V 0.2 TJ, JUNCTION TEMPERATURE (°C) 0 8 10 12 14 16 18 20 22 24 26 28 30 32 34 Figure 6. Gate−to−Source Charged Voltage vs. Input Voltage 3.0 0 6 VIN, INPUT VOLTAGE (V) 3.5 1.6 4 VIN, INPUT VOLTAGE (V) 4.0 1.8 TJ = 25°C 200 180 VIN = 13.5 V 160 VIN−D rising 140 120 100 80 60 40 20 0 VIN−D falling −20 −40 −50 −30 −10 CGS, GATE−SOURCE CAPACITANCE (nF) 10 30 50 70 90 110 130 150 TJ, JUNCTION TEMPERATURE (°C) Figure 10. Discharge Time (from VIN−D = 0 V to VGS = 0 V) vs. Gate−Source Capacitance Figure 11. Input−to−Drain Voltage Thresholds vs. Temperature www.onsemi.com 5 NCV68261 TYPICAL CHARACTERISTICS 300 260 Iq, QUIESCENT CURRENT (mA) TJ = 25°C 280 Charge pump ON 240 220 200 180 160 Charge pump OFF 140 120 100 2 4 6 260 240 200 180 160 120 10 30 50 70 90 110 130 150 Figure 13. Quiescent Current vs. Temperature 0.25 0.2 0.15 VIN = 13.5 V 0.1 VIN = 4 V 0.05 0 −50 −30 −10 10 30 50 70 90 110 130 150 TJ, JUNCTION TEMPERATURE (°C) 2.2 TJ = 150°C 30 TJ = 125°C 25 20 TJ = 25°C 15 TJ = −40°C 10 5 2 4 6 Logic high 1.8 Logic low 1.6 1.4 1.2 1.0 −50 −30 −10 10 30 50 70 90 110 130 150 TJ, JUNCTION TEMPERATURE (°C) Figure 15. Enable Voltage Thresholds vs. Temperature trt_EN_OFF, ENABLE RESPONSE TIME (ms) 35 VIN = 13.5 V 2.0 Figure 14. Disable Current vs. Temperature IEN, ENABLE INPUT CURRENT (mA) Charge pump OFF 140 Figure 12. Quiescent Current vs. Input Voltage VIN = 32 V 0 Charge pump ON 220 TJ, JUNCTION TEMPERATURE (°C) 0.3 0 VIN = 13.5 V VIN, INPUT VOLTAGE (V) 0.35 IDIS, DISABLE CURRENT (mA) 280 100 −50 −30 −10 8 10 12 14 16 18 20 22 24 26 28 30 32 34 Vth(EN), ENABLE VOTLAGE THRESHOLDS (V) Iq, QUIESCENT CURRENT (mA) 300 8 10 12 14 16 18 20 22 24 26 28 30 32 1 VIN = 8 V to 32 V 0.95 0.9 0.85 0.8 0.75 0.7 −50 −30 −10 10 30 50 70 90 110 130 150 VEN, ENABLE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C) Figure 16. Enable Input Current vs. Enable Voltage Figure 17. Enable Response Time (from EN High−to−Low to VGS = 9 V) vs. Temperature www.onsemi.com 6 NCV68261 VIN_OVLO, OVERVOLTAGE LOCKOUT THRESHOLDS (V) 3.4 VIN rising 3.3 VIN falling 3.2 −50 −30 −10 25 ID, DRAIN INPUT CURRENT (mA) 36 3.5 10 30 50 70 90 110 130 150 10 30 50 70 90 110 130 150 50 10 5 Charge pump ON 4 34.5 −50 −30 −10 Figure 19. Overvoltage Lockout (OVLO) Thresholds vs. Temperature Charge pump OFF 2 VIN falling 35 Figure 18. Undervoltage Lockout (UVLO) Thresholds vs. Temperature 15 0 35.5 TJ, JUNCTION TEMPERATURE (°C) TJ = 25°C VEN = 5 V 20 VIN rising TJ, JUNCTION TEMPERATURE (°C) ID, DRAIN INPUT CURRENT (nA) VIN_UVLO, UNDERVOLTAGE LOCKOUT THRESHOLDS (V) TYPICAL CHARACTERISTICS 6 TJ = 25°C 45 VEN = 0 V 40 VD = VIN − 220 mV 35 30 25 20 15 10 5 0 8 10 12 14 16 18 20 22 24 26 28 30 32 34 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 VIN, INPUT VOLTAGE (V) VIN, INPUT VOLTAGE (V) Figure 20. Drain Input Current vs. Input Voltage Figure 21. Drain Input Current vs. Input Voltage www.onsemi.com 7 NCV68261 TYPICAL CHARACTERISTICS Table 8. ISO 7637−2: 2011(E) PULSE TEST RESULTS ISO 7637−2:2011(E) Test Pulse Test Severity Levels, 12 V System I / II III IV Delays and Impedance # of Pulses or Test Time Pulse / Burst Rep. Time 1 −75 −112 −150 2 ms, 10 W 500 pulses 0.5 s 2a +37 +55 +112 0.05 ms, 2 W 500 pulses 0.5 s 3a −112 −165 −220 0.1 ms, 50 W 1h 100 ms 3b +75 +112 +150 0.1 ms, 50 W 1h 100 ms Test Results ISO 7637−2:2011(E) Test Pulse I / II III 1 A E 2a 3a 3b A A IV E E A E Class Functional Status A All functions of a device perform as designed during and after exposure to disturbance. B All functions of a device perform as designed during exposure. However,one or more of them can go beyond specified tolerance. All functions return automatically to within normal limits after exposure is removed. Memory functions shall remain class A. C One or more functions of a device do not perform as designed during exposure but return automatically to normal operation after exposure is removed. D One or more functions of a device do not perform as designed during exposure and do not return to normal operation until exposure is removed and the device is reset by simple ”operator/use” action. E One or more functions of a device do not perform as designed during and after exposure and cannot be returned to proper operation without replacing the device. www.onsemi.com 8 NCV68261 APPLICATION INFORMATION INTEGRATED CIRCUIT AND BLOCK DIAGRAM DESCRIPTION UVLO Comparator The undervoltage lockout (UVLO) comparator compares the Input voltage level with an internal reference voltage level. When the Input voltage falls below the UVLO threshold, the output of the UVLO comparator is set to low resulting in turning OFF the charge pump and switching OFF the external NMOS transistors. Integrated Circuit Description The NCV68261 can operate in conjunction with one or two external NMOS transistors. Two basic applications can be configured: an Ideal diode application or a Reverse Polarity Protection application defined by the Drain pin connection as shown in the Table 9. The applications with single NMOS are always forward conductive. The applications with two NMOS transistors provide a High Side Switch function to control the power supplied to the application. OVLO Comparator The overvoltage lockout (OVLO) comparator compares the Input voltage level with an internal reference voltage level. When the Input voltage rises above the OVLO threshold, the output of the OVLO comparator is set to high resulting in turning OFF the charge pump and switching OFF the external NMOS transistors. Enable The Enable block turns the controller ON and OFF. If the Enable function is not needed, then the Enable pin can be connected to the Input pin for permanent operation. Logic The Logic block controls the Charge Pump block according to the inputs from the Input/Drain, UVLO and OVLO comparators. The truth table of the logic function is shown in Table 10. References The References block provides voltage references and voltage supply for other internal circuitry. This block is supplied from the Input and controlled by the Enable block. Pre−regulator The pre−regulator provides a stable voltage supply for the Charge Pump block. Input/Drain Comparator This comparator compares voltage levels at the Input and Drain pins. Based on the Drain pin connection, the applications can be designed with both Reverse Current Protection and Reverse Polarity Protection features active (Figures 22 and 23) or with Reverse Polarity Protection only (Figures 24 and 25). Oscillator and Charge Pump The oscillator generates an approximately 2 MHz clock signal that drives the charge pump. The charge pump generates the Gate−Source voltage from the voltage provided by the pre−regulator. The OSC+CP block drives the discharge switch as well. Table 9. AVAILABLE PROTECTION FEATURES Protection Features Drain Pin Connection Reverse Current Protection Reverse Polarity Protection Load Side (Protected Battery) (see Figures 22 and 23) Yes Yes GND (see Figures 24 and 25) No Yes Table 10. TRUTH TABLE OF THE LOGIC BLOCK (@ EN = HIGH) Input/Drain Comparator UVLO Comparator OVLO Comparator Disch CP_EN NMOS VIN < VD VIN < VIN_UVLO X TRUE FALSE OFF VIN < VD VIN > VIN_UVLO VIN < VIN_OVLO TRUE FALSE OFF VIN < VD VIN > VIN_UVLO VIN > VIN_OVLO TRUE FALSE OFF VIN > VD VIN < VIN_UVLO X TRUE FALSE OFF VIN > VD VIN > VIN_UVLO VIN < VIN_OVLO FALSE TRUE ON VIN > VD VIN > VIN_UVLO VIN > VIN_OVLO TRUE FALSE OFF www.onsemi.com 9 NCV68261 Operation the charge pump and the NMOS transistor are disabled. As the Input voltage becomes greater than the Drain voltage, forward current flows through the body diode of the NMOS transistor. Once this forward voltage drop exceeds the Input−to−Drain Gate Charge Voltage Threshold level (typ. 140 mV), the charge pump is turned ON and the NMOS transistor becomes fully conductive. Reverse Current Blocking: When the Input voltage becomes less than the Drain voltage, a reverse current initially flows through the conductive channel of the NMOS transistor. This current creates a voltage drop across the conductive channel of the NMOS transistor which is proportional to its RDS(ON) resistance. When this voltage crosses below the Input−to−Drain Gate Discharge Voltage Threshold (typ. −10 mV), the charge pump is disabled and the external NMOS transistor is turned OFF by an internal PMOS transistor (see Figure 5). The main function of the NCV68261 is to control the ON/OFF state of one or two external NMOS transistors depending on the state of the Enable pin and the difference between the voltages at the Input and Drain pins − as shown in Figures 22 to 25. Figure 5 illustrates the internal connections between the functional blocks described above. OFF state: When the Enable input is low, the IC is in disable mode. All the internal blocks are turned OFF, and the current consumption is reduced − typically down to tens of nano−amps. In this state, the external transistors are kept OFF by an integrated 1 MW resistor between the Gate and Source pins. ON state: When the Enable input is high, the IC is active. Further operation depends on the output state of the UVLO, OVLO and Input/Drain comparators. Table 10 shows the charge pump, gate discharge, and NMOS transistor states based on the output states of these comparators. The charge pump is turned ON only when the Input voltage level is between the UVLO and OVLO thresholds and above the Drain voltage level. Undervoltage Lockout: When the Input voltage falls below the UVLO thresholds (typ. 3.25 V), the charge pump is disabled and the external NMOS transistors are turned OFF by an internal PMOS transistor. By decreasing the Input voltage further, the chip is insufficiently powered, and the external NMOSs are kept in OFF state by the integrated 1 MW resistor (see Figure 5). Overvoltage Lockout: When the Input voltage rises above the OVLO thresholds (typ. 35.6 V), the charge pump is disabled and the external NMOS transistors are turned OFF by an internal PMOS transistor. Reverse Polarity Protection (RPP) By connecting the Drain pin to the GND potential (Figure 24), the NCV68261 does not allow a falling input voltage to discharge the output below GND potential, but it does allow the output to follow any positive input voltage between the UVLO and OVLO thresholds. When the Input voltage is between the UVLO (typ. 3.4 V) and OVLO (typ. 34.8 V) thresholds, the Input/Drain, UVLO and OVLO comparators enable the charge pump to provide Gate−Source voltage to the external NMOS transistor, which is fully conductive. For Input voltage below the UVLO (typ. 3.25 V) or above the OVLO (typ. 35.6 V) thresholds, the charge pump and the NMOS transistor are disabled, and any load current flows through the body diode of the NMOS transistor. APPLICATION CONFIGURATIONS High Side Switch (HSS) The applications with two NMOS transistors provide High Side Switch function to control the power supply of the application. The first transistor operates as a switch, while the second operates as an Ideal Diode and/or Reverse polarity protection. Ideal Diode In the Ideal Diode configuration (Figure 22), the input voltage is not allowed to discharge the output. Conduction Mode: Prior to entering the conduction mode, the Input voltage is lower than the Drain voltage, and www.onsemi.com 10 NCV68261 The Ideal Diode application in Figure 22 has rectifying properties as a common diode application, while reducing the forward voltage drop on the diode. Th application is in reverse mode as long as the Input voltage is lower than the Drain voltage. The Ideal Diode + High Side Switch (HSS) application in Figure 23 combines the features of the Ideal Diode and an Ideal Switch depending on the Enable (EN) state. If the EN is high the application is in Ideal Diode mode. If the EN is Battery low, the application behaves as an Ideal Switch and the protected battery line is disconnected from the battery line. The Reverse Polarity Protection (RPP) application in Figure 24 protects the load from negative voltages at the battery line. The Reverse Polarity Protection + High Side Switch application in Figure 25 combines the features of the RPP and HSS, similarly to the Ideal Diode + HSS. Protected Battery CIN S IN EN G D + NCV68261 Battery CIN Cbulk Battery IN EN G IN NCV68261 EN GND D + Cbulk Figure 23. Ideal Diode + High Side Switch Protected Battery CIN S GND Figure 22. Ideal Diode S Protected Battery G D + NCV68261 Battery Protected Battery CIN Cbulk S G IN NCV68261 EN GND D + Cbulk GND Figure 24. Reverse Polarity Protection Figure 25. Reverse Polarity Protection + High Side Switch www.onsemi.com 11 NCV68261 Figure 26. Application Response to 13 V + 6 Vpp Sine Wave on the Input (VIN) – Ideal Diode + High Side Switch Application (see Figure 23) Figure 27. Application Response to 11 V to 0 V Transient on the Input (VIN) − Ideal Diode + High Side Switch Application (see Figure 23) Figure 28. Application response to 11 V to −18 V transient on the Input (VIN) – Reverse Polarity Protection + High Side Switch Application (see Figure 25) www.onsemi.com 12 NCV68261 n CIN Capacitor Considerations – the number of external transistors used in the application (n = 1 for Ideal Diode or RPP applications, n = 2 for Ideal Diode +HSS or RPP +HSS) RDS(ON) – ON resistance of the external NMOS transistor tdrop – the expected duration of the battery voltage drop DUout – the maximum allowed drop of the output voltage For proper device performance, it is recommended that a 0.1 mF ceramic capacitor be placed as close as possible to the NCV68261 and connected with the shortest possible traces. If the device is used in High Side Switch configuration, the CIN capacitor should be large enough to cover the inrush currents flowing into the application during the startup event. Cbulk (Output) Capacitor Considerations Besides presenting a sufficiently low impedance for the load input rail, in an Ideal Diode application the Cbulk capacitance should be high enough to maintain adequate voltage while providing load current for the duration of battery sag plus the charge from reverse current spike before the NMOS transistor turns off. Capacitor ESR is also limited by the RDS(ON) of the NMOS, as high ESR can reduce reverse current flow below that needed to create sufficient NMOS reverse voltage drop (see Figure 26). The value of the Cbulk capacitor can be calculated according to the Equation 1: t Disch @ C bulk + where: tDisch DUin DUin n@RDS(ON) ) I load @ t drop NMOS Transistor Considerations In general, any NMOS can be connected to the NCV68261. There are no special requirements for the transistor. From the NCV68261 perspective, the Gate to Source maximum voltage of the transistor should be rated above a 15 V level (see Table 7 with electrical characteristics) unless an external voltage protection is applied to protect the Gate−Source structure from a breakdown. EMC and Dynamic Performance Considerations To improve the EMC immunity to Direct Power Injection, it is recommended to use the application example and PCB layout shown in Figures 29 and 30. The recommended application contains additional capacitor connected to the Gate and GND pins respectively. The recommended component values are listed in the Table 11. The CG capacitance limits inrush current as well. The typical measurements are shown in Figures 31 to 33. The RG_Q1 and RS mitigate potential oscillations of the output voltage during start up. (eq. 1) DU out – discharge time for the given Gate−Source capacity of the external NMOS (see Figure 10) – expected battery voltage drop Q1 Q2 Battery Protected Battery RG_Q1 CIN 10 mF 10 W S IN EN G RS CG 10 W 1 nF Cbulk 10 mF D NCV68261 GND Figure 29. Application Example for Optimized EMC Performance and Inrush Current Control Figure 30. PCB Layout Example www.onsemi.com 13 NCV68261 Table 11. RECOMMENDED COMPONENTS FOR OPTIMAL EMC PERFORMANCE (Note 7) CIN (mF) Cbulk (mF) 0.1 1 0.1 10 4.7 10 10 10 10 10 CG (nF) 1 RS (W) RG_Q1 (W) 10 10 4.7 7. Global pins: up to 33 dBm Local pins: up to 17 dBm Table 12. RECOMMENDED EXTERNAL COMPONENT PART NUMBERS Component Value/Rating Part Number CG 1 nF/100 V GCM1885C2A102JA16 CG 4.7 nF/100 V GCM188R72A472KA37 CIN 100 nF/100 V GRM188R72A104KA64 Cbulk 1 mF/50 V GCM21BR71H105KA03 CIN 4.7 mF/50 V GCM32ER71H475KA55 CIN, Cbulk 10 mF/50 V GCM32EC71H106KA03 RS, RG_Q1 10 W MC0063W0603110R Figure 31. Startup with EN − No Inrush Current Reduction www.onsemi.com 14 NCV68261 Figure 32. Startup with EN − CG = 1 nF Inrush Current Reduction Figure 33. Startup with EN − CG = 4.7 nF Inrush Current Reduction Thermal Considerations PCB Layout Considerations The NCV68261 has no thermal protection function as it is not designed to handle large currents itself. Regarding the application, the most heated elements are the external NMOS transistors. In case an SMD transistors are used, maximum power dissipation, thermal resistance of the NMOSs and cooling area of the PCB should be considered to keep the junction temperature of the controller below 150°C. For optimal performance, place the transistors and the input and output capacitors as close as possible to the NCV68261. Tracks carrying high load current − Input (Battery), Source, Drain (Protected Battery) and GND are recommended to connect using power planes on the PCB. An example PCB Layout with inrush current reduction circuitry is shown in Figure 30. ORDERING INFORMATION Device NCV68261MTWAITBG Application Marking Package Shipping† Ideal Diode and High Side Switch V6 WDFNW6 (Pb−Free) 3,000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 15 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFNW6 2x2, 0.65P CASE 511DW ISSUE B DATE 15 JUN 2018 SCALE 4:1 GENERIC MARKING DIAGRAM* XXMG G M G = Month Code = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON79327G WDFNW6 2x2, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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