NCV70522MN003R2G

AMIS-30522, NCV70522 Micro-Stepping Motor Driver Introduction The AMIS−30522/NCV70522 is a micro−stepping stepper motor driver for bipolar stepper motors. The chip is connected through I/O pins and a SPI interface with an external microcontroller. The AMIS−30522/NCV70522 contains a current−translation table. It takes the next micro−step depending on the clock signal on the “NXT” input pin and the status of the “DIR” (= direction) register or input pin. The chip provides a so−called “Speed and Load Angle” output. This allows the creation of stall detection algorithms and control loops based on load−angle to adjust torque and speed. It is using a proprietary PWM algorithm for reliable current control. The AMIS −30522/NCV70522 is implemented in I 2 T100 technology, enabling both high voltage analog circuitry and digital functionality on the same chip. The chip is fully compatible with the automotive voltage requirements. The 522 is ideally suited for general purpose stepper motor applications in the automotive, industrial, medical and marine environment. The AMIS−30522 is intended for use in industrial applications. The NCV70522 version is qualified for use in automotive applications. Features http://onsemi.com PINOUT POR/WD MOTXP 26 VBB MOTXP 25 24 GND 23 GND 22 MOTXN 21 MOTXN 20 MOTYN 19 MOTYN 18 GND 17 GND 9 CPN 10 CPP 11 VCP 12 CLR 13 CS 14 VBB 15 MOTYP 16 MOTYP DO TSTO 30 29 VDD 32 GND DI CLK NXT DIR ERR SLA 1 2 3 4 5 6 7 8 31 28 27 AMIS−30522/ NCV70522 • Dual H−Bridge for 2 Phase Stepper Motors • Programmable Peak−Current up to 1.2 A Continuous (1.5 A Short • • • • • • • • • • • • • • • • Time), Using a 5−Bit Current DAC On−Chip Current Translator SPI Interface Speed and Load−Angle Output 7 Step Modes from Full−Step up to 32 Micro−Steps Fully Integrated Current−Sense PWM Current Control with Automatic Selection of Fast and Slow Decay Low EMC PWM with Selectable Voltage Slopes Active Fly−back Diodes Full Output Protection and Diagnosis Thermal Warning and Shutdown Digital IO’s Compatible with 5 V and 3.3 V Microcontrollers Integrated 5 V Voltage Regulator to Supply an External Microcontroller Integrated Reset Function to Reset External Microcontroller Integrated Watchdog Function NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes These are Pb−Free Devices* ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 27 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 December, 2009 − Rev. 0 1 Publication Order Number: AMIS−30522/D AMIS−30522, NCV70522 Table of Contents Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 4 Equivalent Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 5 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended Operation Conditions . . . . . . . . . . . . . . . . 5 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPI Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . 10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Warning, Error Detection and Diagnostics Feedback . . 18 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 http://onsemi.com 2 AMIS−30522, NCV70522 CPN CPP VCP VDD VBB CLK Timebase Charge Pump Vreg EMC PWM MOTXP POR CS TRANSLATOR DI DO NXT DIR SLA POR/WD CLR ERR Temp. Sense Logic & Registers Load Angle SPI OTP I−sense MOTXN EMC PWM MOTYP I−sense MOTYN Band− AMIS−30522/NCV70522 gap TST0 GND Figure 1. Block Diagram AMIS−30522/NCV70522 Table 1. PIN DESCRIPTION Name GND DI CLK NXT DIR ERR SLA / CPN CPP VCP CLR CS VBB MOTYP GND MOTYN MOTXN GND MOTXP VBB POR/WD TST0 / DO VDD Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15, 16 17, 18 19, 20 21, 22 23, 24 25, 26 27 28 29 30 31 32 Ground SPI Data In SPI Clock Input Next Micro−Step Input Direction Input Error Output (Open Drain) Speed Load Angle Output No Function (to be Tied to Ground) Negative Connection of Charge Pump Capacitor Positive Connection of Charge Pump Capacitor Charge−Pump Filter−Capacitor “Clear” = Chip Reset Input SPI Chip Select Input High Voltage Supply Input Positive End of Phase Y Coil Output Ground Negative End of Phase Y Coil Output Negative End of Phase X Coil Output Ground Positive End of Phase X Coil Output High Voltage Supply Input Power On Reset and Watchdog Reset Output Test Pin Input (to be Tied to Ground in Normal Operation) No Function (to be Tied to Ground) SPI Data Output (Open Drain) Logic Supply Output (Needs External Decoupling Capacitor) Digital Output Supply Type 4 Type 3 High Voltage High Voltage High Voltage Digital Input Digital Input Supply Driver Output Supply Driver Output Driver Output Supply Driver Output Supply Digital Output Digital Input Type 3 Type 4 Type 1 Type 2 Type 3 Description Type Supply Digital Input Digital Input Digital Input Digital Input Digital Output Analog Output Type 2 Type 2 Type 2 Type 2 Type 4 Type 5 Equivalent Schematic http://onsemi.com 3 AMIS−30522, NCV70522 Table 2. ABSOLUTE MAXIMUM RATINGS Symbol VBB TST TJ VESD VESD Parameter Analog DC Supply Voltage (Note 1) Storage Temperature Junction Temperature (Note 2) Electrostatic Discharges on Component Level, All Pins (Note 3) Electrostatic Discharges on Component Level, HiV Pins (Note 4) Min −0.3 −55 −50 −2 −8 Max +40 +160 +175 +2 +8 Unit V °C °C kV kV Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. For limited time < 0.5 s 2. Circuit functionality not guaranteed. 3. Human Body Model (100 pF via 1.5 kW, according to JEDEC EIA−JESD22−A114−B) 4. HiV = High Voltage Pins MOTxx, VBB, GND; Human Body Model (100 pF via 1.5 kW, according to JEDEC EIA−JESD22−A114−B) Table 3. THERMAL RESISTANCE Thermal Resistance Junction−to−Ambient Package NQFP−32 Junction−to−Exposed Pad 0.95 1S0P Board 60 2S2P Board 30 Unit K/W EQUIVALENT SCHEMATICS The following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified representations of the circuits used. IN Rpd 4k OUT TYPE 1: CLR Input TYPE 4: DO and ERR Open Drain Outputs Rout SLA IN 4k TYPE 2: CLK, DI, CS, NXT, DIR Inputs VDD VBB TYPE 5: SLA Analog Output VDD VBB TYPE 3: VDD and VBB Power Supply Figure 2. In− and Output Equivalent Diagrams http://onsemi.com 4 AMIS−30522, NCV70522 PACKAGE THERMAL CHARACTERISTICS The 522 is available in a NQFP32 package. For cooling optimizations, the NQFP has an exposed thermal pad which has to be soldered to the PCB ground plane. The ground plane needs thermal vias to conduct the heat to the bottom layer. Figure 3 gives an example for good power distribution solutions. For precise thermal cooling calculations the major thermal resistances of the device are given. The thermal media to which the power of the devices has to be given are: • Static environmental air (via the case) • PCB board copper area (via the exposed pad) The thermal resistances are presented in Table 5: DC Parameters. The major thermal resistances of the device are the Rth from the junction−to−ambient (Rthja) and the overall Rth from the junction−to−exposed pad (Rthjp). In the table below one can find the values for the Rthja and Rthjp, simulated according to JESD−51: The Rthja for 2S2P is simulated conform JEDEC JESD−51 as follows: • A 4−layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used • Board thickness is 1.46 mm (FR4 PCB material) • The 2 signal layers: 70 mm thick copper with an area of 5500 mm2 copper and 20% conductivity • The 2 power internal planes: 36 mm thick copper with an area of 5500 mm2 copper and 90% conductivity The Rthja for 1S0P is simulated conform JEDEC JESD−51 as follows: • A 1−layer printed circuit board with only 1 layer • Board thickness is 1.46 mm (FR4 PCB material) • The layer has a thickness of 70 mm copper with an area of 5500 mm2 copper and 20% conductivity Figure 3. Example of NQFP−32 PCB Ground Plane Layout in Top View (Preferred Layout at Top and Bottom) Recommended Operation Conditions Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the chip outside these operating Table 4. OPERATING RANGES Symbol VBB VDD TJ Analog DC supply Logic supply output voltage Junction temperature Parameter 5. No more than 100 cumulative hours in life time above Ttw ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ NQFP−32 ELECTRICAL SPECIFICATION ranges is not guaranteed. Operating outside the recommended operating ranges for extended periods of time may affect device reliability. Min +6 4.75 −40 Max +30 5.25 +172 (Note 5) Unit V V °C http://onsemi.com 5 AMIS−30522, NCV70522 Table 5. DC PARAMETERS (The DC Parameters are Given for VBB and Temperature in Their Operating Ranges Unless Otherwise Specified) Convention: Currents Flowing in the Circuit are Defined as Positive. Symbol SUPPLY INPUTS VBB IBB IBBS VDD ILoad IDDLIM ILoad_PD VDDH VDDL VDDHYS MOTOR DRIVER IMDmax,Peak IMDabs IMDrel ISET_TC1 ISET_TC2 RHS RLS3 RLS2 RLS1 RLS0 IMpd DIGITAL INPUTS Ileak VIL VIH Rpd_CLR Rpd_TST DI, CLK NXT, DIR CLR, CS CLR TST0 Input Leakage (Note 8) Logic Low Threshold Logic High Threshold Internal Pulldown Resistor Internal Pulldown Resistor TJ = 160°C 0 2.20 120 3 0.5 0.75 VDD 280 8 mA V V kW kW Max Peak Current Through Motor Coil Absolute Error on Coil Current Error On Current Ratio Icoilx/Icoily Temperature Coefficient of Coil Current Set−Level, CUR[4:0] = 0...27 Temperature Coefficient of Coil Current Set−Level, CUR[4:0] = 28...31 MOTXP MOTXN MOTYP MOTYN On−Resistance High−Side Driver, (Note 9) CUR[4:0] = 0...31 On−Resistance Low−Side Driver, (Note 9) CUR[4:0] = 23...31 On−Resistance Low−Side Driver, (Note 9) CUR[4:0] = 16...22 On−Resistance Low−Side Driver, (Note 9) CUR[4:0] = 9...15 On−Resistance Low−Side Driver, (Note 9) CUR[4:0] = 0...8 Pulldown Current TJ ≤ 160°C TJ ≤ 160°C VBB = 12 V, TJ = 27°C VBB = 12 V, TJ = 160°C VBB = 12 V, TJ = 27°C VBB = 12 V, TJ = 160°C VBB = 12 V, TJ = 27°C VBB = 12 V, TJ = 160°C VBB = 12 V, TJ = 27°C VBB = 12 V, TJ = 160°C VBB = 12 V, TJ = 27°C VBB = 12 V, TJ = 160°C HiZ Mode TJ = −40°C TJ = 125°C −10 −7 −240 −490 0.45 0.94 0.45 0.94 0.90 1.9 1.8 3.8 3.6 7.5 1 0.56 1.25 0.56 1.25 1.2 2.5 2.3 5.0 4.5 10 1600 10 7 mA % % ppm/K ppm/K W W W W W W W W W W mA VDD VDD VBB Nominal Operating Supply Range Total Current Consumption Sleep Current in VBB (Note 7) Logic Supply Output Voltage Maximum Output Current Current Limitation Output Current in Power Down Mode 1 6 V ≤ VBB ≤ 8 V 8 V ≤ VBB ≤ 30 V Unloaded Outputs Unloaded Outputs 4.75 15 50 150 5 6 30 8 100 5.25 V mA mA V mA mA mA mA Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit POWER ON RESET (POR) (Note 10) Internal POR Comparator Threshold Internal POR Comparator Threshold Hysteresis Between VDDH and VDDL VDD Rising VDD Falling 0.10 3.85 4.20 3.85 0.35 0.60 4.55 V V V 6. Current with oscillator running, all analogue cells active, SPI communication and NXT pulses applied. No floating inputs. Guaranteed by design. 7. Current with all analogue cells in power down. Logic is powered but no clocks running. All outputs unloaded, no inputs floating. 8. Not valid for pins with internal Pulldown resistor 9. Characterization Data Only 10. POR is derived from VDD. For proper POR operation VBB needs to be minimal VBB_min. http://onsemi.com 6 AMIS−30522, NCV70522 Table 5. DC PARAMETERS (The DC Parameters are Given for VBB and Temperature in Their Operating Ranges Unless Otherwise Specified) Convention: Currents Flowing in the Circuit are Defined as Positive. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit DIGITAL OUTPUTS VOL Ttw Ttsd (Notes 11, 12) CHARGE PUMP 6 V ≤ VBB ≤ 14 V Vcp VCP Output Voltage 14 V < VBB ≤ 30 V External Buffer Capacitor CPP CPN External Pump Capacitor VBB + 10 180 180 220 220 2 * VBB − 2.5 VBB + 15 470 470 DO, ERR Logic Low Level Open Drain IOL = 5 mA 138 145 Ttw + 20 0.30 V THERMAL WARNING AND SHUTDOWN Thermal Warning Thermal Shutdown 152 °C °C V Cbuffer Cpump nF nF PACKAGE THERMAL RESISTANCE VALUES Rthja NQFP Rthjp Thermal Resistance Junction−to−Ambient Thermal Resistance Junction−to−Exposed Pad Simulated Conform JEDEC JESD−51, (2S2P) 30 0.95 K/W K/W SPEED AND LOAD ANGLE OUTPUT Vout Voff SLA Gsla Rout Cload Gain of SLA Pin = VBEMF / VCOIL Output Resistance SLA Pin Load Capacitance SLA Pin Output Voltage Range Output Offset SLA Pin SLAG = 0 SLAG = 1 SLAG = 0 SLAG = 1 0.2 −50 −30 0.5 0.25 0.23 1.0 50 kW pF VDD − 0.2 50 30 V mV mV 11. No more than 100 cumulative hours in life time above Ttw 12. Thermal shutdown is derived from Thermal Warning http://onsemi.com 7 AMIS−30522, NCV70522 Table 6. AC PARAMETERS (The AC Parameters are Given for VBB and Temperature in Their Operating Ranges) Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit INTERNAL OSCILLATOR fosc MOTORDRIVER fPWM fd PWM Frequency MOTxx Double PWM Frequency PWM Jitter Depth (Note 13) EMC[1:0] = 00 tbrise MOTxx Turn−On Voltage Slope, 10% to 90% (Note 13) EMC[1:0] = 01 EMC[1:0] = 10 EMC[1:0] = 11 EMC[1:0] = 00 tbfall MOTxx Turn−off Voltage Slope, 90% to 10% (Note 13) EMC[1:0] = 01 EMC[1:0] = 10 EMC[1:0] = 11 DIGITAL OUTPUTS tH2L DO ERR Output Falltime from VinH to VinL Capacitive Load 400 pF and Pullup Resistor of 1.5 kW 50 ns Frequency Depends Only on Internal Oscillator 20.8 41.6 22.8 45.6 10 150 100 50 25 150 100 50 25 24.8 49.6 kHz kHz % fPWM V/ms V/ms V/ms V/ms V/ms V/ms V/ms V/ms Frequency of Internal Oscillator 3.6 4.0 4.4 MHz CHARGE PUMP fCP tCPU tCLR tNXT_HI tNXT_LO tDIR_SET tDIR_HOLD POWER UP tPU tPD tPOR tRF WATCHDOG tWDTO tWDPR Watchdog Time Out Interval Prohibited Watchdog Acknowledge Delay 32 2.0 512 ms ms PORB/ WD Power−Up Time Power−Down Time Reset Duration Reset Filter Time VBB = 12 V, ILOAD = 50 mA, CLOAD = 220 nF external conditions 100 1.0 110 ms ms ms ms NXT CPN CPP MOTxx Charge Pump Frequency Startup Time of Charge Pump (Note 14) Spec External Components 250 5.0 kHz ms CLR FUNCTION CLR Minimum Time for Hard Reset 100 ms NXT FUNCTION NXT Minimum, High Pulse Width NXT Minimum, Low Pulse Width NXT Hold Time, Following Change of DIR NXT Hold Time, Before Change of DIR See Figure 4 See Figure 4 See Figure 4 See Figure 4 2.0 2.0 2.0 2.0 ms ms ms ms 13. Characterization Data Only 14. Guaranteed by design. http://onsemi.com 8 AMIS−30522, NCV70522 tNXT_HI tNXT_LO NXT 0.5 VCC tDIR_SET tDIR_HOLD DIR VALID Figure 4. NXT−Input Timing Diagram Table 7. SPI TIMING PARAMETERS Symbol tCLK tCLK_HIGH tCLK_LOW tSET_DI tHOLD_DI tCSB_HIGH tSET_CSB tSET_CLK SPI Clock Period SPI Clock High Time SPI Clock Low Time Parameter DI Setup Time, Valid Data Before Rising Edge of CLK DI Hold Time, Hold Data After Rising Edge of CLK CS High Time CS Setup Time, CS Low Before Rising Edge of CLK CLK Setup Time, CLK Low Before Rising Edge of CS CS tSET_CSB 0.2 VCC tCLK 0.8 VCC tSET_CLK CLK 0.2 VCC tCLK_HI tCLK_LO tHOLD_DI 0.8 VCC VALID tSET_DI DI Figure 5. SPI Timing http://onsemi.com 9 ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ Min 1 100 100 50 50 2.5 100 100 Typ Max Unit ms ns ns ns ns ms ns ns 0.2 VCC 0.2 VCC ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ ÌÌ ÌÌ ÌÌ ÌÌÌ ÌÌÌ ÌÌÌ AMIS−30522, NCV70522 TYPICAL APPLICATION SCHEMATIC 100 nF C5 R2 R3 R 4 C4 C2 VDD 32 POR/WD DIR NXT DO DI mC CLK CS CLR ERR R1 SLA C8 28 5 4 31 2 3 13 12 6 7 1, 17, 23, 8 18 24 30 GND 15,16 19,20 AMIS−30522/ NCV70522 10 25,26 21,22 CPP 100 nF 100 nF + 100 nF C3 VBB 14 C1 100 mF C6 VBB 220 nF 27 VCP 11 9 CPN C7 220 nF D1 VBAT MOTXP MOTXN MOTYP MOTYN M 29 TSTO Figure 6. Typical Application Schematic AMIS−30522/NCV70522 Table 8. EXTERNAL COMPONENTS LIST AND DESCRIPTION Component C1 C2, C3 C4 C5 C6 C7 C8 R1 R2, R3 D1 Function VBB Buffer Capacitor (Low ESR < 1 W) VBB Decoupling Block Capacitor VDD Buffer Capacitor VDD Buffer Capacitor Charge−Pump Buffer Capacitor Charge−Pump Pumping Capacitor Low Pass Filter SLA Low Pass Filter SLA Pullup Resistor Open Drain Output Reverse Protection Diode Typ. Value 100 100 220 100 220 220 1 5.6 4.7 MURD530 Tolerance −20 +80% −20 +80% $20% $20% $20% $20% $20% $1% $1% Unit mF nF nF nF nF nF nF kW kW http://onsemi.com 10 AMIS−30522, NCV70522 FUNCTIONAL DESCRIPTION H−Bridge Drivers A full H−bridge is integrated for each of the two stator windings. Each H−bridge consists of two low−side and two high−side N−type MOSFET switches. Writing logic ‘0’ in bit disables all drivers (High−Impedance). Writing logic ‘1’ in this bit enables both bridges and current can flow in the motor stator windings. In order to avoid large currents through the H−bridge switches, it is guaranteed that the top− and bottom switches of the same half−bridge are never conductive simultaneously (interlock delay). A two−stage protection against shorts on motor lines is implemented. In a first stage, the current in the driver is limited. Secondly, when excessive voltage is sensed across the transistor, the transistor is switched−off. In order to reduce the radiated/conducted emission, voltage slope control is implemented in the output switches. The output slope is defined by the gate−drain capacitance of output transistor and the (limited) current that drives the gate. There are two trimming bits for slope control (See Table 12 SPI Control Parameter Overview EMC[1:0]). The power transistors are equipped with so−called “active diodes”: when a current is forced through the transistor switch in the reverse direction, i.e. from source to drain, then the transistor is switched on. This ensures that most of the current flows through the channel of the transistor instead of through the inherent parasitic drain−bulk diode of the transistor. Depending on the desired current range and the micro−step position at hand, the RDS(on) of the low−side Icoil Set value transistors will be adapted such that excellent current−sense accuracy is maintained. The RDS(on) of the high−side transistors remain unchanged, see also the DC−parameter table for more details. PWM Current Control A PWM comparator compares continuously the actual winding current with the requested current and feeds back the information to a digital regulation loop. This loop then generates a PWM signal, which turns on/off the H−bridge switches. The switching points of the PWM duty−cycle are synchronized to the on−chip PWM clock. The frequency of the PWM controller can be doubled to reduce the over−all current−ripple with a factor of two. To further reduce the emission, an artificial jitter can be added to the PWM frequency. (see Table 12, SPI Control Register 1). The PWM frequency will not vary with changes in the supply voltage. Also variations in motor−speed or load−conditions of the motor have no effect. There are no external components required to adjust the PWM frequency. Automatic Forward & Slow−Fast Decay The PWM generation is in steady−state using a combination of forward and slow−decay. The absence of fast−decay in this mode, guarantees the lowest possible current−ripple “by design”. For transients to lower current levels, fast−decay is automatically activated to allow high−speed response. The selection of fast or slow decay is completely transparent for the user and no additional parameters are required for operation. Actual value 0 TPWM t Forward & Slow Decay Fast Decay & Forward Forward & Slow Decay Figure 7. Forward & Slow/Fast Decay PWM http://onsemi.com 11 AMIS−30522, NCV70522 Automatic Duty Cycle Adaptation In case the supply voltage is lower than 2*Bemf, then the duty cycle of the PWM is adapted automatically to >50% to Icoil Duty Cycle < 50% Duty Cycle > 50% maintain the requested average current in the coils. This process is completely automatic and requires no additional parameters for operation. Duty Cycle < 50% Actual value Set value t TPWM Figure 8. Automatic Duty Cycle Adaptation Step Translator Step Mode The Step Translator provides the control of the motor by means of SPI register Stepmode: SM[2:0], SPI register DIRCNTRL and input pins DIR and NXT. It is translating consecutive steps in corresponding currents in both motor coils for a given stepmode. One out of 7 possible stepping modes can be selected through SPI−bits SM[2:0] (Table 12). After power−on or hard reset, the coil−current translator is set to the default 1/32 micro−stepping at position ‘0’. Upon changing the Step Mode, the translator jumps to position 0* of the corresponding stepping mode. When remaining in the same Step Mode, subsequent translator positions are all in the same column and increased or decreased with 1. Table 10 lists the output current vs. the translator position. As shown in Figure 9 the output current−pairs can be projected approximately on a circle in the (Ix,Iy) plane. There are however two exceptions: uncompensated half step and full step. In these stepmodes the currents are not regulated to a fraction of Imax but are in all intermediate steps regulated at 100%. In the (Ix,Iy) plane the current−pairs are projected on a square. Table 9 lists the output current vs. the translator position for these cases. Table 9. SQUARE TRANSLATOR TABLE FOR FULL STEP AND UNCOMPENSATED HALF STEP Stepmode ( SM[2:0] ) 101 MSP[6:0] 000 0000 001 0000 010 0000 011 0000 100 0000 101 0000 110 0000 111 0000 Uncompensated Half−Step 0* 1 2 3 4 5 6 7 110 Full Step − 1 − 2 − 3 − 0 Coil x 0 100 100 100 0 −100 −100 −100 Coil y 100 100 0 −100 −100 −100 0 100 % of Imax http://onsemi.com 12 AMIS−30522, NCV70522 Table 10. CIRCULAR TRANSLATOR TABLE Stepmode (SM[2:0]) 000 MSP[6:0] 000 0000 000 0001 000 0010 000 0011 000 0100 000 0101 000 0110 000 0111 000 1000 000 1001 000 1010 000 1011 000 1100 000 1101 000 1110 000 1111 001 0000 001 0001 001 0010 001 0011 001 0100 001 0101 001 0110 001 0111 001 1000 001 1001 001 1010 001 1011 001 1100 001 1101 001 1110 001 1111 010 0000 010 0001 010 0010 010 0011 010 0100 010 0101 010 0110 010 0111 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 010 1110 010 1111 011 0000 011 0001 011 0010 011 0011 011 0100 011 0101 011 0110 011 0111 011 1000 011 1001 011 1010 011 1011 011 1100 011 1101 011 1110 1/32 ’0’ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 001 1/16 0* − 1 − 2 − 3 − 4 − 5 − 6 − 7 − 8 − 9 − 10 − 11 − 12 − 13 − 14 − 15 − 16 − 17 − 18 − 19 − 20 − 21 − 22 − 23 − 24 − 25 − 26 − 27 − 28 − 29 − 30 − 31 010 1/8 0* − − − 1 − − − 2 − − − 3 − − − 4 − − − 5 − − − 6 − − − 7 − − − 8 − − − 9 − − − 10 − − − 11 − − − 12 − − − 13 − − − 14 − − − 15 − − 011 1/4 0* − − − − − − − 1 − − − − − − − 2 − − − − − − − 3 − − − − − − − 4 − − − − − − − 5 − − − − − − − 6 − − − − − − − 7 − − − − − − 100 1/2 0* − − − − − − − − − − − − − − − 1 − − − − − − − − − − − − − − − 2 − − − − − − − − − − − − − − − 3 − − − − − − − − − − − − − − Coil x 0 3.5 8.1 12.7 17.4 22.1 26.7 31.4 34.9 38.3 43 46.5 50 54.6 58.1 61.6 65.1 68.6 72.1 75.5 79 82.6 84.9 87.2 89.5 91.8 93 94.1 95.3 96.5 97.7 98.8 100 98.8 97.7 96.5 95.3 94.1 93 91.8 89.5 87.2 84.9 82.6 79 75.5 72.1 68.6 65.1 61.6 58.1 54.6 50 46.5 43 38.3 34.9 31.4 26.7 22.1 17.4 12.7 8.1 Coil y 100 98.8 97.7 96.5 95.3 94.1 93 91.8 89.5 87.2 84.9 82.6 79 75.5 72.1 68.6 65.1 61.6 58.1 54.6 50 46.5 43 38.3 34.9 31.4 26.7 22.1 17.4 12.7 8.1 3.5 0 −3.5 −8.1 −12.7 −17.4 −22.1 −26.7 −31.4 −34.9 −38.3 −43 −46.5 −50 −54.6 −58.1 −61.6 −65.1 −68.6 −72.1 −75.5 −79 −82.6 −84.9 −87.2 −89.5 −91.8 −93 −94.1 −95.3 −96.5 −97.7 % of Imax http://onsemi.com 13 AMIS−30522, NCV70522 Table 10. CIRCULAR TRANSLATOR TABLE Stepmode (SM[2:0]) 000 MSP[6:0] 011 1111 100 0000 100 0001 100 0010 100 0011 100 0100 100 0101 100 0110 100 0111 100 1000 100 1001 100 1010 100 1011 100 1100 100 1101 100 1110 100 1111 101 0000 101 0001 101 0010 101 0011 101 0100 101 0101 101 0110 101 0111 101 1000 101 1001 101 1010 101 1011 101 1100 101 1101 101 1110 101 1111 110 0000 110 0001 110 0010 110 0011 110 0100 110 0101 110 0110 110 0111 110 1000 110 1001 110 1010 110 1011 110 1100 110 1101 110 1110 110 1111 111 0000 111 0001 111 0010 111 0011 111 0100 111 0101 111 0110 111 0111 111 1000 111 1001 111 1010 111 1011 111 1100 111 1101 111 1110 111 1111 1/32 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 001 1/16 − 32 − 33 − 34 − 35 − 36 − 37 − 38 − 39 − 40 − 41 − 42 − 43 − 44 − 45 − 46 − 47 − 48 − 49 − 50 − 51 − 52 − 53 − 54 − 55 − 56 − 57 − 58 − 59 − 60 − 61 − 62 − 63 − 010 1/8 − 16 − − − 17 − − − 18 − − − 19 − − − 20 − − − 21 − − − 22 − − − 23 − − − 24 − − − 25 − − − 26 − − − 27 − − − 28 − − − 29 − − − 30 − − − 31 − − − 011 1/4 − 8 − − − − − − − 9 − − − − − − − 10 − − − − − − − 11 − − − − − − − 12 − − − − − − − 13 − − − − − − − 14 − − − − − − − 15 − − − − − − − 100 1/2 − 4 − − − − − − − − − − − − − − − 5 − − − − − − − − − − − − − − − 6 − − − − − − − − − − − − − − − 7 − − − − − − − − − − − − − − − Coil x 3.5 0 −3.5 −8.1 −12.7 −17.4 −22.1 −26.7 −31.4 −34.9 −38.3 −43 −46.5 −50 −54.6 −58.1 −61.6 −65.1 −68.6 −72.1 −75.5 −79 −82.6 −84.9 −87.2 −89.5 −91.8 −93 −94.1 −95.3 −96.5 −97.7 −98.8 −100 −98.8 −97.7 −96.5 −95.3 −94.1 −93 −91.8 −89.5 −87.2 −84.9 −82.6 −79 −75.5 −72.1 −68.6 −65.1 −61.6 −58.1 −54.6 −50 −46.5 −43 −38.3 −34.9 −31.4 −26.7 −22.1 −17.4 −12.7 −8.1 −3.5 Coil y −98.8 −100 −98.8 −97.7 −96.5 −95.3 −94.1 −93 −91.8 −89.5 −87.2 −84.9 −82.6 −79 −75.5 −72.1 −68.6 −65.1 −61.6 −58.1 −54.6 −50 −46.5 −43 −38.3 −34.9 −31.4 −26.7 −22.1 −17.4 −12.7 −8.1 −3.5 0 3.5 8.1 12.7 17.4 22.1 26.7 31.4 34.9 38.3 43 46.5 50 54.6 58.1 61.6 65.1 68.6 72.1 75.5 79 82.6 84.9 87.2 89.5 91.8 93 94.1 95.3 96.5 97.7 98.8 % of Imax http://onsemi.com 14 AMIS−30522, NCV70522 IY Start = 0 Step 1 Step 2 Step 3 IX Start = 0 IY Step 1 Start = 0 IY Step 1 Step 2 I X IX Step 3 1/4th Micro Step SM[2:0] = 011 Uncompensated Half Step SM[2:0] = 101 Step 3 Full Step SM[2:0] = 110 Step 2 Figure 9. Translator Table: Circular and Square Direction Synchronization of Step Mode and NXT Input The direction of rotation is selected by means of following combination of the DIR input pin and the SPI−controlled direction bit as illustrated in Table 12. NXT Input Changes on the NXT input will move the motor current one step up/down in the translator table (even when the motor is disabled). Depending on the NXT−polarity bit (see Table 12), the next step is initiated either on the rising edge or the falling edge of the NXT input. Translator Position The translator position can be read in SPI Status Register 3. This is a 7−bit number equivalent to the 1/32th micro−step from Table 10: “Circular Translator Table” above. The translator position is updated immediately following a NXT trigger. When step mode is re−programmed to another resolution, (Figure 11), this is put in effect immediately upon the first arriving “NXT” input. If the micro−stepping resolution is increased, the coil currents will be regulated to the nearest micro−step, according to the fixed grid of the increased resolution. If however the micro−stepping resolution is decreased, then it is possible to introduce an offset (or phase shift) in the micro−step translator table. If the step resolution is decreased at a translator table position that is shared both by the old and new resolution setting, then the offset is zero and micro−stepping proceeds according to the translator table. If the translator position is not shared both by the old and new resolution setting, then the micro−stepping proceeds with an offset relative to the translator table (See Figure 11 right hand side). NXT Update Translator Position Update Translator Position Figure 10. Translator Position Timing Diagram http://onsemi.com 15 AMIS−30522, NCV70522 Change from lower to higher resolution IY DIR endpos NXT2 NXT3 NXT4 IY NXT1 DIR Change from higher to lower resolution IY endpos DIR NXT2 IX IY NXT1 startpos DIR startpos IX IX IX NXT3 Halfstep 1/4th Step 1/8th Step Halfstep Figure 11. NXT−Step−Mode Synchronization Left: change from lower to higher resolution. The left−hand side depicts the ending half−step position during which a new step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the micro−step position. Right: change from higher to lower resolution. The left−hand side depicts the ending micro−step position during which a new step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the half−step position. NOTE: It is advised to reduce the micro−stepping resolution only at micro−step positions that overlap with desired micro−step positions of the new resolution. Programmable Peak−Current The amplitude of the current waveform in the motor coils (coil peak current = Imax) is adjusted by means of an SPI parameter “CUR[4:0]” (Table 14). Whenever this parameter Peak Current Ipeak (CUR[4:0] = 11111) is changed, the coil−currents will be updated immediately at the next PWM period. Figure 12 presents the Peak−Current and Current Ranges in conjunction to the Current setting (CUR[4:0]). Current Range 3 CUR = 23 −> 31 Ipeak (CUR[4:0] = 10110) Current Range 2 CUR = 16 −> 22 Ipeak (CUR[4:0] = 01111) Ipeak (CUR[4:0] = 01000) Current Range 0 CUR = 0 −> 8 0 8 15 22 31 CUR[4:0] Current Range 1 CUR = 9 −> 15 Figure 12. Programmable Peak−Current Overview Speed and Load−Angle Output The SLA−pin provides an output voltage that indicates the level of the Back−e.m.f. voltage of the motor. This Back−e.m.f. voltage is sampled during every so−called “coil current zero crossings”. Per coil, 2 zero−current positions http://onsemi.com 16 AMIS−30522, NCV70522 exist per electrical period, yielding in total 4 zero−current observation points per electrical period. ICOIL VBEMF t ZOOM Previous Micro−Step ICOIL Coil Current Zero Crossing Current Decay Zero Current t VCOIL VBB Next Micro−Step Voltage Transient |VBEMF| t Figure 13. Principle of Bemf Measurement Because of the relatively high re−circulation currents in the coil during current decay, the coil voltage VCOIL shows a transient behavior. As this transient is not always desired in application software, two operating modes can be selected by means of the bit (see “SLA−transparency” in Table 12). The SLA pin shows in “transparent mode” full visibility of the voltage transient behavior. This allows a sanity−check of the speed−setting versus motor operation and characteristics and supply voltage levels. If the bit “SLAT” is cleared, then only the voltage samples at the end of each coil current zero crossing are visible on the SLA−pin. Because the transient behavior of the coil voltage is not visible anymore, this mode generates smoother Back e.m.f. input for post−processing, e.g. by software. In order to bring the sampled Back e.m.f. to a descent output level (0 V to 5 V), the sampled coil voltage VCOIL is divided by 2 or by 4. This divider is set through a SPI bit . (See Table 12) The following drawing illustrates the operation of the SLA−pin and the transparency−bit. “PWMsh” and “Icoil=0” are internal signals that define together with SLAT the sampling and hold moments of the coil voltage. http://onsemi.com 17 AMIS−30522, NCV70522 VCOIL div2 div4 Ssh Sh buf Csh Ch SLA−Pin Icoil=0 PWMsh SLAT NOT (Icoil=0) PWMsh Icoil=0 SLAT VCOIL t SLA−Pin last sample is retained VBEMF previous output is kept at SLA pin retain last sample t SLAT = 1 => SLA−pin is “transparent” during VBEMF sampling @ Coil Current Zero Crossing. SLA−pin is updated “real−time”. SLAT = 0 => SLA−pin is not “transparent” during VBEMF sampling @ Coil Current Zero Crossing. SLA−pin is updated when leaving current−less state. Figure 14. Timing Diagram of SLA−Pin Warning, Error Detection and Diagnostics Feedback Thermal Warning and Shutdown When Junction temperature rises above TTW, the thermal warning bit is set (Table 16 SPI Status Register 0). If junction temperature increases above thermal shutdown level, then the circuit goes in “Thermal Shutdown” mode () and all driver transistors are disabled (high impedance) (Table 16 SPI Status Register 2). The conditions to reset flag is to be at a temperature lower than TTW and to clear the flag by reading it using any SPI read command. Overcurrent Detection Note: Successive reading the SPI Status Registers 1 and 2 in case of a short circuit condition, may lead to damage to the drivers. Open Coil Detection The overcurrent detection circuit monitors the load current in each activated output stage. If the load current exceeds the overcurrent detection threshold, then the overcurrent flag is set and the drivers are switched off to reduce the power dissipation and to protect the integrated circuit. Each driver transistor has an individual detection bit in the Table 16 SPI Status Registers 1 and SPI Status Register 2 ( and ). Error condition is latched and the microcontroller needs to clear the status bits to reactivate the drivers. Open coil detection is based on the observation of 100% duty cycle of the PWM regulator. If in a coil 100% duty cycle is detected for longer than 32 ms the appropriate status bit in the SPI status register is set ( or ). (Table 16: SPI Status Register 0). When the resistance of a motor coil is very large and the battery voltage is low, it can happen that the motor driver is not able to deliver the requested current to the motor. Under these conditions the PWM controller duty cycle will be 100% and after 32 ms, the error pin and , will flag this situation (motor current is kept alive). This feature can be used to test if the operating conditions (supply voltage, motor coil resistance) still allow reaching the requested coil−current or else the coil−current should be reduced. http://onsemi.com 18 AMIS−30522, NCV70522 Charge Pump Failure Logic Supply Regulator The charge pump is an important circuit that guarantees low RDS(on) for all drivers, especially for low supply voltages. If the supply voltage is too low or external components are not properly connected to guarantee RDS(on) of the drivers, then the bit is set in the SPI Status Register 0. Also after power−on−reset the charge pump voltage will need some time to exceed the required threshold. During that time will be set to “1”. Error Output The 522 has an on−chip 5 V low−drop regulator with external capacitor to supply the digital part of the chip, some low−voltage analog blocks and external circuitry. The voltage level is derived from an internal bandgap reference. To calculate the available drive−current for external circuitry, the specified Iload should be reduced with the consumption of internal circuitry (unloaded outputs) and the loads connected to logic outputs. See Table 5. Power−On Reset (POR) Function This is an open drain digital output to flag a problem to the external microcontroller. The signal on this output is active low and the logic combination of: NOT(ERR) = OR OR OR OR OR VBB The open drain output pin POR/WD provides an “active low” reset for external purposes. At powerup of AMIS−30522/NCV70522, this pin will be kept low for some time to reset for example an external microcontroller. A small analog filter avoids resetting due to spikes or noise on the VDD supply. t VDD VDDH VDDL < tRF tPU tPD t POR/WD pin tPOR tRF Figure 15. Power−on−Reset Timing Diagram Watchdog Function The watchdog function is enabled/disabled through bit (Table 13). Once this bit has been set to “1” (watchdog enable), the microcontroller needs to re−write this bit to clear an internal timer before the watchdog timeout interval expires. In case the timer is activated and WDEN is acknowledged too early (before tWDPR) or not within the interval (after tWDTO), then a reset of the microcontroller will occur through POR/WD pin. In addition, a warm/cold boot bit is available in Table 16 for further processing when the external microcontroller is alive again. http://onsemi.com 19 AMIS−30522, NCV70522 VBB t VDD VDDH t tPOR POR/WD pin tDSPI Enable WD > tWDPR and < tWDTO Acknowledge WD t tWDTO = tWDPR or = tWDTO tWDRD tPOR tPU WD timer t Figure 16. Watchdog Timing Diagram Note: tDSPI is the time needed by the external microcontroller to shift−in the bit after a power−up. The duration of the watchdog timeout interval is programmable through the WDT[3:0] bits. The timing is given in Figure 16. CLR Pin (=Hard Reset) Sleep Mode Logic 0 on CLR pin allows normal operation of the chip. To reset the complete digital inside the 522, the input CLR needs to be pulled to logic 1 during minimum time given by tCLR. (See AC Parameters) This reset function clears all internal registers without the need of a power−cycle, except in sleep mode. The operation of all analog circuits is depending on the reset state of the digital, charge pump remains active. Logic 0 on CLR pin resumes normal operation again. The voltage regulator remains functional during and after the reset and the POR/WD pin is not activated. Watchdog function is reset completely. The bit in SPI Control Register 2 is provided to enter a so−called “sleep mode”. This mode allows reduction of current−consumption when the motor is not in operation. The effect of sleep mode is as follows: • The drivers are put in HiZ • All analog circuits are disabled and in low−power mode • All internal registers are maintaining their logic content • NXT and DIR inputs are ignored • SPI communication remains possible (slight current increase during SPI communication) • Oscillator and digital clocks are silent, except during SPI communication Normal operation is resumed after writing logic ‘0’ to bit . A start−up time is needed for the charge pump to stabilize. After this time, NXT commands can be issued. When the device is in sleep mode and VBB becomes lower than VBB_min the device might reset. http://onsemi.com 20 AMIS−30522, NCV70522 SPI INTERFACE The serial peripheral interface (SPI) allows an external microcontroller (Master) to communicate with the 522. The implemented SPI block is designed to interface directly with numerous micro−controllers from several manufacturers. The 522 acts always as a Slave and cannot initiate any transmission. The operation of the device is configured and controlled by means of SPI registers which are observable for read and/or write from the Master. SPI Transfer Format and Pin Signals During a SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (CLK) synchronizes shifting and sampling of the information on the two serial data lines (DO and DI). #CLK Cycle CS 1 2 3 4 5 DO signal is the output from the Slave (522), and DI signal is the output from the Master. A chip select line (CS) allows individual selection of a Slave SPI device in a multiple− slave system. The CS line is active low. If the 522 is not selected, DO is pulled up with the external pullup resistor. Since 522 operates as a Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock. The Master SPI port must be configured in MODE 0 too, to match this operation. The SPI clock idles low between the transferred bytes. The diagram below is both a Master and a Slave timing diagram since CLK, DO and DI pins are directly connected between the Master and the Slave. 6 7 8 CLK DI MSB 6 5 4 3 2 1 LSB DO MSB 6 5 4 3 2 1 LSB Figure 17. Timing Diagram of a SPI Transfer NOTE: At the falling edge of the eighth clock pulse the data−out shift register is updated with the content of the addressed internal SPI register. The internal SPI registers are updated at the first rising edge of the 522 system clock when CS = High. Transfer Packet Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more bytes. BYTE 1 Command and SPI Register Address MSB LSB MSB D7 D6 D5 D4 D3 D2 D1 BYTE 2 Data LSB D0 CMD2 CMD1 CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 Command SPI Register Address Figure 18. SPI Transfer Packet Byte 1 contains the Command and the SPI Register Address and indicates to the 522 the chosen type of operation and addressed register. Byte 2 contains data, or sent from the Master in a WRITE operation, or received from the 522 in a READ operation. Two command types can be distinguished in the communication between Master and 522: • READ from SPI Register with address ADDR[4:0]: CMD[2:0] = “000” • WRITE to SPI Register with address ADDR[4:0]: CMD[2:0] = “100” http://onsemi.com 21 ÌÌÌ ÌÌÌ ÌÌÌÌ ÌÌÌÌ AMIS−30522, NCV70522 READ Operation If the Master wants to read data from Status or Control Registers, it initiates the communication by sending a READ command. This READ command contains the address of the SPI register to be read out. At the falling edge of the eighth clock pulse the data−out shift register is updated with the content of the corresponding internal SPI register. In the next 8−bit clock pulse train this data is shifted out via DO pin. At the same time the data shifted in from DI (Master) should be interpreted as the following successive command or dummy data. Registers are updated with the internal status at the rising edge of the internal AMIS−30522/NCV70522 clock when CS = 1 CS COMMAND DI DATA from previous command or NOT VALID after POR or RESET DO READ DATA from ADDR1 DATA OLD DATA or NOT VALID COMMAND or DUMMY DATA DATA from ADDR1 Figure 19. Single READ Operation where DATA from SPI Register with Address 1 is Read by the Master All 4 Status Registers (see SPI Registers) contain 7 data bits and an even parity check bit. The most significant bit (D7) represents a parity of D[6:0]. If the number of logical ones in D[6:0] is odd, the parity bit D7 equals “1”. If the number of logical ones in D[6:0] is even then the parity bit D7 equals “0”. This simple mechanism protects against noise and increases the consistency of the transmitted data. If a parity check error occurs it is recommended to initiate an additional READ command to obtain the status again. Also the Control Registers can be read out following the same routine. Control Registers don’t have a parity check. The CS line is active low and may remain low between successive READ commands as illustrated in Figure 21. There is however one exception. In case an error condition is latched in one of Status Registers (see SPI Registers) the ERR pin is activated. (See the “Error Output” Section). This signal flags a problem to the external microcontroller. By reading the Status Registers information, the root cause of the problem can be determined. After this READ operation the Status Registers are cleared. Because the Status Registers and ERR pin (see SPI Registers) are only updated by the internal system clock when the CS line is high, the Master should force CS high immediately after the READ operation. For the same reason it is recommended to keep the CS line high always when the SPI bus is idle. WRITE Operation If the Master wants to write data to a Control Register it initiates the communication by sending a WRITE command. This contains the address of the SPI register to write to. The command is followed with a data byte. This incoming data will be stored in the corresponding Control Register after CS goes from low to high! AMIS−30522/ NCV70522 responds on every incoming byte by shifting out via DO the data stored in the last received address. It is important that the writing action (command − address and data) to the Control Register is exactly 16 bits long. If more or less bits are transmitted the complete transfer packet is ignored. A WRITE command executed for a read−only register (e.g. Status Registers) will not affect the addressed register and the device operation. Because after a power−on−reset the initial address is unknown the data shifted out via DO is not valid. The NEW DATA is written into the corresponding internal register at the rising edge of CS CS COMMAND DI DATA from previous command or NOT VALID after POR or RESET DO WRITE DATA to ADDR3 DATA NEW DATA for ADDR3 DATA OLD DATA or NOT VALID DATA OLD DATA from ADDR3 Figure 20. Single WRITE Operation where DATA from the Master is Written in SPI Register with Address 3 http://onsemi.com 22 AMIS−30522, NCV70522 Examples of Combined READ and WRITE Operations In the following examples successive READ and WRITE operations are combined. In Figure 21 the Master first reads the status from Register at ADDR4 and at ADDR5 followed Registers are updated with the internal status at the rising edge of the internal 522 clock when CS = 1 CS DI DATA from previous command or NOT VALID after POR or RESET DO COMMAND READ DATA from ADDR4 DATA OLD DATA or NOT VALID COMMAND READ DATA from ADDR5 DATA DATA from ADDR4 by writing a control byte in Control Register at ADDR2. Note that during the write command (in Figures 20 and 21) the old data of the pointed register is returned at the moment the new data is shifted in. The NEW DATA is written into the corresponding internal register at the rising edge of CS COMMAND WRITE DATA to ADDR2 DATA DATA from ADDR5 DATA NEW DATA for ADDR2 DATA OLD DATA from ADDR2 Figure 21. Two Successive READ Commands Followed by a WRITE Command After the write operation the Master could initiate a read back command in order to verify if the data is correctly written, as illustrated in Figure 22. During reception of the READ command the old data is returned for a second time. Only after receiving the READ command the new data is Registers are Updated with the Internal Status at the Rising Edge of CS CS COMMAND DI DATA from previous command or NOT VALID after POR or RESET DO WRITE DATA to ADDR2 DATA OLD DATA or NOT VALID DATA transmitted. This rule also applies when the master device wants to initiate an SPI transfer to read the Status Registers. Because the internal system clock updates the Status Registers only when CS line is high, the first read out byte might represent old status information. Registers are Updated with the Internal Status at the Rising Edge of the Internal 522 Clock when CS = 1 COMMAND READ DATA from ADDR2 DATA OLD DATA from ADDR2 COMMAND or DUMMY DATA NEW DATA from ADDR2 NEW DATA for ADDR2 DATA OLD DATA from ADDR2 Figure 22. A WRITE Operation where DATA from the Master is Written in SPI Register with Address 2 Followed by a READ Back Operation to Verify a Correct WRITE Operation NOTE: The internal data−out shift buffer of the AMIS−30522/NCV70522 is updated with the content of the selected SPI register only at the last (every eighth) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data. Table 11. SPI CONTROL REGISTERS (All SPI Control Registers have Read/Write Access and default to “0” after Power−on or hard reset) Structure Content Access Address CRWD (00h) CR0 (01h) CR1 (02h) CR2 (03h) Reset Data Data Data Data DIRCTRL MOTEN Bit 7 R/W 0 WDEN SM[2:0] NXTP SLP − SLAG − SLAT PWMF − Bit 6 R/W 0 Bit 5 R/W 0 Bit 4 R/W 0 WDT[3:0] Bit 3 R/W 0 Bit 2 R/W 0 0 CUR[4:0] PWMJ − EMC[1:0] − − Bit 1 R/W 0 0 Bit 0 R/W 0 0 Where: R/W: Reset: WDEN: WDT[3:0]: Read and Write access Status after Power−On or hard reset Watchdog enable. Writing “0” to this bit will clear WD bit (see SPI Status Register 0) Watchdog timeout interval http://onsemi.com 23 AMIS−30522, NCV70522 Table 12. SPI CONTROL PARAMETER OVERVIEW Symbol WDEN Description Watchdog enable. = 1 = 0 = 0 Status Value Writing “1” to this bit will enable the watchdog timer (if not enabled yet) or will clear this timer (if already enabled) Writing “0” to this bit will disable the Watchdog = 0 = 1 = 0 = 1 Very Fast Fast Slow Very Slow Drivers Disabled Drivers Enabled Trigger on Rising Edge Trigger on Falling Edge Default Frequency Double Frequency Jitter Disabled Jitter Enabled 1/32 1/16 1/8 1/4 1/2 1/2 Full Step n.a. Gain = 0.5 Gain = 0.25 SLA is NOT Transparent SLA is Transparent Active Mode Sleep Mode Micro Step Micro Step Micro Step Micro Step Compensated Half Step Uncompensated Half Step CW Motion CCW Motion CCW Motion CW Motion DIRCTRL Controls the Direction of Rotation (in Combination with Logic Level on Input DIR) = 1 00 EMC[1:0] Turn On− and Turn−off Slopes (Note 15) 01 10 11 MOTEN Activates the Motor Driver Outputs Selects if NXT triggers on Rising or Falling Edge Enables Doubling of the PWM Frequency (Note 15) Enables Jitter PWM = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 000 001 010 NXTP PWMF PWMJ SM[2:0] Stepmode 011 100 101 110 111 SLAG Speed Load Angle Gain Setting Speed Load Angle Transparency Bit Enables Sleep Mode = 0 = 1 = 0 = 1 = 0 = 1 SLAT SLP 15. The typical values can be found in Table 5: DC Parameters and Table 6: AC Parameters http://onsemi.com 24 AMIS−30522, NCV70522 WDT[3:0] Selects the watchdog timeout interval. Table 13. WATCHDOG TIMEOUT INTERVAL AS FUNCTION OF WDT[3:0] Index 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 WDT[3:0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 tWDTO (ms) 32 64 96 128 160 192 224 256 Index 8 9 A B C D E F 1 1 1 1 1 1 1 1 WDT[3:0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 tWDTO (ms) 288 320 352 384 416 448 480 512 CUR[4:0] Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils. Table 14. SPI CONTROL PARAMETER OVERVIEW: CURRENT AMPLITUDE CUR[4:0] Current Range (Note 17) Index CUR[4:0] 0 00000 1 00001 2 00010 3 00011 0 4 00100 5 00101 6 00110 7 00111 8 01000 9 01001 10 01010 11 01011 1 12 01100 13 01101 14 01110 15 01111 Current (mA) (Note 16) 33 64 95 104 115 126 138 153 166 190 205 230 250 275 300 325 3 2 Current Range (Note 17) Index CUR[4:0] 16 10000 17 10001 18 10010 19 10011 20 10100 21 10101 22 10110 23 10111 24 11000 25 11001 26 11010 27 11011 28 11100 29 11101 30 11110 31 11111 Current (mA) (Note 16) 365 400 440 485 530 585 630 750 825 895 975 1065 1155 1245 1365 1480 16. Typical current amplitude at TJ = 125°C. 17. Reducing the current over different current ranges might trigger overcurrent detection, please refer to dedicated application note for solutions. SPI Status Register Description All 4 SPI Status Registers have Read Access and are default to “0” after Power−on or hard reset. Table 15. SPI STATUS REGISTERS Structure Content Access Address SR0 04h SR1 05h SR2 06h SR3 07h Reset Data Not Latched Data is Latched Data is Latched Data Not Latched Bit 7 R 0 PAR PAR PAR PAR Bit 6 R 0 TW OVCXPT OVCYPT Bit 5 R 0 CPfail OVCXPB OVCYPB Bit 4 R 0 WD OVCXNT OVCYYNT Bit 3 R 0 OPENX OVCXNB OVCYNB Bit 2 R 0 OPENY − TSD Bit 1 R 0 − − − Bit 0 R 0 − − − MSP[6:0] Where: R: Read only mode access Reset: PAR: http://onsemi.com 25 Status after Power−On or hard reset Parity check AMIS−30522, NCV70522 Table 16. SPI STATUS FLAGS OVERVIEW Mnemonic CPFail Flag Charge Pump Failure Length (bit) 1 Related SPI Register Status Register 0 Comment ‘0’ = no failure ‘1’ = failure: indicates that the charge pump does not reach the required voltage level. This bit indicates the watchdog timer has not been cleared properly in time. If the master reads that WD is set to “1” after reset, it means that a watchdog reset occurred (warm boot) instead of power−on−reset (cold boot). WD bit will be cleared only when the master writes “0” to WDEN bit. Translator micro step position ‘1’ = Open coil detected ‘1’ = Open coil detected ‘0’ = no failure ‘1’ = failure: indicates that overcurrent is detected at bottom transistor XN−terminal ‘0’ = no failure ‘1’ = failure: indicates that overcurrent is detected at top transistor XN−terminal ‘0’ = no failure ‘1’ = failure: indicates that overcurrent is detected at bottom transistor XP−terminal ‘0’ = no failure ‘1’ = failure: indicates that overcurrent is detected at top transistor XP−terminal ‘0’ = no failure ‘1’ = failure: indicates that overcurrent is detected at bottom transistor YN−terminal ‘0’ = no failure ‘1’ = failure: indicates that overcurrent is detected at top transistor YN−terminal ‘0’ = no failure ‘1’ = failure: indicates that overcurrent is detected at bottom transistor YP−terminal ‘0’ = no failure ‘1’ = failure: indicates that overcurrent is detected at top transistor YP−terminal Reset State ‘0’ WD Watchdog event 1 Status Register 0 ‘0’ MSP[6:0] OPENX OPENY OVCXNB Micro Step Position OPEN Coil X OPEN Coil Y Overcurrent at MOTXN Terminal; Bottom Transistor Overcurrent at MOTXN Terminal; Top Transistor Overcurrent at MOTXP Terminal; Bottom Transistor Overcurrent at MOTXP Terminal; Top Transistor Overcurrent at MOTYN Terminal; Bottom Transistor Overcurrent at MOTYN Terminal; Top Transistor Overcurrent at MOTYP Terminal; Bottom Transistor Overcurrent at MOTYP Terminal; Top Transistor Thermal Shutdown Thermal Warning Watchdog event 7 1 1 1 Status Register 3 Status Register 0 Status Register 0 Status Register 1 ‘0000000’ ‘0’ ‘0’ ‘0’ OVCXNT 1 Status Register 1 ‘0’ OVCXPB 1 Status Register 1 ‘0’ OVCXPT 1 Status Register 1 ‘0’ OVCYNB 1 Status Register 2 ‘0’ OVCYNT 1 Status Register 2 ‘0’ OVCYPB 1 Status Register 2 ‘0’ OVCYPT TSD TW WD 1 1 1 1 Status Register 2 Status Register 2 Status Register 0 Status Register 0 ‘0’ ‘0’ ‘0’ ‘0’ = no watchdog reset ‘1’ = watchdog reset occurred ‘0’ http://onsemi.com 26 AMIS−30522, NCV70522 DEVICE ORDERING INFORMATION Part Number AMIS30522C5222RG AMIS30522C5222G NCV70522MN003R2G* NCV70522MN003G* Ambient Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Type NQFP−32 (Pb−Free) NQFP−32 (Pb−Free) NQFP−32 (Pb−Free) NQFP−32 (Pb−Free) Peak Current 1500 mA 1500 mA 1500 mA 1500 mA Shipping† Tape & Reel Tube / Tray Tape & Reel Tube / Tray †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *Qualified for automotive applications. http://onsemi.com 27 AMIS−30522, NCV70522 PACKAGE DIMENSIONS NQFP−32, 7x7 CASE 560AA−01 ISSUE O http://onsemi.com 28 AMIS−30522, NCV70522 NQFP−32, 7x7 CASE 560AA−01 ISSUE O ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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