NCV7380_07

NCV7380 LIN Transceiver The NCV7380 is a physical layer device for a single wire data link capable of operating in applications where high data rate is not required and a lower data rate can achieve cost reductions in both the physical media components and in the microprocessor which uses the network. The NCV7380 is designed to work in systems developed for LIN 1.3 or LIN 2.0. The IC furthermore can be used in ISO9141 systems. Because of the very low current consumption of the NCV7380 in recessive state, it’s suitable for ECU applications with low standby current requirements, whereby no sleep/wakeup control from the microprocessor is necessary. Features http://onsemi.com MARKING DIAGRAM 8 8 1 SO−8 D SUFFIX CASE 751 1 V7380 A L Y W G V7380 ALYW G • Operating Voltage VS = 7.0 to 18 V • Low Current Consumption of Typ. 24 mA • LIN−Bus Transceiver: ♦ ♦ ♦ • • • • • • • • • Slew Rate Control for Good EMC Behavior Fully Integrated Receiver Filter BUS Input Voltage −27 V to 40 V ♦ Integrated Termination Resistor for LIN Slave Nodes (30 kW) ♦ Baud Rate up to 20 kBaud ♦ Will Work in Systems Designed for either LIN 1.3 or LIN 2.0 Compatible to ISO9141 Functions High EMI Immunity Bus Terminals Protect Against Short−Circuits and Transients in the Automotive Environment Bus Pin High Impedance During Loss of Ground and Undervoltage Conditions Thermal Overload Protection High Signal Symmetry for use in RC–Based Slave Nodes up to 2% Clock Tolerance when Compared to the Master Node "1000 V ESD Protection, Charged Device Model NCV Prefix for Automotive and Other Applications Requiring Site and Change Control Pb−Free Packages are Available = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS RxD 1 NC 2 VCC 3 TxD 4 (Top View) 8 7 6 5 NC VS BUS GND ORDERING INFORMATION Device NCV7380D NCV7380DG NCV7380DR2 NCV7380DR2G Package SO−8 SO−8 (Pb−Free) SO−8 SO−8 (Pb−Free) Shipping† 95 Units/Rail 95 Units/Rail 2500 Tape & Reel 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2007 February, 2007 − Rev. 2 1 Publication Order Number: NCV7380/D NCV7380 NCV7380 VS Internal Supply and References Biasing & Bandgap Thermal Shutdown VCC POR 30 K 15 K SLEW RATE CONTROL BUS Driver BUS TxD GND RxD Receive Comparator Input Filter Figure 1. Block Diagram PACKAGE PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 Symbol RXD NC VCC TXD GND BUS VS NC Description Receive data from BUS to microprocessor, LOW in dominant state. No connection. 5.0 V supply input. Transmit data from microprocessor to BUS, LOW in dominant state. Ground. LIN bus pin, LOW in dominant state. Battery input voltage. No connection. http://onsemi.com 2 NCV7380 Electrical Specification All voltages are referenced to ground (GND). Positive currents flow into the IC. The maximum ratings given in the table below are limiting values that do not lead to a permanent damage of OPERATING CONDITIONS Characteristic Battery Supply Voltage (Note 1) Supply Voltage Operating Ambient Temperature Symbol VS VCC TA Min 7.0 4.5 −40 Max 18 5.5 +125 Unit V V °C the device but exceeding any of these limits may do so. Long term exposure to limiting values may effect the reliability of the device. MAXIMUM RATINGS Rating Battery Supply Voltage Symbol VS VCC VS.tr1 VS..tr2 VS..tr3 VBUS VBUS..tr1 VBUS.tr2 VBUS.tr3 VDC VESDCDM VESDHBM ILATCH Ptot qJA Tstg TJ t < 1 min Load Dump, t < 500 ms Supply Voltage Transient Supply Voltage Transient Supply Voltage Transient Supply Voltage BUS Voltage − ISO 7637/1 Pulse 1 (Note 2) ISO 7637/1 Pulses 2 (Note 2) ISO 7637/1 Pulses 3A, 3B t < 500 ms , Vs = 18 V t < 500 ms ,Vs = 0 V Transient Bus Voltage Transient Bus Voltage Transient Bus Voltage DC Voltage on Pins TxD, RxD ESD Capability, Charged Device Model ESD Capability of RxD, TxD, VCC, BUS Pins ESD Capability of VS Pin Maximum Latchup Free Current at Any Pin Maximum Power Dissipation Thermal Impedance Storage Temperature Junction Temperature ISO 7637/1 Pulse 1 (Note 3) ISO 7637/1 Pulses 2 (Note 3) ISO 7637/1 Pulses 3A, 3B (Note 3) − (Note 4) Human body model, equivalent to discharge 100 pF with 1.5 kW (Note 4) − At TA = 125°C In Free Air − − Condition Min −0.3 −0.3 −150 − −150 −27 −40 −150 − −150 −0.3 −1.0 −2.0 −1.5 −500 − − −55 −40 Max 30 40 +7.0 − 100 150 40 − 100 150 7.0 1.0 2.0 1.5 500 197 152 +150 +150 V V V V V Unit V V V V V kV kV kV mA mW °C/W °C °C LEAD TEMPERATURE SOLDERING REFLOW Lead Free, 60 sec −150 sec above 217, 40 sec Max at Peak Leaded, 60 sec −150 sec above 183, 30 sec Max at Peak TSLD TSLD − − 265 Peak 240 Peak °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. VS is the IC supply voltage including voltage drop of reverse battery protection diode, VDROP = 0.4 to 1.0 V, VBAT_ECU voltage range is 7.0 to 18 V. 2. ISO 7637 test pulses are applied to VS via a reverse polarity diode and > 2.0 mF blocking capacitor. 3. ISO 7637 test pulses are applied to BUS via a coupling capacitance of 1.0 nF. 4. This device incorporates ESD protection and is tested by the following methods: ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A 114C) ESD CDM tested per EIA/JESD22−C 101C, Field Induced Model. http://onsemi.com 3 NCV7380 ELECTRICAL CHARACTERISTICS (VS = 7.0 to 18 V, VCC = 4.5 to 5.5 V and TA = −40 to 125°C unless otherwise noted.) Characteristic GENERAL VCC Undervoltage Lockout Supply Current, Dominant Supply Current, Dominant Supply Current, Recessive Supply Current, Recessive Supply Current, Recessive Thermal Shutdown Thermal Recovery BUS − Transmit Short Circuit Bus Current Pullup Current Bus Bus Reverse Current, Recessive Bus Reverse Current Loss of Battery Bus Current During Loss of Ground Transmitter Dominant Voltage Transmitter Dominant Voltage Bus Input Capacitance BUS − Receive Receiver Dominant Voltage Receiver Recessive Voltage Center Point of Receiver Threshold Receiver Hysteresis VBUSdom (Notes 6 and 7) VBUSrec (Notes 6 and 7) VBUS_CNT (Notes 6 and 7) VHYS (Notes 6 and 7) − − VBUS_CNT = (VBUSdom and VBUSrec)/2 VBUS_CNTt = (VBUSrec−VBUSdom) 0.4*VS − 0.487 *VS − − − 0.5*VS 0.16*VS − 0.6*VS 0.512*VS − V V V V IBUS_LIM (Notes 6 and 7) IBUS_PU (Notes 6 and 7) IBUS_PAS_rec (Notes 6 and 7) IBUS (Notes 6 and 7) IBUS_NO_GND (Notes 6 and 7) VBUSdom_DRV_2 (Note 6) VBUSdom_DRV_3 (Note 6) CBUS (Note 5) VBUS = VS, Driver On VBUS = 0, VS = 12 V, Driver Off VBUS > VS, 8.0 V < VBUS < 18 V, 7.0 V < VS < 18 V , Driver Off VS = 0 V, 0 V < VBUS < 18 V VS = 12 V, 0 < VBUS < 18 V VS = 7.0 V, Load = 500 W VS = 18 V, Load = 500 W Pulse Response via 10 kW, VPULSE = 12 V, VS = Open − −600 − − −1.0 − − − 120 − − − − − − 25 200 −200 5.0 5.0 1.0 1.2 2.0 35 mA mA mA mA mA V V pF VCC_UV ISd ICCd ISr ICCr ISr + ICCr Tsd (Note 5) Thys (Note 5) VS > 6.0 V, TxD = L, EN = H VS = 18 V, VCC = 5.5 V, TxD = L VS = 18 V, VCC = 5.5 V, TxD = L VS = 18 V, VCC = 5.5 V, TxD = Open VS = 18 V, VCC = 5.5 V, TxD = Open VS = 12 V, VCC = 5.0 V, TxD = Open, TA = 25° − − 2.75 − − − − − 155 126 − 1.0 0.8 10 14 24 − 140 4.3 3.0 1.5 20 30 − 180 150 V mA mA mA mA mA °C °C Symbol Condition Min Typ Max Unit 5. No production test, guaranteed by design and qualification. 6. In accordance to LIN physical layer specification 1.3. 7. In accordance to LIN physical layer specification 2.0. http://onsemi.com 4 NCV7380 ELECTRICAL CHARACTERISTICS (continued) (VS = 7.0 to 18 V, VCC = 4.5 to 5.5 V and TA = −40 to 125°C unless otherwise noted.) Characteristic TXD High Level Input Voltage Low Level Input Voltage TxD Pullup Resistor RXD Low Level Output Voltage Leakage Current AC CHARACTERISTICS Propagation Delay Transmitter (Notes 10 and 12) Propagation Delay Transmitter Symmetry (Notes 8 and 12) Propagation Delay Receiver (Notes 8, 9, 10, 12 and 15) Propagation Delay Receiver Symmetry (Notes 8 and 9) Slew Rate Rising and Falling Edge, High Battery (Notes 8 and 13) Slew Rate Rising and Falling Edge, Low Battery (Notes 8 and 13) Slope Symmetry, High Battery (Notes 8 and 13) Bus Duty Cycle (Notes 9 and 16) Receiver Debounce Time (Notes 11, 14 and 15) ttrans_pdf ttrans_pdr ttrans_sym trec_pdf trec_pdr trec_sym tSR_HB Bus Loads: 1.0 KW/1.0 nF, 660 W/6.8 nF, 500 W/10 nF Calculate ttrans_pdf − ttrans_pdr CRxD = 20 pF Calculate ttrans_pdf − ttrans_pdr Bus Loads: VS = 18 V, 1.0 KW/1.0 nF, 660 W/6.8 nF, 500 W/10 nF Bus Loads: VS = 7.0 V, 1.0 KW/1.0 nF, 660 W/6.8 nF, 500 W/10 nF Bus Loads: VS = 18 V, 1.0 KW/1.0 nF, 660 W/6.8 nF, 500 W/10 nF, Calculate tsdom−tsrec Calculate tBUS_rec(min)/100 ms Calculate tBUS_rec(max)/100 ms BUS Rising and Falling Edge − −2.0 − −2.0 1.0 − − − − 2.0 5.0 2.0 6.0 2.0 3.0 ms ms ms ms V/ms Vol_rxd Vleak_rxd IRxD = 2.0 mA VRxD = 5.5 V, Recessive − −10 − − 0.9 10 V mA Vih Vil RIH_TXD Rising Edge Falling Edge VTxD = 0 V − 0.3*VCC 10 − − 15 0.7*VCC − 25 V V kW Symbol Condition Min Typ Max Unit tSR_LB 0.5 2.0 3.0 V/ms tssym_HB −5.0 − 5.0 ms D1 D2 trec_deb 0.396 − 1.5 − − − − 0.581 4.0 ms/ms ms/ms ms 8. In accordance to LIN physical layer specification 1.3. 9. In accordance to LIN physical layer specification 2.0. 10. Propagation delays are not relevant for LIN protocol transmission, only symmetry. 11. No production test, guaranteed by design and qualification. 12. See Figure 2 − Input/Output Timing. 13. See Figure 7 − Slope Time Calculation. 14. See Figure 3 − Receiver Debouncing. 15. This parameter is tested by applying a square wave to the bus. The minimum slew rate for the bus rising and falling edges is 50 V/ms. 16. See Figure 8 − Duty Cycle Measurement and Calculation. http://onsemi.com 5 NCV7380 TIMING DIAGRAMS TxD 50% ttrans_pdf VBUS 95% 100% ttrans_pdr BUS 50% 50% 5% 0% trec_pdf RxD 50% trec_pdr Figure 2. Input/Output Timing t < trec_deb VBUS t < trec_deb 60% 40% t VRxD 50% t Figure 3. Receiver Debouncing Filter http://onsemi.com 6 NCV7380 TEST CIRCUITS FOR DYNAMIC AND STATIC CHARACTERISTICS NCV7380 VSUP RL 100 nF VCC 100 nF BUS CL TxD 2.7 K RxD GND 20 pF Figure 4. Test Circuit for Dynamic Characteristics NCV7380 2 mF + VSUP VCC 100 nF 500 BUS 1 nF TxD GND RxD Oscilloscope Schaffner− Generator Puls3a,3b 12 V + − Puls1,2,4 Figure 5. Test Circuit for Automotive Transients http://onsemi.com 7 NCV7380 Functional Description Initialization BUS Input/Output After power on, the chip automatically enters the recessive state (TxD = Open). Both VCC and VS must be present. Operating Modes All operation modes will be handled from the NCV7380 automatically. Normal Mode The recessive BUS level is generated from the integrated 30 k pullup resistor in series with a diode. The diode prevents reverse current on VBUS when VBUS > VS. No additional termination resistor is necessary to use the NCV7380 on LIN slave nodes. If this IC is used for LIN master nodes, it is necessary to terminate the bus with an external 1.0 kW resistor in series with a diode to VBAT (Figure 9). TxD Input After power on, the IC switches automatically to normal mode. Bus communication is possible. If there is no communication on the bus line the power consumption of the IC is very low and does not require microprocessor control. Thermal Shutdown Mode If the junction temperature TJ is higher than 155°C, the NCV7380 could be switched into the thermal shutdown mode (bus driver will be switched off, receiver is on). If TJ falls below the thermal shutdown temperature (typical 140°C) the NCV7380 will be switched to the normal mode. LIN BUS Transceiver During transmission the signal on TxD will be transferred to the BUS driver for generating a BUS signal. To minimize the electromagnetic emission of the bus line, the BUS driver has integrated slew rate control and wave shaping. Transmitting will be interrupted if thermal shutdown is active. The CMOS compatible input TxD directly controls the BUS level: TxD = low → BUS = low (dominant level) TxD = high → BUS = high (recessive level) The TxD pin has an internal pullup resistor connected to VCC. This secures that an open TxD pin generates a recessive BUS level. RxD Output The transceiver consists of a bus−driver (1.2 V @ 40 mA) with slew rate control and current limit, and a receiver with a high voltage comparator with filter circuitry. The signal on the BUS pin will be transferred continuously to the RxD pin. Short spikes on the bus signal are filtered with internal circuitry (Figure 3 and Figure 6). VS 60% BUS 50% 40% VBUS_CNT_max VhHYS VBUS_CNT_min t < trec_deb t < trec_deb RxD Figure 6. Receive Impulse Diagram http://onsemi.com 8 NCV7380 The receive threshold values VBUS_CNT_max and VBUS_CNT_min are symmetrical to 0.5*VS with a hysteresis of 0.16*VS (typ). The LIN specific receive threshold is between 0.4*VS and 0.6*VS. The received BUS signal will be output to the RxD pin: BUS < VBUS_CNT – 0.5 * VHYS → RxD = low (BUS dominant) BUS > VBUS_CNT + 0.5 * VHYS → RxD = high, floating (BUS recessive) RxD is a buffered open drain output with a typical load of: Resistance: 2.7 kW Capacitance: < 20 pF Data Rate Operating Under Disturbance Loss of Battery If VS and VCC are disconnected from the battery, the bus pin is in high impedance state. There is no impact to the bus traffic. Loss of Ground In case of an interrupted ground connection from VS and VCC, there is no influence to the bus line. Short Circuit BUS to Battery The transmitter output current is limited to 200 mA (max) in case of short circuit to battery. Short Circuit BUS to Ground The NCV7380 is a constant slew rate transceiver. The bus driver operates with a fixed slew rate range of 1.0 V/ms v DV/DT v 3.0 V/ms. This principle provides very good symmetry of the slope times between recessive to dominant and dominant to recessive slopes within the LIN bus load range (CBUS, Rterm). The NCV7380 guarantees data rates up to 20 kBit within the complete bus load range under worst case conditions. The constant slew rate principle holds appropriate voltage levels and can operate within the LIN Protocol Specification for RC oscillator systems with a matching tolerance up to 2%. Application Hints LIN System Parameter Bus Loading Requirements Parameter Operating Voltage Range Voltage Drop of Reverse Protection Diode Voltage Drop of Bus Decouple Diode in the Master Node Battery Offset Voltage Ground Offset Voltage Master Termination Resistor Slave Termination Resistor Number of System Nodes Network Distance between any two ECU Nodes Line Capacitance Capacitance of Master Node Capacitance of Slave Node Network Total Capacitance Network Total Resistance Time Constant of Overall System Negative voltages on the bus pin are limited to current through the internal 30 k resistor and series diode from VS. Thermal Overload The NCV7380 is protected against thermal overloads. If the chip temperature exceeds the thermal shutdown threshold, the transmitter is switched off until thermal recovery. The receiver continues to work during thermal shutdown. Undervoltage VCC The VCC undervoltage lockout feature disables the transmitter until it is above the undervoltage lockout threshold to prevent undesirable bus traffic. Symbol VBAT VDrop_rev VDrop_dec Vbatoff Vgoff Rpu_master Rpu_slave N BUS_length CLINE CMaster CSlave Ct1 Rt1 tnet Min 8.0 0.4 0.4 − − 900 20 2 − − − 195 1.0 537 1.0 Typ − − − − − 1000 30 − − 100 220 220 4.0 − − Max 18 1.0 1.0 0.1 0.1 1100 60 16 40 150 − 300 10 863 5.0 Unit V V V VBAT VBAT W kW − m pF/m pF pF nF W ms http://onsemi.com 9 NCV7380 Recommendations for System Design The goal of the LIN physical layer standard is to have a universal definition of the LIN system for plug and play solutions in LIN networks up to 20 kBd bus speeds. In case of small and medium LIN networks, it’s recommended to adjust the total network capacitance to at least 4.0 nF for good EMC and EMI behavior. This can be done by setting only the master node capacitance. The slave node capacitance should have a unit load of typically 220 pF for good EMC/EMI behavior. In large networks with long bus lines and the maximum number of nodes, some system parameters can exceed the defined limits and the LIN system designer must intervene. The whole capacitance of a slave node is not only the unit load capacitor itself. Additionally, there is the capacitance of wires and connectors, and the internal capacitance of the LIN transmitter. This internal capacitance is strongly dependent on the technology of the IC manufacturer and should be in the range of 30 pF to 150 pF. If the bus lines have a total length of nearly 40m, the total bus capacitance can exceed the LIN system limit of 10 nF. A second parameter of concern is the integrated slave termination resistor tolerance. If most of the slave nodes have a slave termination resistance at the allowed maximum of 60 kW, the total network resistance is more than 700 W. Even if the total network capacitance is below or equal to the maximum specified value of 10 nF, the network time constant is higher than 7.0 ms. This problem can be solved only by adjusting the master termination resistor to the required maximum network time constant of 5.0 ms (max). NOTE: The NCV7380 meets the requirements for implementation in RC−based slave nodes. The LIN Protocol Specification requires the deviation of the slave node clock to the master node clock after synchronization must not differ by more than "2%. Setting the network time constant is necessary in large networks (primarily resistance) and also in small networks (primarily capacitance). MIN/MAX SLOPE TIME CALCULATION (In accordance to the LIN System Parameter Table) VBUS 100% 60% 60% 40% 40% 0% Vdom tsdom tsrec Figure 7. Slope Time and Slew Rate Calculation (In accordance to LIN physical layer specification 1.3) The slew rate of the bus voltage is measured between 40% and 60% of the output voltage swing (linear region). The output voltage swing is the difference between dominant and recessive bus voltage. dV dt + 0.2 * Vswing (t40%−t60%) The slope time of the recessive to dominant edge is directly determined by the slew rate control of the transmitter: tslope + Vswing dV dt The slope time is the extension of the slew rate tangent until the upper and lower voltage swing limits: tslope + 5 * (t40%−t60%) The dominant to recessive edge is influenced from the network time constant and the slew rate control, because it’s a passive edge. In case of low battery voltages and high bus loads the rising edge is only determined by the network. If the rising edge slew rate exceeds the value of the dominant one, the slew rate control determines the rising edge. http://onsemi.com 10 NCV7380 tBit TxD tBit tdom(max) VSUP 100% trec(min) tdom(min) BUS 58.1% 28.4% 74.4% 42.2% 58.1% trec(max) GND 0% 28.4% RxD Figure 8. Duty Cycle Measurement and Calculation in Accordance to LIN Physical Layer Specification 2.0 Duty Cycle Calculation With the timing parameters shown in Figure 8 two duty cycles, based on trec(min) and trec(max) can be calculated as follows: D1* = trec(min)/(2 x tBit) D2* = trec(max)/(2 x tBit) For proper operation at 20 KBit/s (bit time is 50 ms) the LIN driver has to fulfill the duty cycles specified in the AC characteristics for supply voltages of 7...18 V and the three defined standard loads. Due to this simple definition there is no need to measure slew rates, slope times, transmitter delays and dominant voltage levels as specified in the LIN physical layer specification 1.3. The devices within the D1/D2 duty cycle range also operates in applications with reduced bus speed of 10.4 kBit/s or below. In order to minimize EME, the slew rates of the transmitter can be reduced (by up to [ 2 times). Such devices have to fulfill the duty cycle definition D3/D4 in the LIN physical layer specification 2.0. Devices within this duty cycle range cannot operate in higher frequency 20 kBit/s applications. *D1 and D2 are defined in the LIN protocol specification 2.0. http://onsemi.com 11 NCV7380 Car Battery Ignition VBAT 1N4001 VIN Voltage Regulator NCV8502 VOUT 10 mF 100 nF Reset 47 nF 100 nF 2.2 mF LIN BUS Slave ECU 10 k 2.7 K VCC RxD VS BUS 220 pF ECU Connector to Single Wire LIN Bus ECU Connector to Single Wire LIN Bus mP NCV7380 TxD GND GND 1N4001 VBAT VIN Voltage Regulator NCV8501 ENABLE 10 k 2.2 mF 100 nF Master ECU VOUT 10 mF 10 k Reset 47 nF 47 nF 2.7 K 100 nF VCC INH RxD VS 1K mP NCV7382* BUS TxD EN 220 pF GND GND *The NCV7382 is a pin compatible transceiver with INH control. Figure 9. Application Circuitry http://onsemi.com 12 NCV7380 ESD/EMC Remarks General Remarks ESD Test Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe ESD control procedures whenever handling semiconductor products. The NCV7380 is tested according to MIL883D (Human Body Model). EMC The test on EMC impacts is done according to ISO 7637−1 for power supply pins and ISO 7637−3 for data and signal pins. POWER SUPPLY PIN VS Test Pulse 1 2 3a/b 5 Condition t1 = 5.0 s/US = −100 V/tD = 2.0 ms t1 = 0.5 s/US = 100 V/tD = 0.05 ms US = −150 V/US = 100 V Burst 100 ns/10 ms/90 ms Break Ri = 0.5 W, tD = 400 ms tr = 0.1 ms/UP + US = 40 V Duration 5000 Pulses 5000 Pulses 1h 10 Pulses Every 1 Min DATA AND SIGNAL PINS BUS Test Pulse 1 2 3a/b Condition t1 = 5.0 s/US = −100 V/tD = 2.0 ms t1 = 0.5 s/US = 100 V/tD = 0.05 ms US = −150 V/US = 100 V Burst 100 ns/10 ms/90 ms Break Duration 1000 Pulses 1000 Pulses 1000 Burst http://onsemi.com 13 NCV7380 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH − X− A 8 5 B 1 S 4 0.25 (0.010) M Y M −Y− G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S SOLDERING FOOTPRINT* DIM A B C D G H J K M N S 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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