NCV7450DB0R2G

System Basis Chip with CAN FD, LDO Regulator and HS Driver NCV7450 The system basis chip (SBC) NCV7450 integrates +5 V / 250 mA LDO regulator with a high−speed CAN FD transceiver and one high−side driver with diagnostics, directly controlled by dedicated pins. www.onsemi.com Features • 5 V ±2% / 250 mA LDO 16 Current Limitation with Fold−back Output Voltage Monitoring One High−Speed CAN FD Transceiver ♦ Current Limitation, Reverse Current Protected ♦ Compliant to ISO11898−2:2016 ♦ CAN FD Timing Specified up to 5 Mbit/s ♦ TxDC Timeout One High−Side Driver ♦ Rdson = 300 mW @ 25°C ♦ Current Limitation ♦ Diagnostic Output ♦ Overcurrent Protection ♦ Underload Detection Direct Control Window Watchdog Two−level Thermal Shutdown Protection AEC−Q100 Qualified and PPAP Capable This Device is Pb−Free, Halogen Free/BFR Free and RoHS Compliant ♦ • • • • • • • 1 ♦ Typical Applications TSSOP16−EP CASE 948BV MARKING DIAGRAM 16 NCV 7450 ALYWG 1 NCV7450 A L Y W G PIN CONNECTIONS VR1 • Automotive • Industrial Networks = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package WD_EN RSTN TxDC HS_DIAG RxDC WDI HS_EN 1 16 2 15 3 14 4 5 6 NCV 7450 13 12 11 7 10 8 9 VS1 VS2 HS GND CANL CANH GND CAN_EN ORDERING INFORMATION Device Package NCV7450DB0R2G TSSOP16−EP (Pb−Free) Shipping† 4000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2018 November, 2019 − Rev. 1 1 Publication Order Number: NCV7450/D NCV7450 Battery connection Cbuf 100n VS1 VS2 References, oscillator VR1 VR1 4u7 5 V / 250 mA VDD RESET RSTN WD_EN Watchdog WDI HS_EN HS_DIAG High−Side MCU HS 10n VR1 Load CAN_EN CANH TxDC CAN CAN CANL RxDC NCV7450 GND GND GND Figure 1. Simplified Application Diagram www.onsemi.com 2 Termination, Protection CAN bus NCV7450 VS1 16 VR1 VS2 15 1 UV RSTN 3 Internal supply ref References LDO Regulator VR1 WD_EN WDI Thermal Monitoring Oscillator 2 Watchdog 7 OV HS_EN 8 Slope Control VR1 HS_DIAG 14 HS 5 Diagnosis Thermal Monitoring High−Side Driver CAN_EN 9 VR1 VR1 TxDC 4 11 Tx Timeout VR1 RxDC CANH CAN 12 6 10 13 GND GND Figure 2. Block Diagram www.onsemi.com 3 CANL NCV7450 VR1 WD_EN RSTN TxDC HS_DIAG RxDC WDI HS_EN 1 16 2 15 3 14 4 5 6 NCV 7450 13 12 11 7 10 8 9 VS1 VS2 HS GND CANL CANH GND CAN_EN Table 1. PIN DESCRIPTION Pin No. Pin Name Pin Type (LV = Low Voltage; HV = High Voltage) 1 VR1 LV supply output 2 WD_EN LV digital input; internal pull−up current 3 RSTN LV digital output; open drain; internal pull−up 4 TxDC LV digital input; internal pull−up 5 HS_DIAG LV digital output; push−pull HS driver diagnostic output (active Low) 6 RxDC LV digital output; push−pull CAN receiver data output 7 WDI LV digital input; internal pull−down Watchdog trigger input 8 HS_EN LV digital input; internal pull−down HS driver enable input CAN transceiver enable input Description Output of the 5 V / 250 mA low−drop regulator Watchdog enable input Reset signal to the MCU CAN transmitter data input 9 CAN_EN LV digital input; internal pull−down 10 GND Ground connection Ground supply (all GND pins have to be connected externally) 11 CANH CAN bus interface CANH line of the CAN bus 12 CANL CAN bus interface CANL line of the CAN bus 13 GND Ground connection Ground supply (all GND pins have to be connected externally) 14 HS HV output; high−side 15 VS2 HV supply input Main supply input (HS Driver), keep floating if HS driver not used 16 VS1 HV supply input Main supply input (VR1, logic) EP Exposed pad High−side driver output Substrate (has to be connected to all GND pins externally) www.onsemi.com 4 NCV7450 Table 2. MAXIMUM RATINGS Symbol Rating Min Max Unit Vmax_VS1 DC Power Supply Voltage (Note 1) −0.3 40 V Vmax_VS2 DC Power Supply Voltage (Note 1) −0.3 40 V Vmax_HS DC High−side driver Voltage −0.3 VS2+0.3 V Vmax_digIO DC voltage on digital pins (CAN_EN, WD_EN, WDI, RSTN, RxDC, TxDC, HS_EN, HS_DIAG) −0.3 VR1+0.3 V Vmax_CAN DC voltage on pin CANH and CANL −40 40 V Vmax_diff Differential DC voltage between any two pins (incl. CANH and CANL) −40 40 V Vmax_VR1 LDO Supply pin output voltage −0.3 6 or VS1+0.3 (whichever is lower) V Tj Junction Temperature Range −40 150 °C Tstg Storage Temperature Range −55 150 °C Tsld Peak Soldering Temperature (Note 3) 260 °C V_ESDHBM ESD Capability, Device HBM (Note 2) Pins VS1/2, CANH, CANL, HS −5 +5 kV V_ESDHBM ESD Capability, Device HBM (Note 2) All other pins −4 +4 kV V_ESDMM ESD Capability, Machine Model (Note 2) −250 +250 V V_ESDCDM ESD Capability, Charged Device Model (Note 2) −750 +750 V V_ESDIEC V_SCHAF MSL ESD Capability, System HBM (Note 2), pins VS1/2, CANH, CANL, HS Voltage transients per ISO7637*3, Class D, pins VS1/2, CANH and CANL −6 +6 kV Test pulse 1 −100 − V Test pulse 2a − +75 V Test pulse 3a −150 − V Test pulse 3b − +100 V Moisture Sensitivity Level 2 − Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 2. This device series incorporates ESD protection and is tested by the following methods: Device ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) Device ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Device ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101) System ESD Human Body Model tested per IEC61000−4−2 (150 pF, 330 W) Latchup Current Maximum Rating: v150 mA per JEDEC standard: JESD78. 3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Table 3. THERMAL CHARACTERISTICS Symbol Rating Value RθJA RψJA Thermal Characteristics, Thermal Resistance, Junction−to−Air (Note 4) Thermal Resistance, Junction−to−Air (Note 5) RθJC Thermal Characteristics, Thermal Resistance, Junction−to−Case Unit °C/W 54 81 °C/W 10.5 4. Value based on test board according to JESD51−3 standard, signal layer with 10% trace coverage. 5. Value based on test board according to JESD51−7 standard, signal layers with 20% trace coverage, inner planes with 90% coverage. www.onsemi.com 5 NCV7450 Table 4. RECOMMENDED OPERATING RANGES Symbol VS1 VS2 VR1 VdigIO HS Rating Min Max Unit Functional supply voltage 5 28 V Supply voltage for valid parameter specification 6 18 V 4.3 24 V 6 18 V 4.9 5.1 V 0 VR1 V Functional supply voltage Supply voltage for valid parameter specification VR1 LDO output voltage Digital inputs/outputs voltage 0 VS2 V CANH, CANL High−side driver voltage CAN bus pins voltage −40 40 V TJ Junction Temperature −40 150 °C TA Ambient Temperature −40 125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Table 5. ELECTRICAL CHARACTERISTICS (6 V v Vs1 = Vs2 v 18 V; −40°C v Tj v 150°C; unless otherwise specified.) Symbol Parameter Conditions Min Typ Max Unit VS1, VS2 SUPPLY VS_PORH VS1 POR threshold VS1 rising 3.4 − 4.1 V VS_PORL VS1 POR threshold VS1 falling 2.0 − 3.5 V Is1_off VS1 consumption, low−power VS1 = VS2 = 14 V, VR1 on (not loaded), HS load to GND, CAN bus recessive, CAN_EN = Low, HS_EN = Low, WD_EN = Low, Tj v 85°C − 25 − mA Is2_off VS2 consumption, low−power VS1 = VS2 = 14 V, HS load to GND, HS_EN = Low, Tj v 85°C − 4 − mA Is_act VS1+VS2 consumption, active VS1 = VS2 = 14 V, VR1 on (loaded by 100 mA, not included in Is_act), HS floating, CAN bus recessive, CAN_EN = High, HS_EN = High, WD_EN = High, TxDC = High − 10 20 mA VS2 overvoltage HS_EN = High 28 − − V VS2_OV_hyst VS2 overvoltage hysteresis HS_EN = High − 1 − V tfilt_VS2_OV VS2 overvoltage filter time VS2 rising 60 − 105 ms 4.9 5.0 5.1 V VS2_OV VR1 VOLTAGE REGULATOR V_VR1 Regulator output voltage 0 mA v I(VR1) v 250 mA, 6 V v VS1 v 28 V Iout_VR1 Regulator output current Maximum VR1 load current − − 250 mA Ilim_VR1 Regulator current limitation Maximum VR1 overload current, VR1 > RES_VR1 400 − 1000 mA Ishort_VR1 Regulator short current Maximum VR1 short current, VR1 < RES_VR1 133 1/3 x Ilim_VR1 333 mA Vdrop_VR1 Dropout Voltage I(VR1) = 100 mA, VS1 = 5 V ·Tj v 150°C ·Tj v 40°C (Note 6) ·Tj = −40°C − − − − 0.2 − 0.4 − 0.2 I(VR1) = 100 mA, VS1 = 4.5 V − − 0.5 I(VR1) = 50 mA, VS1 = 4.5 V − − 0.4 V Loadreg_VR1 Load Regulation 1 mA v I(VR1) v 100 mA −50 − 50 mV Linereg_VR1 Line Regulation I(VR1) v 100 mA −30 − 30 mV VR1 load capacity ESR < 200 mW, ceramic capacitor recommended 1 4.7 − mF Cload_VR1 www.onsemi.com 6 NCV7450 Table 5. ELECTRICAL CHARACTERISTICS (6 V v Vs1 = Vs2 v 18 V; −40°C v Tj v 150°C; unless otherwise specified.) Symbol Parameter Conditions Min Typ Max Unit 4.3 4.5 4.7 V 0.05 0.1 0.2 V VR1 VOLTAGE REGULATOR RES_VR1 VR1 Reset threshold VR1 voltage decreasing RES_hyst_VR1 VR1 Reset threshold hysteresis tfilt_RES_VR1 VR1 undervoltage filter time − 15 − ms VR1 off time after TSD − 1.0 − s toff_VR1 Is_add_VR1 VS consumption adder of VR1 (Note 6) − 0.02 x I(VR1) − A On−resistance Tj = 25°C (Note 6) − 0.3 − W Tj = 125°C − − 0.6 Tj = 125°C, Vs2 = 4.3 V (Note 6) − − 0.8 Tj = 150°C − − 0.7 HS DRIVER Ron_HS Ilim_HS Current Limitation −3.7 −3 −2.5 A Ioc_HS Overcurrent threshold −3.7 −2.7 −1.7 A Iuld_HS Underload detection threshold −40 − −6.0 mA Ileak_HS Output leakage current −1 −5 − − − − td_on_HS Output delay time td_off_HS Output delay time td_oc_HS Overcurrent detection filter time HS off ; V(HS) = 0 V Tj = 25°C (Note 6) Tj = 150°C mA HS_EN = Low −> High; V(HS) = 0.1 x Vs2 ·HS_EN was Low for more than 30 ms ·HS_EN was Low for less than 20 ms − − 140 40 − − HS_EN = High −> Low; V(HS) = 0.9 x Vs2 − 40 − ms − − 65 ms ms tdb_uld_HS Underload detection blanking delay Timer started after driver activation and V(HS) = Vs2 – 2 V − − 130 ms td_uld_HS Underload detection filter time HS Driver active, tdb_uld_HS elapsed − − 70 ms dVout_HS Slew rate HS load = 16 Ω to GND − 0.2 − V/ms Is_add_HS HS consumption from VS2 HS_EN = High; HS pin floating 2.0 4.4 8.0 mA −15 − +15 % − 65 − ms WATCHDOG TIMING (see Figure 3) twd_acc Watchdog timing accuracy t_wd_TO Timeout watchdog period t_wd_CW Window watchdog closed window − 6 − ms t_wd_OW Window watchdog open window − 100 − ms t_RSTN Reset pulse length after VR1 undervoltage or watchdog failure − 8 − ms 6.0 − − ms 1.0 6 12 mA −8.0 −3 −1.0 mA 2.0 5 12 mA t_WDI After WD_EN low −> high transition or RSTN pulse Minimum WDI pulse width accepted as a watchdog service DIGITAL OUTPUTS, RxDC, HS_DIAG IoutL_pinx Low−level output driving current pinx is logical Low, forced V(pinx) = 0.4 V IoutH_pinx High−level output driving current pinx is logical High, forced V(pinx) = VR1 − 0.4 V DIGITAL OUTPUT RSTN IoutL_RSTN Low−level output driving current RSTN is active (logical Low), forced V(RSTN) = 0.4 V www.onsemi.com 7 NCV7450 Table 5. ELECTRICAL CHARACTERISTICS (6 V v Vs1 = Vs2 v 18 V; −40°C v Tj v 150°C; unless otherwise specified.) Symbol Parameter Conditions Min Typ Max Unit VR1 > 4.7 V, I(RSTN) = 0.7 mA − − 0.4 V VR1 > 2 V, VS1 < VR1, I(RSTN) = 0.1 mA − − 0.4 VS1 > 2 V, I(RSTN) = 0.3 mA − − 0.4 5.0 10 19 kW DIGITAL OUTPUT RSTN Low−level output voltage, low VR1/VS1 VoutL_RSTN Rpullup_RSTN Internal pull−up resistor to VR1 DIGITAL INPUTS TxDC, CAN_EN, WD_EN, HS_EN, WDI VinL_pinx Low−level input voltage (logical “Low”) 0 − 0.8 V VinH_pinx High−level input voltage (logical “High”) 2.0 − VR1 V Vin_hys_pinx Input voltage hysteresis 100 − 500 mV Rpullup_pinx Internal pull−up resistor to VR1; pin TxDC 55 100 185 kΩ Rpulldown_pinx Internal pull−down resistor to ground; pins CAN_EN, HS_EN, WDI 55 100 185 kΩ Ipullup_WD_EN Internal pull−up current to VR1, pin WD_EN V(WD_EN) = 0 V, pull−up current source active 50 100 200 mA tper_pullup_WDEN WD_EN pull−up current source activation period WD_EN = CAN_EN = HS_EN = Low − 610 − ms ton_pullup_WDEN WD_EN = CAN_EN = HS_EN = Low − 5.0 − ms WD_EN pull−up current source activation on−time THERMAL PROTECTION Tsd1 Thermal shutdown level 1 Temperature increasing; HS switched off consequently 145 155 165 °C Tsd2 Thermal shutdown level 2 Temperature increasing; VR1 and CAN switched off consequently 165 175 185 °C Thermal shutdown recovery temperature Temperature decreasing; HS switched on 135 145 155 °C Tsd1_off 6. Not tested in production, guaranteed by design. Reset or previous WD service nominal t _wd_TO Timeout WD period Safe trigger of timeout WD Previous WD service ÎÎÎÎÎÏÏÏÏÏÏÏ ÎÎÎÎÎÏÏÏÏÏÏÏ WD expired t_ wd_TO tolerance nominal t _wd_OW t_wd_trig ÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÎÎÎ nominal t _wd_CW Window WD period Closed window (WD trigger would be too early ) Safe trigger of window WD OK20121113 .01 t _wd_CW tolerance Figure 3. Watchdog modes timing www.onsemi.com 8 recommended WD trigger ÎÎÎ ÎÎÎ ÎÎÎ t _wd_OW tolerance NCV7450 Table 6. ELECTRICAL CHARACTERISTICS (CONTINUED) (VR1 = 4.75 V to 5.25 V; TJ = −40°C to +150°C; RLT = 60 W, CLT = 100 pF, C1 not used unless specified otherwise.) Symbol Parameter Conditions Min Typ Max Unit CAN BUS LINES (Pins CANH and CANL) Recessive output current at pins CANH and CANL CAN enabled; −27 V < VCANH/L < +32 V −5.0 − +5.0 mA Input leakage current 0 < R(VR1 to GND) < 1 MW VCANH = VCANH = 5 V −5.0 0 +5.0 mA Vo(rec) (CANH) Recessive output voltage at pin CANH CAN enabled; VTxDC = VR1 2.0 2.5 3.0 V Vo(rec) (CANL) Recessive output voltage at pin CANL CAN enabled; VTxDC = VR1 2.0 2.5 3.0 V Vo(off) (CANH) Recessive output voltage at pin CANH CAN disabled −0.1 0 0.1 V Vo(off) (CANL) Recessive output voltage at pin CANL CAN disabled −0.1 0 0.1 V Differential bus output voltage in off mode (VCANH − VCANL) CAN disabled −0.2 0 0.2 V Vo(dom) (CANH) Dominant output voltage at pin CANH 50 Ω < RLT < 65 Ω; VTxDC = 0 V; t < tdom(TxDC) 2.75 3.5 4.5 V Vo(dom) (CANL) Dominant output voltage at pin CANL 50 Ω < RLT < 65 Ω; VTxDC = 0 V; t < tdom(TxDC) 0.5 1.5 2.25 V Vo(dom)(sym) Dominant output CANH/CANL drivers symmetry (VCANH + VCANL) RLT = 60 Ω; C1 = 4.7 nF; TxDC driven by square wave up to 1 MHz 0.9 1.1 VR1 Vo(dom) (diff) Differential bus output voltage (VCANH − VCANL) VTxDC = 0 V; dominant; 45 Ω < RLT < 65 Ω 1.5 3.0 V Differential bus output voltage during arbitration (VCANH − VCANL) VTxDC = 0 V; dominant; RLT = 2240 Ω; (Note 7) 1.5 5.0 V Vo(rec) (diff) Differential bus output voltage (VCANH − VCANL) VTxDC = VR1; recessive; no load −50 0 +50 mV Io(sc) (CANH) Short circuit output current at pin CANH VCANH = −3 V; VTxDC = 0 V −3 V ≤ VCANH ≤ +18 V −100 −100 −70 −40 1.0 mA Io(sc) (CANL) Short circuit output current at pin CANL VCANL = 36 V; VTxDC = 0 V −3 V ≤ VCANL ≤ +18 V 40 −1.0 70 100 100 mA Vi(th)(diff)_NORM Differential receiver threshold voltage in normal mode CAN enabled; −12 V ≤ VCANH ≤ +12 V; −12 V ≤ VCANL ≤ +12 V 0.5 − 0.9 V Vi(rec)(diff)_NORM Differential receiver input voltage for recessive state in normal mode CAN enabled; −12 V ≤ VCANH ≤ +12 V; −12 V ≤ VCANL ≤ +12 V −3.0 − 0.5 V Vi(dom)(diff)_NORM Differential receiver input voltage for dominant state in normal mode CAN enabled; −12 V ≤ VCANH ≤ +12 V; −12 V ≤ VCANL ≤ +12 V 0.9 − 8.0 V Vi(th)(diff)_WU Differential receiver threshold voltage in wakeup−detection mode CAN in wakeup−detection mode; −12 V ≤ VCANH ≤ +12 V; −12 V ≤ VCANL ≤ +12 V 0.4 − 1.05 V Vi(rec)(diff) _WU Differential receiver input voltage for recessive state in wakeup−detection mode CAN in wakeup−detection mode; −12 V ≤ VCANH ≤ +12 V; −12 V ≤ VCANL ≤ +12 V −3.0 − 0.4 V Vi(dom)(diff)_WU Differential receiver input voltage for dominant state in wakeup−detection mode CAN in wakeup−detection mode; −12 V ≤ VCANH ≤ +12 V; −12 V ≤ VCANL ≤ +12 V 1.05 − 8.0 V Common−mode input resistance at pin CANH −2 V ≤ VCANH ≤ +7 V; −2 V ≤ VCANL ≤ +7 V 15 25 37 kΩ Io(rec) ILI Vo(off) (diff) Vo(dom) (diff)_arb Ri(cm) (CANH) www.onsemi.com 9 2.25 NCV7450 Table 6. ELECTRICAL CHARACTERISTICS (CONTINUED) (VR1 = 4.75 V to 5.25 V; TJ = −40°C to +150°C; RLT = 60 W, CLT = 100 pF, C1 not used unless specified otherwise.) Symbol Parameter Conditions Min Typ Max Unit CAN BUS LINES (Pins CANH and CANL) Ri(cm) (CANL) Common−mode input resistance at pin CANL −2 V ≤ VCANH ≤ +7 V; −2 V ≤ VCANL ≤ +7 V 15 25 37 kΩ Ri(cm) (m) Matching between pin CANH and pin CANL common mode input resistance VCANH = VCANL = 5 V −1.0 0 +1.0 % Differential input resistance −2 V ≤ VCANH ≤ +7 V; −2 V ≤ VCANL ≤ +7 V 25 50 75 kΩ Ci(CANH) Input capacitance at pin CANH VTxDC = VR1; (Note 7) − 7.5 20 pF Ci(CANL) Input capacitance at pin CANL VTxDC = VR1; (Note 7) − 7.5 20 pF Differential input capacitance VTxDC = VR1; (Note 7) − 3.75 10 pF Ri(diff) Ci(diff) TIMING CHARACTERISTICS (see Figure 4 and Figure 5) td(TxDC−BUSon) Delay TxDC to bus dominant − 65 − ns td(TxDC−BUSoff) Delay TxDC to bus recessive − 90 − ns td(BUSon−RxDC) Delay bus dominant to RxDC − 60 − ns td(BUSoff−RxDC) Delay bus recessive to RxDC − 65 − ns tpd_dr Propagation delay TxDC to RxDC dominant to recessive transition 50 100 210 ns tpd_rd Propagation delay TxDC to RxDC recessive to dominant transition 50 120 210 ns td(stb−nm) Delay wake−up detection mode to normal mode 7.0 25 47 ms twake_filt Dominant time for wake−up via bus CAN_EN = low 0.15 − 1.8 ms tdwakerd Delay to flag wake event (recessive to dominant transitions) Valid bus wake−up event 0.5 − 10 ms tdwakedr Delay to flag wake event (dominant to recessive transitions) Valid bus wake−up event 0.5 − 10 ms twake_to Bus time for wake−up timeout CAN_EN = low 1.0 − 10 ms tdom(TxDC) TxDC dominant time for timeout CAN_EN = high; VTxDC = 0 V 1.0 − 10 ms tBit(RxDC) Bit time on RxDC pin tBit(TxDC) = 500 ns 400 − 550 ns tBit(TxDC) = 200 ns 120 − 220 ns tBit(TxDC) = 500 ns 435 − 530 ns tBit(TxDC) = 200 ns 155 − 210 ns tBit(TxDC) = 500 ns −65 − 40 ns tBit(TxDC) = 200 ns −45 − 15 ns tBit(Vi(diff)) DtRec Bit time on bus (CANH – CANL pin) Receiver timing symmetry DtRec = tBit(RxDC) − tBit(Vi(diff)) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 7. Not tested in production, guaranteed by design. www.onsemi.com 10 NCV7450 6-18 V 100 nF VS1 VS2 VR1 CANH 2.2 uF CAN _EN R LT C LT NCV 7450 100 pF 60 W TxDC CANL RxDC 15 pF GND Figure 4. Test Circuit for Timing Characteristics 0.7 x VR1 TxDC 0.3 x VR1 0.3 x VR1 t Bit(TxDC) t d(TxDC−BUSon ) 5 x t Bit(TxDC) Vi(diff) = VCANH − VCANL tpd_rd td(BUSon −RxDC ) 900 mV 500 mV t Bit(Vi(diff )) td(TxDC−BUSoff ) d(BUSoff −RxDC)) tpd_dr 0.7 x VR1 RxDC 0.3 x VR1 t Bit(RxDC ) Figure 5. CAN Transceiver Timing Diagram www.onsemi.com 11 NCV7450 FUNCTIONAL DESCRIPTION Supply Concept V(VR1) The device has two independent supply pins VS1 and VS2. While VR1 regulator and logic control are supplied from VS1, High−side driver is supplied from VS2. Both supply lines have to be properly decoupled by filtration capacitors close to the device pins. As long as VS1 < VS_POR level, all the blocks are in power−down mode. V_VR1 RES_hys_VR1 RES_VR1 VR1 Low−drop Regulator Ishort _VR1 VR1 is a low−drop output regulator providing 5 V voltage derived from the VS1 main supply. It is able to deliver up to 250 mA and is primarily intended to supply the on−chip CAN transceiver, the application microcontroller unit (MCU) and related 5 V loads (e.g. its own MCU−related digital inputs/outputs). An external capacitor needs to be connected on VR1 pin in order to ensure the regulator’s stability and to filter the disturbances caused by the connected loads. VR1 voltage is supplying all the digital low−voltage input/output pins. The protection and monitoring of the VR1 regulator consist of the following features: ♦ VR1 Current Limitation – the two−level current limitation controlled by VR1 reset comparator to reduce the power dissipation in case of shorts to ground by the current fold−back (see Figure 7) ♦ VR1 Reset Comparator – the VR1 regulator output is compared with a reset level RES_VR1. If the VR1 level drops below this level for longer than tflt_RES_VR1, a reset towards the MCU is generated through the RSTN pin and peripherals (CAN transceiver and HS driver) disabled. ♦ Temperature (see Figure 14) V(VS) V(VR1) CAN Transceiver The SBC contains one high−speed CAN transceiver compliant with ISO11898−2:2016, supporting bit rates up to 5 Mbit/s. The transceiver consists of the following sub−blocks: transmitter, receiver, and wakeup detector. If enabled (CAN_EN = High), the CAN transceiver is ready to provide the full−speed interface between the bus and a CAN controller connected on pins RxDC (received data) and TxDC (data to transmit). The bus lines are biased to VR1 / 2. In order to prevent a faulty node from blocking the bus traffic, the maximum length of the transmitted dominant symbol is limited by a timeout counter to tdom(TxDC). In case the TxDC Low signal exceeds the timeout value, the transmitter returns automatically to the recessive state. The transmission is again de−blocked when TxDC pin returns to high (recessive) state. If the CAN block is disabled (CAN_EN = Low) or RSTN pin active (Low) due to failed watchdog service or VR1 undervoltage, the CAN transceiver is in its wake−up detection state. The bus lines are biased to ground. Logical level on TxDC is ignored and pin RxDC is kept high until a CAN bus wake−up is detected. The CAN bus wake−up corresponds to a pattern consisting of dominant – recessive – dominant symbols of at least twake_filt each. The RxDC starts following the CAN bus afterwards. The pattern must be received within twake_to to be recognized as a valid wake−up event, otherwise internal wake−up logic is reset. Vdrop_VR1 tfilt_VR1_RES 100 mH) an external freewheeling diode connected between GND and the HS pin is required. HS high−side driver is intended to drive an external load. Its state is directly controlled via HS_EN pin and diagnostics are flagged on HS_DIAG pin (see Table 7). When the driver is enabled (HS_EN = High), it is protected against an excessive current and temperature and diagnosed on Underload condition. In case the HS driver is controlled by a PWM signal through HS_EN with very low duty−cycle, the diagnostic Table 7. HS Driver Diagnostics Event HS_EN Failure condition HS status HS_DIAG Recovery condition Low − Off High − High − On High − High I(HS) > Ioc_HS Off Low HS_EN = Low High I(HS) < Iuld_HS On Low I(HS) > Iuld_HS Over−temperature High Tj > Tsd1 Off Low Tj < Tsd1_off VS2 Overvoltage High VS2 > VS2_OV Off Low VS2 < VS2_OV RSTN active High RSTN = Low Off Low RSTN = High Normal operation (no failure) Overcurrent Underload Short−to−battery Unpowered Any mode Vs < Vs_PORL Vs > Vs_PORH Reset No trigger within t_wd_TO WD_EN = high Disabled Trigger Trigger WD_EN = high WD_EN = low No trigger within t_wd_OW Closed Window Timeout t_wd_CW elapsed Trigger Figure 9. Watchdog operating modes Watchdog Open Window WD Enable The on−chip watchdog requires that the MCU software “triggers” or “services” the watchdog in a specified time frame. A correct watchdog service consists of high−to−low transition on the WDI input. The watchdog timer restarts immediately after a successful trigger is received. After any Reset event (power−up, watchdog failure, VR1 undervoltage, thermal shutdown 2) or watchdog enable (WD_EN = Low −> High), the watchdog always starts in a timeout mode. The MCU software must serve the watchdog any time before the timeout expiration. After the watchdog is triggered for the first time, it starts working in a window mode operation: the watchdog time is split to two distinct parts – a closed window, where the watchdog may not be triggered, is followed by an open window where the MCU must send a valid watchdog trigger (see Figure 10). WD_EN Service Service Service WDI RSTN WD status off Timeout Closed window Open window