NCV7513AFTR2G

NCV7513A FLEXMOSt Hex Low-Side MOSFET Pre-Driver The NCV7513A programmable six channel low−side MOSFET pre−driver is one of a family of FLEXMOSTM automotive grade products for driving logic −level MOSFETs. The product is controllable by a combination of serial SPI and parallel inputs. It features programmable fault management modes and allows power−limiting PWM operation with programmable refresh time. The device offers 3.3 V/5.0 V compatible inputs and the serial output driver can be powered from either 3.3 V or 5.0 V. Power−on reset provides controlled powerup and two enable inputs allow all outputs to be simultaneously disabled. Each channel independently monitors its external MOSFET’s drain voltage for fault conditions. Shorted load fault detection thresholds are fully programmable using an externally programmed reference voltage and a combination of four discrete internal ratio values. The ratio values are SPI selectable and allow different detection thresholds for each group of three output channels. Fault information for each channel is 2−bit encoded by fault type and is available through SPI communication. Fault recovery operation for each channel is programmable and may be selected for latch−off or automatic retry. The FLEXMOS family of products offers application scalability through choice of external MOSFETs. Features http://onsemi.com MARKING DIAGRAM 32 LEAD LQFP FT SUFFIX CASE 873A NCV7513A AWLYYWWG A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device NCV7513AFTG Package LQFP (Pb−Free) Shipping† 250 Units/Tray • • • • • • • • • • • 16−Bit SPI with Frame Error Detection 3.3 V/5.0 V Compatible Parallel and Serial Control Inputs 3.3 V/5.0 V Compatible Serial Output Driver Two Enable Inputs Open−Drain Fault and Status Flags Programmable − Shorted Load Fault Detection Thresholds − Fault Recovery Mode − Fault Retry Timer − Flag Masking Load Diagnostics with Latched Unique Fault Type Data − Shorted Load − Open Load − Short to GND AEC Qualified PPAP Capable NCV Prefix for Automotive and Other Applications Requiring Site and Change Controls These are Pb−Free Devices* NCV7513AFTR2G LQFP 2000 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Benefits • Scalable to Load by Choice of External MOSFET *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 March, 2009 − Rev. 1 1 Publication Order Number: NCV7513A/D NCV7513A IN5 IN4 IN3 IN2 IN1 IN0 ENA2 VCC2 NCV7513A Hex MOSFET Pre−Driver VCC1 POWER ON RESET & BIAS CHANNEL 0 FAULT DETECT VSS VCC2 DRN0 POR ENA1 GATE SELECT FLAG MASK DISABLE MODE REFRESH/REF ENA ENA VCC2 DRN 1 2 REF DISABLE PARALLEL SERIAL IREF ENA ENA VCC2 DRN 1 2 REF DISABLE PARALLEL SERIAL DRIVER GAT0 VSS CHANNEL 1 DRN1 CSB SCLK SI VDD SO VCC POR CSB SCLK SI 6 VSS GAT1 DRN2 CHANNEL 2 16 BIT SPI IREF ENA ENA VCC2 DRN 1 2 REF DISABLE PARALLEL SERIAL VSS GAT2 DRN3 CHANNEL 3 DRIVER SO ENA ENA VCC2 1 2 REF DISABLE PARALLEL SERIAL DRN 12 IREF VSS GAT3 DRN4 VSS CHANNEL 4 FAULT BITS FLTB FAULT LOGIC & REFRESH TIMER ENA1 ENA ENA VCC2 DRN 1 2 REF DISABLE PARALLEL SERIAL IREF VSS GAT4 DRN5 CHANNEL 5 2 GND CLOCK ENA 1 IREF VSS GAT5 VSS 4 FLTREF + FAULT REFERENCE GENERATOR CH 0−2 CH 3−5 DRN 0:5 MASK 0:5 POR DRAIN FEEDBACK MONITOR STAB − OA Figure 1. Block Diagram http://onsemi.com 2 NCV7513A 28W 28W 14W M +5V POWER−ON RESET RX1 RFILT +5V OR +3.3V CB1 VCC1 FLTREF ENA1 VCC2 DRN0 GAT0 DRN1 GAT1 DRN2 RD2 NID9N05CL RD1 NID9N05CL RD0 NID9N05CL RST RX2 ENA2 IN0 IN1 IN2 IN3 HOST CONTROLLER PARALLEL NCV7513A GAT2 DRN3 GAT3 DRN4 GAT4 DRN5 GAT5 VDD SO VSS RD5 RD4 RD3 UNCLAMPED LOAD CB2 NID9N05CL NID9N05CL NID9N05CL VLOAD SPI IN4 IN5 FLTB CSB SCLK IRQ I/O RFPU SI STAB RSPU GND Figure 2. Application Diagram http://onsemi.com 3 14W 5W NCV7513A PIN FUNCTION DESCRIPTION Symbol FLTREF DRN0 – DRN5 GAT0 – GAT5 ENA1, ENA2 IN0 – IN5 CSB SCLK SI SO STAB FLTB VCC1 GND VCC2 VDD VSS Description Analog Fault Detect Threshold: 5.0 V Compliant Analog Drain Feedback: Internally Clamped Analog Gate Drive: 5.0 V Compliant Digital Master Enable Inputs: 3.3 V/5.0 V (TTL) Compatible Digital Parallel Input: 3.3 V/5.0 V (TTL) Compatible Digital Chip Select Input: 3.3 V/5.0 V (TTL) Compatible Digital Shift Clock Input: 3.3 V/5.0 V (TTL) Compatible Digital Serial Data Input: 3.3 V/5.0 V (TTL) Compatible Digital Serial Data Output: 3.3 V/5.0 V Compliant Digital Open−Drain Output: 3.3 V/5.0 V Compliant Digital Open−Drain Output: 3.3 V/5.0 V Compliant Power Supply − Low Power Path Power Return − Low Power Path – Device Substrate Power Supply − Gate Drivers Power Supply − Serial Output Driver Power Return – VCC2, VDD, Drain Clamps DRN2 DRN3 DRN4 DRN5 GAT2 GAT3 GAT4 24 23 22 21 20 19 18 17 GAT1 DRN1 GAT0 DRN0 VCC2 VCC1 FLTREF GND 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 16 15 14 VSS STAB VDD SO SI SCLK CSB FLTB GAT5 13 12 11 10 9 ENA1 NCV7513A IN0 IN1 IN2 IN3 IN4 IN5 Figure 3. 32 Pin LQFP Pinout (Top View) http://onsemi.com 4 ENA2 NCV7513A MAXIMUM RATINGS (Voltages are with respect to device substrate.) Rating DC Supply (VCC1, VCC2, VDD) Difference Between VCC1 and VCC2 Difference Between GND (Substrate) and VSS Output Voltage (Any Output) Drain Feedback Clamp Voltage (Note 1) Drain Feedback Clamp Current (Note 1) Input Voltage (Any Input) Junction Temperature, TJ Storage Temperature, TSTG Peak Reflow Soldering Temperature: Lead−Free 60 to 150 seconds at 217°C (Note 2) Value −0.3 to 6.5 "0.3 "0.3 −0.3 to 6.5 −0.3 to 40 10 −0.3 to 6.5 −40 to 150 −65 to 150 260 peak Unit V V V V V mA V °C °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ATTRIBUTES Characteristic ESD Capability Human Body Model Machine Model Moisture Sensitivity (Note 2) Package Thermal Resistance (Note 3) Junction–to–Ambient, RqJA Junction–to–Pin, RYJL Value w " 2.0 kV w " 200 V MSL3 86.0 °C/W 58.5 °C/W 1. An external series resistor must be connected between the MOSFET drain and the feedback input in the application. Total clamp power dissipation is limited by the maximum junction temperature, the application environment temperature, and the package thermal resistances. 2. For additional information, see or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D, and Application Note AND8003/D. 3. Values represent still air steady−state thermal performance on a 4 layer (42 x 42 x 1.5 mm) PCB with 1 oz. copper on an FR4 substrate, using a minimum width signal trace pattern (384 mm2 trace area). RECOMMENDED OPERATING CONDITIONS Symbol VCC1 VCC2 VDD VIN High VIN Low TA Main Power Supply Voltage Gate Drivers Power Supply Voltage Serial Output Driver Power Supply Voltage Logic High Input Voltage Logic Low Input Voltage Ambient Still−Air Operating Temperature Parameter Min 4.75 VCC1 − 0.3 3.0 2.0 0 −40 Max 5.25 VCC1 + 0.3 VCC1 VCC1 0.8 125 Unit V V V V V °C http://onsemi.com 5 NCV7513A ELECTRICAL CHARACTERISTICS (4.75 VvVCCXv5.25 V, VDD = VCCX, −40°CvTJv125°C, unless otherwise specified.) (Note 4) Characteristic VCC1 Supply Operating Current – VCC1 = 5.25 V, VFLTREF = 1.0 V ENAX = 0 ENA1 = ENA2 = VCC1, VDRNX = 0 V, GATX drivers off ENA1 = ENA2 = VCC1, GATX drivers on VCC1 Rising − ENAX, INX, SI, SCLK, CSB ENAX, INX, SI, SCLK, CSB ENAX, INX, SI, SCLK, CSB CSB VIN = 0 V ENA2, INX, SI, SCLK, VIN = VCC1 ENA1 VDD = 3.3 V, ISINK = 5.0 mA VDD = 3.3 V, ISOURCE = 5.0 mA Output High or Low CSB = 3.3 V STAB Active, ISTAB = 1.25 mA VSTAB = VCC1 FLTB Active, IFLTB = 1.25 mA VFLTB = VCC1 VFLTREF = 0 V (Note 5) (Note 5) VCL IDRNX = 10 mA IDRNX = ICL(MAX) = 10 mA Register 2: R1 = 0, R0 = 0 or R4 = 0, R3 = 0 Register 2: R1 = 0, R0 = 1 or R4 = 0, R3 = 1 Register 2: R1 = 1, R0 = 0 or R4 = 1, R3 = 0 Register 2: R1 = 1, R0 = 1 or R4 = 1, R3 = 1 DRNX Input Leakage Current VCC1 = VCC2 = VDD = 5.0 V, ENAX = INX = 0 V, VDRNX = VCL(MIN) VCC1 = VCC2 = VDD = 0 V, ENAX = INX = 0 V, VDRNX = VCL(MIN) – – – 3.65 0.150 2.0 – 100 −25 – 100 – VDD − 0.25 – −10 – – – – −1.0 0 30 27 – 20 45 70 95 −1.0 2.80 3.10 2.80 4.20 0.385 – – 330 −10 10 150 0.11 VDD − 0.11 22 – 0.1 – 0.1 – – – – 32 33.6 25 50 75 100 – 5.0 5.0 5.0 4.60 – – 0.8 500 – 25 200 0.25 – – 10 0.25 10 0.25 10 – VCC1 − 2.0 – – 37 30 55 80 105 1.0 V V V V mV mA mA kW V V W mA V mA V mA mA V dB V % VFLTREF % VFLTREF % VFLTREF % VFLTREF mA mA Symbol Conditions Min Typ Max Unit Power−On Reset Threshold Power−On Reset Hysteresis Digital I/O VIN High VIN Low VIN Hysteresis Input Pullup Current Input Pulldown Current Input Pulldown Resistance SO Low Voltage SO High Voltage SO Output Resistance SO Tri−State Leakage Current STAB Low Voltage STAB Leakage Current FLTB Low Voltage FLTB Leakage Current Fault Detection – GATX ON FLTREF Input Current FLTREF Input Linear Range FLTREF Op−amp VCC1 PSRR DRNX Clamp Voltage DRNX Shorted Load Threshold GATX Output High VFLTREF = 1.0 V 4. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100% parametrically tested in production. 5. Guaranteed by design. http://onsemi.com 6 NCV7513A ELECTRICAL CHARACTERISTICS (continued) (4.75 VvVCCXv5.25 V, VDD = VCCX, −40°CvTJv125°C, unless otherwise specified.) (Note 6) Characteristic Fault Detection – GATX OFF DRNX Diagnostic Current ISG IOL DRNX Fault Threshold Voltage DRNX Off State Bias Voltage Gate Driver Outputs GATX Output Resistance GATX High Output Current GATX Low Output Current Turn−On Propagation Delay Turn−Off Propagation Delay Output Rise Time tP(ON) tP(OFF) tR Output High or Low VGATX = 0 V VGATX = VCC2 INX to GATX (Figure 4) CSB to GATX (Figure 5) INX to GATX (Figure 4) CSB to GATX (Figure 5) 20% to 80% of VCC2, CLOAD = 400 pF (Figure 4, Note 5) Output Fall Time tF 80% to 20% of VCC2, CLOAD = 400 pF (Figure 4, Note 5) Fault Timers Channel Fault Blanking Timer tBL(ON) tBL(OFF) Channel Fault Filter Timer Global Fault Refresh Timer (Auto−retry Mode) Timer Clock SO Supply Voltage SCLK Clock Period Maximum Input Capacitance SCLK High Time SCLK Low Time Sl Setup Time Sl Hold Time VDD tFF tFR VDRNX = 5.0 V; INX rising to FLTB falling (Figure 6) VDRNX = 0 V; INX falling to FLTB falling (Figure 6) Figure 7 Register 2: Bit R2 = 0 or R5 = 0 Register 2: Bit R2 = 1 or R5 = 1 ENA1 = 1 3.3 V Interface 5.0 V Interface − Sl, SCLK (Note 7) SCLK = 2.0 V to 2.0 V SCLK = 0.8 V to 0.8 V Sl = 0.8 V/2.0 V to SCLK = 2.0 V (Note 7) SCLK = 2.0 V to Sl = 0.8 V/2.0 V (Note 7) 30 90 7.0 7.5 30 – 3.0 4.5 – – 125 125 25 25 45 120 12 10 40 500 3.3 5.0 250 – – – – – 60 150 17 12.5 50 – 3.6 5.5 – 12 – – – – ms ms ms ms ms kHz V V ns pF ns ns ns ns – – 1.40 ms 1.0 −5.25 1.9 – – – 1.80 – – – – – 2.5 −1.9 5.25 1.0 1.0 1.40 kW mA mA ms ms ms VSG VOL VCTR Short to GND Detection, VDRNX = 0.30 VCC1 Open Load Detection, VDRNX = 0.75 VCC1 Short to GND Detection Open Load Detection − −27 30 27 72 – −20 60 30 75 50 −10 80 33 78 – mA mA %VCC1 %VCC1 %VCC1 Symbol Conditions Min Typ Max Unit Serial Peripheral Interface (Figure 9) Vccx = 5.0 V, VDD = 3.3 V, FSCLK = 4.0 MHz, CLOAD = 200 pF 6. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100% parametrically tested in production. 7. Guaranteed by design. http://onsemi.com 7 NCV7513A ELECTRICAL CHARACTERISTICS (continued) (4.75 VvVCCXv5.25 V, VDD = VCCX, −40°CvTJv125°C, unless otherwise specified.) (Note 8) Characteristic Symbol Conditions Min Typ Max Unit Serial Peripheral Interface (continued) (Figure 9) Vccx = 5.0 V, VDD = 3.3 V, FSCLK = 4.0 MHz, CLOAD = 200 pF SO Rise Time SO Fall Time CSB Setup Time CSB Hold Time CSB to SO Time SO Delay Time Transfer Delay Time (20% VSO to 80% VDD) CLOAD = 200 pF (Note 9) (80% VSO to 20% VDD) CLOAD = 200 pF (Note 9) CSB = 0.8 V to SCLK = 2.0 V (Note 9) SCLK = 0.8 V to CSB = 2.0 V (Note 9) CSB = 0.8 V to SO Data Valid (Note 9) SCLK = 0.8 V to SO Data Valid (Note 9) CSB Rising Edge to Next Falling Edge (Note 9) – – 60 75 – – 1.0 25 – – – 65 65 – 50 50 – – 125 125 – ns ns ns ns ns ns ms 8. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100% parametrically tested in production. 9. Guaranteed by design. http://onsemi.com 8 NCV7513A INX 50% tP(OFF) GAT X tP(ON) 50% 80% 20% tR tF Figure 4. Gate Driver Timing Diagram – Parallel Input CSB 50% GX tP(OFF) GAT X tP(ON) Figure 5. Gate Driver Timing Diagram – Serial Input 50% DRNX INX 50% tBL(ON) FLTB 50% tBL(OFF) 50% Figure 6. Blanking Timing Diagram http://onsemi.com 9 NCV7513A OPEN LOAD THRESHOLD DRNX SHORTED LOAD THRESHOLD INX tFF FLTB 50% tFF 50% Figure 7. Filter Timing Diagram GAT X tBL(ON) tFR tFF tFR tBL(ON) tFR DRNX SHORTED LOAD THRESHOLD (FLTREF) INX Figure 8. Fault Refresh Timing Diagram CSB SETUP TRANSFER DELAY CSB SI SETUP CSB HOLD 16 SCLK 1 SI HOLD SI CSB to SO VALID MSB IN BITS 14...1 SO DELAY LSB IN SO RISE,FALL SO MSB OUT BITS 14...1 LSB OUT SEE NOTE 80% VDD 20% VDD Note: Not defined but usually MSB of data just received. Figure 9. SPI Timing Diagram http://onsemi.com 10 NCV7513A DETAILED OPERATING DESCRIPTION General The NCV7513A is a six channel general purpose low−side pre−driver for controlling and protecting N−type logic level MOSFETs. While specifically designed for driving MOSFETs with resistive, inductive or lamp loads in automotive applications, the device is also suitable for industrial and commercial applications. Programmable fault detection and protection modes allow the NCV7513A to accommodate a wide range of external MOSFETs and loads, providing the user with flexible application solutions. Separate power supply pins are provided for low and high current paths to improve analog accuracy and digital signal integrity. ON Semiconductor’s SMARTDISCRETES TM clamp MOSFETs, such as the NID9N05CL, are recommended when driving unclamped inductive loads. Power Up/Down Control The NCV7513A’s powerup/down control prevents spurious output operation by monitoring the VCC1 power supply. An internal Power−On Reset (POR) circuit causes all GATX outputs to be held low until sufficient voltage is available to allow proper control of the device. All internal registers are initialized to their default states, fault data is cleared, and the open−drain fault (FLTB) and status (STAB) flags are disabled. When VCC1 exceeds the POR threshold, outputs and flags are enabled and the device is ready to accept input data. When VCC1 falls below the POR threshold during power down, flags are reset and disabled and all GATX outputs are driven and held low until VCC1 falls below about 0.7 V. SPI Communication The NCV7513A is a 16−bit SPI slave device. SPI communication between the host and the NCV7513A may either be parallel via individual CSB addressing or daisy−chained through other devices using a compatible SPI protocol. The active−low CSB chip select input has a pullup current source. The SI and SCLK inputs have pulldown current sources. The recommended idle state for SCLK is low. The tri−state SO line driver can be supplied with either 3.3 or 5.0 V and is powered via the device’s VDD and VSS pins. The NCV7513A employs frame error detection that requires integer multiples of 16 SCLK cycles during each CSB high−low−high cycle (valid communication frame.) A frame error does not affect the flags. The CSB input controls SPI data transfer and initializes the selected device’s frame error and fault reporting logic. The host initiates communication when a selected device’s CSB pin goes low. Output (fault) data is simultaneously sent MSB first from the SO pin while input (command) data is received MSB first at the SI pin under synchronous control of the master’s SCLK signal while CSB is held low (Figure 10). Fault data changes on the falling edge of SCLK and is guaranteed valid before the next rising edge of SCLK. Command data received must be valid before the rising edge of SCLK. When CSB goes low, frame error detection is initialized, latched fault data is transferred to the SPI, and the FLTB flag is disabled and reset if previously set. Data for faults detected while CSB is low are ignored but will be captured if still present after CSB goes high. If a valid frame has been received when CSB goes high, the last multiple of 16 bits received is decoded into command data, and FLTB is re−enabled. Latched (previous) fault data is cleared and current fault data is captured. The FLTB flag will be set if a fault is detected. If a frame error is detected when CSB goes high, new command data is ignored, and previous fault data remains latched and available for retrieval during the next valid frame. The FLTB flag will be set if a fault (not a frame error) is detected. CSB MSB LSB 2 3 SCLK 1 4 − 13 14 15 16 SI X Z B15 B15 B14 B14 B13 B13 B12 − B3 B12 − B3 B2 B2 B1 B1 B0 B0 UKN X Z SO Note: X=Don’t Care, Z=Tri−State, UKN=Unknown Data Figure 10. SPI Communication Frame Format http://onsemi.com 11 NCV7513A Serial Data and Register Structure The 16−bit data sent by the NCV7513A is always the encoded 12−bit fault information, with the upper 4 bits forced to zero. The 16−bit data received is decoded into a 4−bit address and a 6−bit data word (see Figure 11). The upper four bits, beginning with the received MSB, are fully decoded to address one of four programmable registers and the lower six bits are decoded into data for the addressed register. Bit B15 must always be set to zero. The valid register addresses are shown in Table 1. Each register is next described in detail. Table 1. Register Address Definitions 4−BIT ADDRESS B15 0 0 0 0 0 A2 0 0 0 0 1 A1 0 0 1 1 X A0 0 1 0 1 X 16−BIT OUTPUT DATA B15 0 B14 0 B13 0 B12 0 B11 D11 12−bit Fault Data B0 D0 D5 D4 6−BIT INPUT DATA D3 Gate Select Disable Mode Refresh & Reference Flag Mask Null D2 D1 D0 MSB LSB B15 B14 B13 B12 B11 B10 0 0 0 0 CH5 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CH4 CH3 CH2 CH1 CH0 CHANNEL FAULT OUTPUT DATA REGISTER SELECT MSB COMMAND INPUT DATA LSB B15 B14 B13 B12 B11 B10 0 A2 A1 A0 X X B9 X B8 X B7 X B6 X B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 D0 Figure 11. SPI Data Format Gate Select – Register 0 Each GATX output is turned on/off by programming its respective GX bit (see Table 2). Setting a bit to 1 causes the selected GATX output to drive its external MOSFET’s gate to VCC2 (ON). Setting a bit to 0 causes the selected GATX output to drive its external MOSFET’s gate to VSS (OFF). Note that the actual state of the output depends on POR, ENAX and shorted load fault states as later defined by Equation 1. At powerup, each bit is set to 0 (all outputs OFF). Table 2. Gate Select Register A2 0 A1 0 A0 0 D5 G5 D4 G4 D3 G3 D2 G2 D1 G1 D0 G0 to 1 causes the selected GATX output to latch−off when a fault is detected. Setting a bit to 0 causes the selected GATX output to auto−retry when a fault is detected. At powerup, each bit is set to 0 (all outputs in auto−retry mode). Table 3. Disable Mode Register A2 0 A1 0 A0 1 D5 M5 D4 M4 D3 M3 D2 M2 D1 M1 D0 M0 0 = AUTO−RETRY 1 = LATCH OFF 0 = GATX OFF 1 = GATX ON Disable Mode – Register 1 The disable mode for shorted load faults is controlled by each channel’s respective MX bit (see Table 3). Setting a bit Refresh and Reference – Register 2 Refresh time (auto−retry mode) and shorted load fault detection references are programmable in two groups of three channels. Refresh time and the fault reference for channels 5−3 is programmed by RX bits 5−3. Refresh time and the fault reference for channels 2−0 is programmed by RX bits 2−0 (see Table 4). At powerup, each bit is set to 0 (VFLT = 25% VFLTREF , tFR = 10 ms). http://onsemi.com 12 NCV7513A Table 4. Refresh and Reference Register A2 0 A1 1 A0 0 D5 R5 X X X X X X 0 1 D4 R4 CHANNELS 5−3 25% VFLTREF 50% VFLTREF 75% VFLTREF VFLTREF tFR = 10 ms tFR = 40 ms tFR = 10 ms tFR = 40 ms 0 0 1 1 X X X X 0 1 0 1 X X X X X X X X 0 1 X X D3 R3 D2 R2 D1 R1 CHANNELS 2−0 0 0 1 1 X X X X 0 1 0 1 X X X X D0 R0 Flag Mask – Register 3 The drain feedback from each channel’s DRNX input is combined with the channel’s KX mask bit (Table 5). When KX = 1, a channel’s mask is cleared and its feedback to the FLTB and STAB flags is enabled. At powerup, each bit is set to 0 (all masks set). Table 5. Flag Mask Register A2 0 A1 1 A0 1 D5 K5 D4 K4 D3 K3 D2 K2 D1 K1 D0 K0 0 = MASK SET 1 = MASK CLEAR The STAB flag is influenced when a mask bit changes CLR→SET after one valid SPI frame. FLTB is influenced after two valid SPI frames. This is correct behavior for FLTB since, while a fault persists, the FLTB will be set when CSB goes LO→HI at the end of an SPI frame. The mask instruction is decoded after CSB goes LO→HI so FLTB will only reflect the mask bit change after the next SPI frame. Both FLTB and STAB require only one valid SPI frame when a mask bit changes SET→CLR. Null Register – Register 4 Fault information is always returned when any register is addressed. The null register (Table 6) provides a way to read back fault information without regard to the content of DX. Table 6. Null Register A2 1 A1 X A0 X D5 X D4 X D3 X D2 X D1 X D0 X Gate Driver Control and Enable Each GATX output may be turned on by either its respective parallel INX input or the internal GX (Gate Select) register bit via SPI communication. The device’s common ENAX enable inputs can be used to implement global control functions, such as system reset, overvoltage or input override by a watchdog controller. Each parallel input and the ENA2 input have individual internal pulldown current sources. The ENA1 input has an internal pulldown resistor. Unused parallel inputs should be connected to GND and unused enable inputs should be connected to VCC1. Parallel input is recommended when low frequency (v2.0 kHz) PWM operation of the outputs is desired. ENA2 disables all GATX outputs when brought low. When ENA1 is brought low, all GATX outputs, the timer clock, and the flags are disabled. The fault and gate registers are cleared and the flags are reset. New serial GX data is ignored while ENA1 is low but other registers can be programmed. When both the ENA1 and ENA2 inputs are high, the outputs will reflect the current parallel or serial input states. This allows ENA1 to be used to perform a soft reset and ENA2 to be used to disable the GATX outputs during initialization of the NCV7513A. The INX input state and the GX register bit data are logically combined with the internal (active low) power−on reset signal (POR), the ENAX input states, and the shorted load state (SHRTX) to control the corresponding GATX output such that: GATX + POR · ENA1 · ENA2 · SHRTx · (INx ) Gx) (eq. 1) http://onsemi.com 13 NCV7513A The GATX state truth table is given in Table 7. Table 7. Gate Driver Truth Table POR 0 1 1 1 1 1 1 1 1 1 1 ENA1 X 0 0 1 1 1 1 1 1→0 1 1 ENA2 X 0 1 0 1 1 1 1 1 1→0 0→1 SHRTX X X X X 1 1 1 0 X X X INX X X X X 0 1 X X X X 0 GX X X X X 0 X 1 X →0 GX GX GATX L L L L L H H L →L →L → GX On−state faults will initiate MOSFET protection behavior, set the FLTB flag and the respective channel’s DX bits in the device’s fault latches. Off−state faults will simply set the FLTB flag and the channel’s DX bits. Fault types are uniquely encoded in a 2−bit per channel format. Fault information for all channels simultaneously is retrieved by SPI read (Figure 11). Table 8 shows the fault−encoding scheme for channel 0. The remaining channels are identically encoded. Table 8. Fault Data Encoding CHANNEL 0 D1 0 0 1 1 D0 0 1 0 1 NO FAULT OPEN LOAD SHORT TO GND SHORTED LOAD STATUS Gate Drivers The non−inverting GATX drivers are symmetrical resistive switches (1.80 kW typ.) to the VCC2 and VSS voltages. While the outputs are designed to provide symmetrical gate drive to an external MOSFET, load current switching symmetry is dependent on the characteristics of the external MOSFET and its load. Figure 12 shows the gate driver block diagram. DX0 DX1 tFR R | R5 2 MX IN X GX ENA1 ENA2 POR ENCODING LOGIC FILTER TIMER BLANKING TIMER FAULT DETECTION 50 DRNX VSS VCC2 DRIVER S LATCH OFF / AUTO RE−TRY _ EN R SHRT X 1800 VSS GAT X Figure 12. Gate Driver Channel Blanking and Filter Timers Blanking timers are used to allow drain feedback to stabilize after a channel is commanded to change states. Filter timers are used to suppress glitches while a channel is in a stable state. A turn−on blanking timer is started when a channel is commanded on. Drain feedback is sampled after tBL(ON). A turn−off blanking timer is started when a channel is commanded off. Drain feedback is sampled after tBL(OFF). A filter timer is started when a channel is in a stable state and a fault detection threshold associated with that state has been crossed. Drain feedback is sampled after tFF. Blanking timers for all channels are started when both ENA1 and ENA2 go high or when either ENAX goes high while the other is high. The blanking time for each channel depends on the commanded state when ENAX goes high. While each channel has independent blanking and filter timers, the parameters for the tBL(ON), tBL(OFF), and tFF times are the same for all channels. Shorted Load Detection An external reference voltage applied to the FLTREF input serves as a common reference for all channels (Figure 13). The FLTREF voltage must be within the range of 0 to VCC1−2.0 V and can be derived via a voltage divider between VCC1 and GND. Shorted load detection thresholds can be programmed via SPI in four 25% increments that are ratiometric to the applied FLTREF voltage. Separate thresholds can be selected for channels 0−2 and for channels 3−5 (Table 4). Fault Diagnostics and Behavior Each channel has independent fault diagnostics and employs blanking and filter timers to suppress false faults. An external MOSFET is monitored for fault conditions by connecting its drain to a channel’s DRNX feedback input through an external series resistor. When either ENA1 or ENA2 is low, diagnostics are disabled. When both ENA1 and ENA2 are high, diagnostics are enabled. Shorted load (or short to VLOAD) faults can be detected when a driver is on. Open load or short to GND faults can be detected when a driver is off. http://onsemi.com 14 NCV7513A A shorted load fault is detected when a channel’s DRNX feedback is greater than its selected fault reference after either the turn−on blanking or the filter has timed out. VCC1 RX1 RX2 FLTREF 0 − 3V VCC1 CHANNELS 0−2 3 2 1 0 + 2X4 DECODER − OA R 75% R 50% R 25% R 3 2 1 0 R1 R0 KELVIN REGISTER 2 BITS R4 R3 2X4 DECODER CHANNELS 3−5 Figure 13. Shorted Load Reference Generator Fault Recovery Refresh Time Refresh time for shorted load faults is SPI programmable to one of two values for channels 0−2 (register bit R2) and for channels 3−5 (register bit R5) via the Refresh and Reference register (Table 4). A global refresh timer with taps at nominally 10 ms and 40 ms is used for auto−retry timing. The first faulted channel triggers the timer and the full refresh period is guaranteed for that channel. An additional faulted channel may initially retry immediately after its turn−on blanking time, but subsequent retries will have the full refresh time period. If all channels in a group (e.g. channels 0−2) become faulted, they will become synchronized to the selected refresh period for that group. If all channels become faulted and are set for the same refresh time, all will become synchronized to the refresh period. Open Load and Short to GND Detection A window comparator with fixed references proportional to VCC1 along with a pair of bias currents is used to detect open load or short to GND faults when a channel is off. Each channel’s DRNX feedback is compared to the references after either the turn−off blanking or the filter has timed out. Figure 14 shows the DRNX bias and fault detection zones. The diagnostics are disabled and the bias currents are turned off when ENAX is low. No fault is detected if the feedback voltage at DRNX is greater than the VOL open load reference. If the feedback is less than the VSG short to GND reference, a short to GND fault is detected. If the feedback is less than VOL and greater than VSG, an open load fault is detected. I DRNX Short to GND Open Load No Fault Shorted Load Fault Recovery Shorted load fault disable mode for each channel is individually SPI programmable via the MX bits in the device’s Disable Mode register (Table 3). When latch−off mode is selected the corresponding GATX output is turned off upon detection of a fault. Fault recovery is initiated by toggling (ON→OFF→ON) the channel’s respective INX parallel input, serial GX bit, or ENA2. When auto−retry mode is selected (default mode) the corresponding GATX output is turned off for the duration of the programmed fault refresh time (tFR) upon detection of a fault. The output is automatically turned back on (if still commanded on) when the refresh time ends. The channel’s DRNX feedback is resampled after the turn−on blanking time. The output will automatically be turned off if a fault is again detected. This behavior will continue for as long as the channel is commanded on and the fault persists. In either mode, a fault may exist at turn−on or may occur some time afterward. To be detected, the fault must exist longer than either tBL(ON) at turn−on or longer than tFF some time after turn−on. The length of time that a MOSFET stays on during a shorted load fault is thus limited to either tBL(ON) or tFF. In auto−retry mode, a persistent shorted load fault will result in a low duty cycle (tFD [ tBL(ON)/tFR) for the affected channel and help prevent thermal failure of the channel’s MOSFET. CAUTION − CONTINUOUS INPUT TOGGLING VIA INX, GX or ENA2 WILL OVERRIDE EITHER DISABLE MODE. Care should be taken to service a shorted load fault quickly when one has been detected. I OL 0 −ISG VSG VCTR VOL VDRNX Figure 14. DRNX Bias and Fault Detection Zones Figure 15 shows the simplified detection circuitry. Bias currents ISG and IOL are applied to a bridge along with bias voltage VCTR (50% VCC1 typ.). http://onsemi.com 15 NCV7513A VCC1 I SG A CMP1 − VOL VLOAD D3 D1 + + 1600 DZ1 50 DRNX RDX +VOS RLOAD VX RSG B CMP2 − D4 D2 VSG VCTR + _ I OL (VCL) Figure 15. Short to GND/Open−Load Detection When a channel is off and VLOAD and RLOAD are present, RSG is absent, and VDRNX >> VCTR, bias current IOL is supplied from VLOAD to ground through external resistors RLOAD and RDX, and through the internal 1650 W resistance and bridge diode D2. Bias current ISG is supplied from VCC1 to VCTR through D3. No fault is detected if the feedback voltage (VLOAD minus the total voltage drop caused by ISG and the resistance in the path) is greater than VOL. When either VLOAD or RLOAD and RSG are absent, the bridge will self−bias so that the voltage at DRNX will settle to about VCTR. An open load fault can be detected since the feedback is between VSG and VOL. Short to GND detection can tolerate up to a 1.0 V offset (VOS) between the NCV7513A’s GND and the short. When RSG is present and VDRNX VOL < VOL < VOL < VOL > VOL VSG