NCV7544MWTXG

NCV7544 FLEXMOSt Quad Half-Bridge MOSFET Pre-driver The NCV7544 programmable four channel half−bridge MOSFET pre−driver is one of a family of FLEXMOS automotive grade products for driving logic−level NMOS FETs. The product is controllable by a combination of serial SPI and CMOS−compatible parallel inputs. An internal power−on reset provides controlled power up. A reset input allows external re−initialization and a failsafe input allows the device to be safely disabled in the event of system upset. Each channel independently monitors its external MOSFETs’ drain−source voltages for fault conditions. Overload detection thresholds are SPI−selectable and the product allows different detection thresholds for each channel. The FLEXMOS family of products offers application scalability through choice of external MOSFETs. www.onsemi.com QFN32 5x5, 0.5P (PUNCHED) CASE 485CZ MARKING DIAGRAM Features • Supports Functional Safety Compliance • 4 Half−bridge Pre−drivers for External Logic−level NMOS FETs • Integrated Charge Pump for: 1 ON NCV7544 AWLYYWW G ♦ • • • • • High−side Gate Drive Switched Reverse Battery Protection 5 V CMOS Compatible I/O: ♦ 16−bit SPI Interface for Control and Diagnosis ♦ Reset and Failsafe Inputs ♦ 2 PWM Control Inputs Programmable: ♦ Slew Rate Control ♦ Overload Protection Thresholds Low Quiescent Current Wettable Flanks Pb−free Packaging NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable ♦ Benefits • Scalable to Load by Choice of External MOSFET © Semiconductor Components Industries, LLC, 2018 October, 2018 − Rev. 0 1 NCV7544 A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device Package Shipping† NCV7544MWTXG QFN−32 (Pb−Free) 5000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NCV7544/D NCV7544 VCC VS CP CPSW CSB C1A SCLK POWER SUPPLY SPI SI CHARGE PUMP SO C1B C2A C2B SFL N/C RSTB FSM NCV7544 PWM1 PWM2 CP GH1 HB1 GL1 SFL SFL LOGIC CORE PDH HB1 PDH HB2 PDL PDL PGND CP SFL GH3 HB3 GL3 CP GH2 HB2 GL2 PGND SFL CP PDH PDH WATCH DOG HB3 HB4 PDL PDL GH4 HB4 GL4 FAILSAFE PGND PGND AGND DGND PGND Figure 1. Block Diagram www.onsemi.com 2 {2018.06.25} NCV7544 REVERSE PROTECT VBAT SECURITY SWITCH VBAT_P WD_EN VS CP CPSW C1A C1B GH1 C2A HB1 OPTIONAL C2B LIMITER VCC GL1 14V 5V M NCV7544 GH2 VCC HB2 CSB GL2 MICROCONTROLLER SCLK M SI SO GH3 RSTB HB3 PWM1 GL3 PWM2 M GH4 WATCHDOG FSM AGND HB4 PGND GL4 DGND A/D 3−5 3−5 mW mW {2018.06.25} Figure 2. Application Diagram www.onsemi.com 3 NCV7544 PACKAGE PIN DESCRIPTION 32 Pin QFN Exposed Pad Package Pin Label Function Description 29 VS Main Power Supply Main high−power device supply (battery) input; VDS sense reference node for the half−bridge high−side drivers. An external ceramic bypass capacitor shall be connected between VS and GND close to the pin. 24 VCC Logic Supply SPI block and internal logic and low power (analog) supply input. An external ceramic bypass capacitor shall be connected between VCC and GND close to the pin. 27 AGND Signal Ground Low power return path; reference for the analog circuitry. 26 DGND Digital Ground Low power return path; reference for the digital circuitry. 31 PGND Power Ground High power return path; reference for the half−bridge drivers; VDS sense reference node for the half−bridge low−side drivers. Charge Pump Switch Node Switching nodes for external ceramic charge pumping capacitors 1 & 2. Charge pump output; an external ceramic buffer capacitor shall be connected between CP and VS to provide stable output voltage during transient noise on VS. 1 C1A 32 C1B 3 C2A 4 C2B 2 CP Charge Pump Output 30 CPSW Charge Pump Switched Output 17 RSTB Wake Input 18 CSB SPI Chip Select 19 SCLK SPI Clock Digital input with pull−down resistor. 20 SI SPI Serial Input Digital input with pull−down resistor. 21 PWM2 PWM Inputs 22 PWM1 Digital inputs with symmetrical adaptive digital de−glitch and pull−down resistor; provide PWM signals to the half−bridge pre−drivers. 23 FSM Fail−safe Input Digital input with symmetrical digital de−glitch and pull−down resistor; the active high fail−safe mode (can be set via an external watchdog circuit). 25 SO SPI Serial Output Digital tri−state output with high−side path protection to prevent VCC back−bias in the event of an external voltage regulator failure or short to VS. 6 GH1 High−side Pre−driver Output High−side pre−drivers with pull−down resistor to HBx switch nodes; gate drive for external logic−level N−MOS FETs. Half−bridge Switch Node Monitoring inputs for external half−bridge switches; high−side MOSFET source node; low−side MOSFET drain node. 9 GH2 12 GH3 15 GH4 7 HB1 10 HB2 13 HB3 16 HB4 5 GL1 Low−side Pre−driver Output 8 GL2 11 GL3 14 GL4 28 N/C No Connection – EP Exposed Pad Switched charge pump output; activates external reverse battery and security power MOSFET switches via SPI. Digital input with falling edge digital de−glitch and pull−down resistor; active low master reset; the device is in wake state when the pin is high. Digital input with pull−up resistor; active low chip select. Low−side pre−drivers with pull−down resistor to PGND; gate drive for external logic−level N−MOS FETs. Unused pin Connect to GND. www.onsemi.com 4 NCV7544 SO DGND AGND N/C VS CPSW PGND C1B Exposed Pad (EP) 32 31 30 29 28 27 26 25 C1A 1 24 VCC CP 2 23 FSM C2A 3 22 PWM1 C2B 4 21 PWM2 GL1 5 20 SI GH1 6 19 SCLK HB1 7 18 CSB GL2 8 17 RSTB NCV7544 9 10 11 12 13 14 15 16 HB4 GH4 GL4 HB3 GH3 GL3 HB2 GH2 {2018.06.25} Figure 3. 32 Pin 5 x 5 mm Exposed Pad Pin−out (Top View) MAXIMUM RATINGS (Except as noted, voltages are with respect to AGND = DGND = PGND = GND.) Rating VS Supply DC: 2 min @ 25°C AC: ISO7637 Pulse 5b, 400 ms @ 25°C VCC Supply Output Voltage: CP, CPSW SO Input Voltage: FSM, C1A, C1B, C2A, C2B Input Voltage (Clamped): Input Voltage: HBx CSB, SCLK, SI, RSTB, PWMx Symbol Value Unit VSMAX −0.3 to 28 40 V VCCMAX −0.3 to 7.0 V V_OUTMAX V_SOMAX −0.3 to 40 −0.3 to 20 V V_INMAX1 −0.3 to 40 V V_INMAX2 −1.0 to 40 V V_INMAX3 −0.3 to 20 V I_INMAX ± 5.0 mA Junction Temperature TJ −40 to 150 °C Storage Temperature TSTG −55 to 150 °C Peak Reflow Soldering Temperature: Lead−free 60 to 150 seconds at 217°C (Note 1) TPK 260 °C Input Current (Clamped): CSB, SCLK, SI, RSTB, FSM, PWMx, GHx, GLx Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. See or download ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D www.onsemi.com 5 NCV7544 ATTRIBUTES Characteristic Symbol Value Unit ESD Capability: Human Body Model per AEC−Q100−002 All pins VS, HBx VESD_HBM Charged Device Model per AEC−Q100−011 All Pins Corner Pins VESD_CDM kV ≥ ± 2.0 ≥ ± 4.0 V ≥ ± 500 ≥ ± 750 Moisture Sensitivity (Note 1) MSL 3 RqJA RqJA RYJPAD 68.0 27.4 1.7 – °C/W Package Thermal Resistance – Still−air, PIN = 1 W (Uniform Power Density) Junction–to–Ambient, RqJA (Note 2) (Note 3) Junction–to–Exposed Pad, RYJPAD 2. 2S0P 2−layer PCB based on JESD51−3, 80 x 80 x 1.6 mm FR4, 20 thermal vias, 1 oz. signal, 1 oz. 400 mm2 bottom spreader. 3. S2P 4−layer PCB based on JESD51−7, 80 x 80 x 1.6 mm FR4, 20 thermal vias, 1 oz. signal, 1 oz. 6400 mm2 internal spreaders. RECOMMENDED OPERATING CONDITIONS Parameter Main Power Supply Voltage Logic Power Supply Voltage Symbol Min Max Unit VSOP 7.0 18.0 V VCCOP 4.5 5.5 V Logic High Input Voltage VIN_HIGH 3.5 VCCOP V Logic Low Input Voltage VIN_LOW 0 1.5 V fPWM – 25 kHz Half−bridge Output PWM Rate Charge Pump Capacitors (C1, C2, CCP) − 220 4700 nF SPI Clock Frequency fSCLK 0.1 2.5 MHz Startup Delay at VCC Power−On Reset (POR) (Note 4) tRESET – 200 ms TA −40 125 °C Ambient Still−Air Operating Temperature Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 4. Minimum wait time until device is ready to accept serial input data. www.onsemi.com 6 NCV7544 PARAMETRIC TABLES ELECTRICAL CHARACTERISTICS (4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ TJ ≤ 150°C, unless otherwise specified.) (Note 5) Characteristic Symbol Conditions Min Typ Max Unit – – 5.0 mA 0.9 5.0 mA VS Supply Standby Current IVS_SBY VS = 12.0V, 0 v VCC v 5.5 V, RSTB = 0, TA = 25°C IVS_OP0 VCC = 5.0 V , RSTB = 1, TA = 25 °C Default Settings at POR, SPI Inactive CR1.D[10]=0 – IVS_OP1 CR1.D[10]=1 – 13.4 25.0 mA VSUVLO VS decreasing, SR0.D[5] ³ 1 4.5 5.0 5.5 V Under−voltage Hysteresis VSUVHY SR0.D[5] ³ 0 (after read status if VS > VSUVLO+UVHY) 100 200 – mV Under−voltage Filter Time tUVDGL VS decreasing 4.0 5.0 6.0 ms VSOVSDR VS increasing, SR0.D[4] ³ 1 19.0 20.0 21.0 V VSOVSDF VS decreasing, SR0.D[4] ³ 0 18.0 19.0 20.0 V Over−voltage Hysteresis VSOVHY SR0.D[4] ³ 0 (after read status if VS < VSOV – OVHY) – 0.9 – V Over−voltage Filter Time tOVDGL VS increasing 4.0 5.0 6.0 ms VS PWM Threshold VSPWM VS decreasing, SR0.D[7] ³ 1 8.90 9.45 10.0 V SR0.D[7] ³ 0 and/or SR0.D[6] ³ 0 VSPWM_HY (after read status if VS > VSPWM +PWM_HY) − 100 – mV Operating Current Under−voltage Lockout Over−voltage Shutdown VS PWM Hysteresis VCC Supply Standby Current IVCC_SBY VS = 12.0V, VCC = 5.5 V , RSTB = 0, TA = 25 °C Default Settings at POR, SPI Inactive – – 5.0 mA Operating Current IVCC_OP VS = 12.0V, RSTB = 1, TA = 25 °C – 8.0 12.0 mA VCCPORR VCC Increasing 3.71 4.10 4.49 V VCCPORF VCC Decreasing 3.50 3.85 4.20 V Power−On Reset Threshold Charge Pump C1 = C2 = 470 nF; CCP = 1000 nF Switching Frequency Regulation Voltage Startup Delay Dropout Voltage Charge Pump Low Detection fCP Single−stage, complementary−phase topology 1.04 1.25 1.56 MHz CPREG V(CP, VS), VS > VSPWM, 0 v I(CP) v 10 mA 8.3 8.9 9.5 V CPDLY VS = 13V, I(CP) = no load C1 = C2 = 470 nF, CCP = 1000 nF – – 500 ms CPDROP0 V(VS) − V(CP, VS), I(CP) = 10 mA, VS=9.4 – – 1.50 V(VS) − V(CP, VS), I(CP) = 10 mA, VS=10V and SR0.D[7] = 0 TJ w 125 °C – – 1.75 CPDROP1 – – 1.90 CPLOW0 V(CP, VS) decreasing, VS > VSPWM, SR0.D[7] ³ 1 7.3 8.0 8.8 V CPLOW1 Detection margin, CPLOW1 = CPREG − CPLOW0 300 – – mV 120 150 180 ms – 100 – mV 4.925 5.375 5.750 V 120 150 180 ms – 100 – mV Charge Pump Low Detection Filter Time tCPL_DGL Charge Pump Low Hysteresis CPLOW_HY Charge Pump Fail Detection CPFAIL Charge Pump Fail Detection Filter Time tCPF_DGL Charge Pump Fail Hysteresis CPFAIL_HY (Note 6.) SR0.D[7] ³ 0 (after read status if V(CP,VS) > CPLOW+LOW_HY) V(CP, VS) decreasing, SR0.D[6] ³ 1 SR0.D[6] ³ 0 (after read status if V(CP,VS) > CPFAIL+FAIL_HY) www.onsemi.com 7 V NCV7544 ELECTRICAL CHARACTERISTICS (4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ TJ ≤ 150°C, unless otherwise specified.) (Note 5) Characteristic Symbol Charge Pump Over−voltage Detection CPOV Charge Pump Over−voltage Hysteresis CPOV_HYS CP Switch Resistance RCPTOT Conditions VS increasing *Guaranteed by Simulation* 8x CP switches in parallel, TA = 25°C Switched CP Output Resistance RCPSW_ON CR1.D[9] = 1, I(CPSW) = 5 mA Switched CP Output Leakage CPSW_LKG CR1.D[9] = 0 Min Typ Max Unit 28.0 30.25 32.5 V 0.5 1.0 2.0 V – 1.5 – W – – 100 W −1.0 0 1.0 uA Digital I/O VIN_X High VINHX CSB, SCLK, SI, RSTB, FSM, PWMx 3.5 – – V VIN_X Low VINLX CSB, SCLK, SI, RSTB, FSM, PWMx – – 1.5 V Input Pull−down Resistance RPDX SCLK, SI, RSTB, FSM, PWMx, VINX = VCC 70 100 130 kW Input Pull−up Resistance RPU CSB, VIN = 0V 70 100 130 kW Input Current IINX VINX = 5.5V: SCLK, SI, RSTB, FSM, PWMx VINX = 0V: CSB – −80 0 80 – mA Input Leakage IIN_LKG VINX = 0V: SCLK, SI, RSTB, FSM, PWMx VINX = VCC: CSB −1.0 0 1.0 mA Input Filter Time tIN_DGL FSM input 8.0 10 12 ms Minimum RSTB pulse (H ³ L ³ H) detected 8.0 – – ms – 11 15 ms Reset De−glitch Time tRST_DGL Reset Assert Time tWRST Minimum RSTB hold after H ³ L transition SO Low Voltage VSOL ISINK = 1.0 mA SO High Voltage SO Tri−State Leakage Current VSOH SOLKG ISOURCE = 1.0 mA CSB = VCC, SO = VCC/2 – – 0.4 V VCC – 0.4 – – V −1.0 – 1.0 mA Serial Peripheral Interface (See Figure 4) VCC = 5.0V, FSCLK = 2.5 MHz, CLOAD = 80 pF, all timing is at 30% and 70% VCC unless otherwise specified. SCLK Clock Period tSCLK 400 – – ns SCLK High Time tCLKH SCLK Low Time tCLKL SCLK = 70% VCC to 70% VCC 200 – – ns SCLK = 30% VCC to 30% VCC 200 – – ns Maximum Input Capacitance CINX SCLK, Sl (Note 6) – – 15 pF Sl Setup Time tSISU Sl Hold Time tSIHD Sl = 30%|70% to SCLK = 70% VCC (Note 6) 25 – – ns SCLK = 30% to Sl = 30%|70% VCC (Note 6) 25 – – ns SO Rise Time SO Fall Time tSOR (20% VSO to 80% VCC) (Note 6) – 25 50 ns tSOF (80% VSO to 20% VCC) (Note 6) – – 50 ns CSB Setup Time tCSBSU CSB = 30% to SCLK = 30% VCC (Note 6) 60 – – ns CSB Hold Time tCSBHD SCLK = 30% to CSB = 70% VCC (Note 6) 75 – – ns – 65 125 ns CSB to SO Assert Time tSO_A CSB = 30% VCC to SO = 30%|70% VCC RLOAD = 5 kW (Note 6) CSB to SO Release Time tSO_R CSB = 70% VCC to SO = 20%|80% VCC/2 RLOAD = 5 kW (Note 6) – – 350 ns SO Delay Time SODLY SCLK = 70% VCC to SO = 30%|70% (Note 6) – 65 125 ns Transfer Delay Time CSDLY CSB rising edge to next falling edge. (Note 6) – – 1.0 ms 20 400 25 500 30 600 ms – 40 – MHz Watchdog Timer Watchdog Timeout tWD Core Clock Oscillator CR1.D[8] = 0 CR1.D[8] = 1 fCORE www.onsemi.com 8 NCV7544 ELECTRICAL CHARACTERISTICS (4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ TJ ≤ 150°C, unless otherwise specified.) (Note 5) Characteristic Symbol Conditions Min Typ Max Unit Half−Bridge Pre−Driver Outputs VS > VSPWM On−state Drive Voltage VPDHX High−side, VPDHX = H = V(GHx, HBx), No External Load 8.3 – 9.5 V VPDLX Low−side, VPDLX = H =V(GLx, PGND), No External Load 8.1 – 9.8 V High−side driver Gate−source Clamp Positive Voltage VGSX_CLPH V(GHx, HBx), ICLMP = 3.0 mA 14.0 – 18.0 V High−side driver Source−gate Clamp Negative Voltage VSGX_CLPH V(HBx, GHx), ICLMP = −2.0 mA −20.0 – −16.0 V Low−side driver Gate−source Clamp Positive Voltage VGSX_CLPL V(GLx, PGND), ICLMP = 10 mA 11.5 – 15.0 V Low−side driver Gate−source Clamp Negative Voltage VGSX_CLN V(GLx, PGND), ICLMP = −1.0 mA −1.0 – – V Gate Drive Timeout tTIMEOUT IGHx v IGHx_SS Gate Drive Timeout Current IGHx_SS V(GHx, HBx) = 0 V , t > tTIMEOUT 16 20 24 ms −1.2 −1.0 −0.8 mA 70 – 130 kW BLANKx[1:0] = 0x00 0.8 1.0 1.2 BLANKx[1:0] = 0x01 1.6 2.0 2.4 BLANKx[1:0] = 0x02 2.4 3.0 3.6 BLANKx[1:0] = 0x03 3.2 4.0 4.8 T_PCx[1:0] = 0x00 80 100 120 T_PCx[1:0] = 0x01 160 200 240 T_PCx[1:0] = 0x02 240 300 360 T_PCx[1:0] = 0x03 320 400 480 High−side Pre−charge Current GHx Rising Slope I_PCRx[2:0] = 0x00 1.23 1.50 1.77 I_PCRx[2:0] = 0x01 4.52 5.25 5.99 V(GHx) = 3.5 V I_PCRx[2:0] = 0x02 7.42 8.63 9.84 I_PCRx[2:0] = 0x03 10.65 12.38 14.11 I_PCRx[2:0] = 0x04 14.19 16.50 18.81 I_PCRx[2:0] = 0x05 17.42 20.25 23.09 I_PCRx[2:0] = 0x06 20.64 24.00 27.36 I_PCRx[2:0] = 0x07 24.19 28.13 32.07 High−side Pre−charge Current GHx Falling Slope I_PCFx[2:0] = 0x00 24.84 28.88 32.92 I_PCFx[2:0] = 0x01 30.64 35.63 40.62 V(GHx) = (VS + 3.5) V I_PCFx[2:0] = 0x02 36.12 42.00 47.88 I_PCFx[2:0] = 0x03 41.61 48.38 55.15 I_PCFx[2:0] = 0x04 47.41 55.13 62.85 I_PCFx[2:0] = 0x05 52.89 61.50 70.11 I_PCFx[2:0] = 0x06 58.38 67.88 77.38 I_PCFx[2:0] = 0x07 64.18 74.63 85.08 Gate−source Pull−down Resistor RGSX Cross Conduction Blank Time tBLANKX GHx, GLx R(GHx, HBx), R(GLx, PGND) ms Pre−Driver Slope Control VS > VSPWM High−side Pre−charge Time GHx Rising and Falling Slope tPRCX IPRCX_R IPRCX_F www.onsemi.com 9 ns mA mA NCV7544 ELECTRICAL CHARACTERISTICS (4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ TJ ≤ 150°C, unless otherwise specified.) (Note 5) Conditions Min Typ Max High−side Slew Current GHx Rising and Falling Slope Characteristic Symbol SR_CTRLx[2:0] = 0x00 1.23 1.50 1.77 SR_CTRLx[2:0] = 0x01 1.94 2.25 2.57 Rising: V(GHx) = (VS + 3.5) V Falling: V(GHx) = 3.5 V SR_CTRLx[2:0] = 0x02 2.91 3.38 3.85 SR_CTRLx[2:0] = 0x03 4.52 5.25 5.99 SR_CTRLx[2:0] = 0x04 6.78 7.88 8.98 SR_CTRLx[2:0] = 0x05 10.00 11.63 13.26 SR_CTRLx[2:0] = 0x06 14.84 17.25 19.67 ISRX SR_CTRLx[2:0] = 0x07 21.93 25.50 29.07 Low−side Drive Current GLx Rising and Falling slope SR_CTRLx[2:0] = 0x00 5.16 6.00 6.84 SR_CTRLx[2:0] = 0x01 7.74 9.00 10.26 V(GLx) = 3.5 V SR_CTRLx[2:0] = 0x02 11.63 13.52 15.41 SR_CTRLx[2:0] = 0x03 18.06 21.00 23.94 SR_CTRLx[2:0] = 0x04 27.11 31.52 35.93 SR_CTRLx[2:0] = 0x05 40.01 46.52 53.03 SR_CTRLx[2:0] = 0x06 59.34 69.00 78.66 SR_CTRLx[2:0] = 0x07 87.72 102.00 116.28 ILSX Unit mA mA Slope Control Calibration Unit Slope Calibration Comparator Window Thresholds VCALF_L Falling slope window lower threshold 3.0 5.0 7.0 VCALF_U Falling slope window upper threshold 13 15 17 VCALR_L Rising slope window lower threshold 82 85 88 VCALR_U Rising slope window upper threshold 92 95 98 – 62 100 ns – 50 – ns (Note 7) ns Comparator Propagation Delay tCAL_PD Sample Synchronization Delay tSYNC Calibration Pre−charge Time HBx Rising & Falling Slope tSYNC = 2/fCORE CAL_PC[3:0] = 0x00 50 CAL_PC[3:0] = 0x01 150 CAL_PC[3:0] = 0x02 250 CAL_PC[3:0] = 0x03 350 CAL_PC[3:0] = 0x04 450 CAL_PC[3:0] = 0x05 550 CAL_PC[3:0] = 0x06 650 CAL_PC[3:0] = 0x07 tCAL_PCx CAL_PC[3:0] = 0x08 750 (Note 7) 850 CAL_PC[3:0] = 0x09 950 CAL_PC[3:0] = 0x0A 1050 CAL_PC[3:0] = 0x0B 1150 CAL_PC[3:0] = 0x0C 1250 CAL_PC[3:0] = 0x0D 1350 CAL_PC[3:0] = 0x0E 1450 CAL_PC[3:0] = 0x0F 1550 www.onsemi.com 10 % VS NCV7544 ELECTRICAL CHARACTERISTICS (4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ TJ ≤ 150°C, unless otherwise specified.) (Note 5) Characteristic Symbol Calibration Delay Time HBx Rising & Falling Slope Conditions Min CAL_DLY[3:0] = 0x00 0.35 CAL_DLY[3:0] = 0x01 0.55 CAL_DLY[3:0] = 0x02 0.75 CAL_DLY[3:0] = 0x03 0.95 CAL_DLY[3:0] = 0x04 1.15 CAL_DLY[3:0] = 0x05 1.35 CAL_DLY[3:0] = 0x06 1.55 CAL_DLY[3:0] = 0x07 tCAL_DLYx Typ CAL_DLY[3:0] = 0x08 Max Unit (Note 7) ms 1.75 (Note 7) 1.95 CAL_DLY[3:0] = 0x09 2.15 CAL_DLY[3:0] = 0x0A 2.35 CAL_DLY[3:0] = 0x0B 2.55 CAL_DLY[3:0] = 0x0C 2.75 CAL_DLY[3:0] = 0x0D 2.95 CAL_DLY[3:0] = 0x0E 3.15 CAL_DLY[3:0] = 0x0F 3.35 Half−Bridge Diagnostics Static VDS Monitor Thresholds VDS = V(VS, HBx) − or− VDSTHR_S VDS = V(HBx, GND) VDSx[2:0] = 0x00 267 300 333 VDSx[2:0] = 0x01 356 400 444 VDSx[2:0] = 0x02 445 500 555 VDSx[2:0] = 0x03 534 600 666 VDSx[2:0] = 0x04 623 700 777 VDSx[2:0] = 0x05 712 800 888 VDSx[2:0] = 0x06 801 900 999 VDSx[2:0] = 0x07 890 1000 1110 mV Static VDS Monitor Filter Time tDGL_STAT 0.92 1.15 1.38 ms Static VDS Monitor Propagation Delay tVDSS_PD – 550 750 ns VDSTHR_R 77.0 80.0 83.0 % VS VDSTHR_F 17.0 20.0 23.0 % VS Dynamic VDS Monitor Thresholds www.onsemi.com 11 NCV7544 ELECTRICAL CHARACTERISTICS (4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ TJ ≤ 150°C, unless otherwise specified.) (Note 5) Characteristic Symbol Conditions Min Typ Dynamic VDS Detection Delay Time T_DLYX[3:0] = 0x00 0.35 T_DLYX[3:0] = 0x01 0.55 Rising or Falling Slope T_DLYX[3:0] = 0x02 0.75 T_DLYX[3:0] = 0x03 0.95 T_DLYX[3:0] = 0x04 1.15 T_DLYX[3:0] = 0x05 1.35 T_DLYX[3:0] = 0x06 1.55 T_DLYX[3:0] = 0x07 tDLYX T_DLYX[3:0] = 0x08 Max Unit (Note 7) ms 1.75 (Note 7) 1.95 T_DLYX[3:0] = 0x09 2.15 T_DLYX[3:0] = 0x0A 2.35 T_DLYX[3:0] = 0x0B 2.55 T_DLYX[3:0] = 0x0C 2.75 T_DLYX[3:0] = 0x0D 2.95 T_DLYX[3:0] = 0x0E 3.15 T_DLYX[3:0] = 0x0F 3.35 Dynamic VDS Monitor Filter Time tDGL_DYN 231 330 429 ns Dynamic VDS Monitor Propagation Delay tVDSD_PD – 59 100 ns HBx Monitor Threshold VHBTHR 45 50 55 % VS HBx Monitor Propagation Delay tHBX_PD – 1.0 2.0 ms ± 6.0 ± 7.5 ± 9.0 mA HBx Monitor Test Currents ITST CR0.HB_ENx = 0, HB1, HB3 source or sink, 10V v VS v 16V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Min/Max values are valid for the stated temperature range unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation 6. No production test 7. These values, measured in production via test mode, result in values that are tSYNC longer than the stated values. The specification limits shall therefore be: (tCAL_PCx Typ + tSYNC Typ) ±20%, (tCAL_DLYx Typ + tSYNC Typ) ±20%, and (tDLYX Typ + tSYNC Typ) ±20%. www.onsemi.com 12 NCV7544 TRANSFER DELAY CSB SETUP CSB 70% 30% SCLK PERIOD SCLK SCLK HIGH LOW 70% SCLK 1 16 30% SI SETUP SI X 70% SI HOLD MSB IN 30% CSB to SO ASSERT SO CSB HOLD 70% 30% X BITS 14...1 SO DELAY BITS 14...1 MSB OUT LSB IN SO RISE,FALL LSB OUT CSB to SO RELEASE 80% 20% {05/20/16} Figure 4. SPI Timing www.onsemi.com 13 NCV7544 DETAILED OPERATING DESCRIPTION Power Supply • • • Table 1 gives suggested values for the external pump and buffer capacitors to support the charge pump DC loading while maintaining good transient response and regulation stability. The power supply block provides: all internal supply and reference voltages; all internal bias and reference currents; VCC power−on reset (POR) and VS under/over−voltage lockout signals. Table 1. SUGGESTED CHARGE PUMP CAPACITORS The analog and power portions of the device (reference voltages/currents, charge pump, low−side gate drivers, etc.) are supplied from the VS terminal. Each of the low−side gate driver outputs (GLx) is supplied from VS via an individual buffer (source follower) with voltage limit functionality. The high−side gate driver outputs (GHx) are supplied from a regulated charge pump. The logic core and the SPI communication interface are supplied from the VCC terminal in order to achieve a high frequency operation by use of external bypass capacitors. In case of breakdown of the external voltage regulator, the device can be protected by use of an external voltage limiter, which must limit the maximum voltage at the VCC terminal to VCCMAX (see § MAXIMUM RATINGS). The outputs are disabled during device initialization at power−up via an interlock between VS and VCC and such that no control is available until after VCC > VCCPORR (see § Electrical Characteristics: VCC Supply). Reverse battery protection for VS and the VCC regulator is provided externally by the application (see Figure 2). The device is initialized at power−up into a reduced power state (CR1.DRV_EN = 0, see § SPI Control Set): • the charge pump is disabled; • all gate drive currents are disabled; • gate pull−down structures are enabled; • HBx diagnostic test currents are available (see § OFF−state Monitoring of Half−bridge Drivers). DC Load (mA) Pump Capacitors C1, C2 (nF) Buffer Capacitor CCP (nF) 1.0 100 220 7.5 220 470 15.0 470 1000 The device is initialized at power−up into a reduced power state and the charge pump disabled. The charge pump is controlled by SPI command via the CR1.DRV_EN bit (see Table 7) and the charge pump is: • disabled when CR1.DRV_EN=0; • enabled when CR1.DRV_EN=1. The optional external reverse protection and security switches are connected to the charge pump buffer capacitor through the switched charge pump (CPSW) output. The output is controlled by SPI command via the CR1.CP_SW bit (see Table 7). The CPSW output is: • disabled (the reverse and security MOSFETs are turned OFF) when CR1.CP_SW=0; • enabled (the reverse and security MOSFETs are turned ON) when CR1.CP_SW=1. The charge pump is internally monitored to ensure safe operation of the charge pump circuit and the high−side driver outputs (see § Protection and Diagnosis − Charge Pump Monitoring). Due to the single stage configuration the charge pump provides the following output characteristics (see Figure 5, Figure 6, § SPI Diagnosis Set and § Electrical Characteristics: Charge Pump): • V(CP, VS) < CPFAIL SR0.CPF → 1 the GHx and GLx outputs are shut down to prevent damage to the external power MOSFETs; • VS < VSPWM SR0.CPL → 1 the CP output voltage follows the VS voltage (the regulation saturates) with a maximum drop voltage per the equation V(CP, VS) = VS − CPDROP ; • CPFAIL < V(CP, VS) < CPLOW SR0.CPL → 1 • VSPWM ≤ VS ≤ VSOVSDR the charge pump delivers a regulated output voltage V(CP, VS) = CPREG and PWM operation of the GHx outputs is allowed; The device is placed into a full power state when CR1.DRV_EN = 1. Multiple GND pins are used in order to avoid loss of GND due to a single−point failure, to improve ESD capability, and to improve the VDS overload protection performance of the device. Charge Pump A regulated charge pump circuit in single−stage / complementary−phase configuration is implemented. The charge pump is sized to drive up 2 high−side drivers in PWM operation (fPWM ≤ 25 kHz). The topology utilizes 2 external pump capacitors and an external buffer capacitor (see Figure 2) to supply: • the high−side gate driver outputs (GHx); • an optional external reverse protection power MOSFET; • an optional external security switch power MOSFET. www.onsemi.com 14 NCV7544 • VSOVSDF < VS < VS(CPOV) • In the case of VS overvoltage, the charge pump automatically resumes normal operation when the VS voltage returns to below CPOV − CPOV_HYS. In the case of VS < VSPWM or V(CP, VS) < CPLOW it should be considered for the microcontroller to adopt a PWM duty ratio management schema in order to minimize charge pump loading while ensuring smooth motor operation. the charge pump including the CPSW output is functional, but the GHx outputs are shut down; VS > VS(CPOV) the charge pump is disabled and the charge pump buffer capacitor is discharged to VS in order to protect the device from destruction. V(CP, VS) ÍÍÍÍÍÍÍÍÍ CPREG CPLOW CP In Regulation (MIN) CP Low OR VS < VSPWM ÍÍÍÍÍÍÍÍÍÍÍÍ SR0.D[7] → 1 CPFAIL (MIN) CP Fail GHx → L GLx → L SR0.D[6] → 1 V(VS) CPDROP VSPWM VSOVSD (MAX) (MIN) {02/16/2018} Figure 5. Charge Pump Characteristics V Load Dump Rise Time (per ISO7637 Pulse 5b) V(VS MAX ) V(CP OV ) CP REG V(CP) CP REG V(VS) t CP Oscillator Stopped Buffer Cap Discharged to VS Figure 6. Charge Pump Overvoltage Behavior www.onsemi.com 15 {04/07/2014} NCV7544 SPI Interface Watchdog Timer) in order to facilitate module boot loader programming. The timeout setting is controlled by the CR1.WD_CFG bit: • when CR1.WD_CFG=0 (default setting) the WD timeout is tWD = 25 ms; • when CR1.WD_CFG=1 the WD timeout is tWD = 500 ms. A full−duplex synchronous serial data transfer interface (SPI) is used to control the device and provide diagnosis during normal operation. Daisy chain capability of the interface is implemented in order to minimize circuit expenditure and communication efforts. The SPI protocol utilizes 16−bit data words (B15 = MSB). The idle state of SCLK is low and the SI data must be stable before the falling edge of SCLK (“legacy mode 1”: CPOL=0, CPHA=1). The interface consists of 4 I/O lines with 5V CMOS logic levels and termination resistors (see Figure 7, Figure 2): • the active−low CSB enables the SPI interface; • the SCLK pin clocks the internal shift registers of the device; • the SI pin receives data of the input shift registers MSB first; • the SO pin sends data of the output shift registers MSB first. The first WD bit value sent after VCC POR or wake−up must be WD = 0 in the first frame, then WD = 1 in the next. A correct communication is reported when bit SR0.SPIF = 0 and the device is in NORMAL MODE (NM) when bit SRx.NM = 1. The device enters FAILSAFE MODE immediately in the event of an SPI communication error (see § Operating Modes). Serial Data and SPI Register Structures The input and output message formats of the implemented SPI protocol are as shown in the following tables. In the descriptions in the following sections, it is implied that the frame length is correct and that the WD bit has been properly toggled when sending and receiving SPI messages. Please also note that the SPI hardware protocol is a “frame−behind” response type, i.e. the requested data is delivered in the next frame. The device offers the following SPI communication error checks in order to protect the application from unintended motor activation: • protocol length error (modulo 16); • no edges on SCLK during a CSB period; • an undefined SPI command (not used bits must be set to logic 0); • watchdog (WD) toggle (the internal watchdog bit (CRx.WD) must be toggled with each SPI message); • WD timeout (the WD bit must be toggled before the internal watchdog timeout is reached). SPI Control Set The first 4 bits (D15 ... D12) serve as address bits, while 12 bits (D11 ... D0) are used as data bits. The D11 bit is the WD toggle bit: A SPI fail is detected if the bit is not toggled within the WD timeout. The D10 bit may be used as an extended address in some messages. All Control Register (CRx) bits are initialized to logic 0 after a reset. The predefined value is off / inactive unless otherwise noted. The SPI control set (input data map) and input data structure prototype are shown in the following tables. An SI pin stuck−at condition during a CSB period is detected by a WD toggle error. A VCC under−voltage condition is directly blocking the complete SPI functionality via the VCCPORF signal. The length of the watchdog timeout is SPI programmable (see § SPI Control Set and § Electrical Characteristics: TOGGLE CSB SAMPLE SCLK SI 1 X 2 B15 4 − 13 3 B14 B13 14 B12 − B3 15 B2 16 B1 MSB Z SO X B15 B0 LSB B14 B12 − B3 B13 B2 Note: SPI Legacy Mode 1; X=Don’t Care, Z=Tri−State Figure 7. SPI Communication Frame Format www.onsemi.com 16 B1 B0 Z NCV7544 Table 2. SPI INPUT DATA FORMAT Command Input Message Format MSB LSB B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A3 A2 A1 A0 WD D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 4−bit REGISTER ADDRESS WATCH DOG 11−bit INPUT DATA Table 3. INPUT DATA STRUCTURE PROTOTYPE Input Data Prototype CRx WD D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ? ? ? ? ? ? ? ? ? ? ? ? Table 4. SPI INPUT REGISTER DEFINITIONS Defined Command Input Registers (CRx) NOTE: D15 D14 D13 D12 D11 D10 Register Name Alias A3 A2 A1 A0 WD D10 Status Output Mode & HBx Enable CR0 0 0 0 0 D10 HBx Mode CR1 0 0 0 1 D10 HBx PWM Control CR2 0 0 1 0 0 HBx PWM Mode CR3 0 0 1 1 0 HBx Calibration Control CR4 0 1 0 0 D10 HB1 Configuration A CR5A 0 1 0 1 HB1 Configuration B CR5B HB2 Configuration A CR6A HB2 Configuration B CR6B HB3 Configuration A CR7A HB3 Configuration B CR7B HB4 Configuration A CR8A HB4 Configuration B CR8B 0 WD 0 1 1 1 0 0 1 0 1 1 0 1 1 1 0 0 0 0 1 Not Used CR9 1 0 0 1 X Not Used CR10 1 0 1 0 X Not Used CR11 1 0 1 1 X HBx Diagnosis CR12 1 1 0 0 0 Not Used CR13 1 1 0 1 0 HBx PWM De−glitch CR14 1 1 1 0 0 Test Mode CR15 1 1 1 1 D10 Half−bridge gate drive settings must only be changed when HBx is in tri−state (HB_ENx = 0); Gate drive pre−charge time settings must only be changed in single increments (i.e. 00 to 01, 01 to 10 etc.). Table 5. CR0: STATUS OUTPUT MODE & HBx ENABLE REGISTER CR0 WD D10 WD SRA_MODE D9 D8 SRA[2:0] D7 D6 D5 D4 X X X www.onsemi.com 17 D3 D2 D1 HB_EN4 … HB_EN1 D0 NCV7544 Table 6. CR0 INSTRUCTION DEFINITIONS Mnemonic Value Comment 0 The Status Register Address selected via CR0.SRA [2:0] will be used for a single read command. The address always points to SR0 after the read (default state). 1 The Status Register Address selected via SRA [2:0] will be used for the next and all further read commands until a new address is selected. SRA_MODE SRA[2:0] HB_ENx 000 SR0 data is returned in the next frame (default state). 001 SR1 data is returned in the next frame. 010 SR2 data is returned in the next frame. 011 SR3 data is returned in the next frame. 100 SR4 data is returned in the next frame. 101 SR5 data is returned in the next frame. 110 SR6 data is returned in the next frame. 111 SR7 data is returned in the next frame. 0 HBx output disabled (default state). 1 HBx output enabled. Table 7. CR1: HBx MODE CONTROL REGISTER WD D10 D9 D8 D7 D6 D5 D4 WD DRV_EN CP_SW WD_CFG X X X X CR1 D3 D2 D1 D0 HB_MODE4 … HB_MODE1 Table 8. CR1 INSTRUCTION DEFINITIONS Mnemonic Value DRV_EN CP_SW WD_CFG HB_MODEx Comment 0 Charge pump and gate drive currents are disabled (default state). 1 Charge pump and gate drive currents are enabled. 0 Charge pump switched output is OFF: CPSW = Hi−Z (default state). 1 Charge pump switched output is ON: CPSW = V(CP−VS). 0 Watch dog timeout = 25 ms (default state). 1 Watch dog timeout = 500 ms. 0 Low−side pre−driver active (default state). 1 High−side pre−driver active. Table 9. CR2: HBx PWM CONTROL REGISTER WD D10 D9 D8 D7 D6 D5 D4 D3 CR2 WD 0 0 0 0 X X D2 D1 D0 HB_PWM4 … HB_PWM1 X Table 10. CR2 INSTRUCTION DEFINITIONS Mnemonic HB_PWMx Value Comment 0 Output is in 100% ON mode (default). 1 Output is in PWM mode. Table 11. CR3: HBx PWM MODE CONTROL REGISTER CR3 WD D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 WD X X X X PWM40 X PWM30 X PWM20 X PWM10 www.onsemi.com 18 NCV7544 Table 12. CR3 INSTRUCTION DEFINITIONS Mnemonic PWMx0 Value Comment 0 Output PWM source is input PWM1 (default). 1 Output PWM source is input PWM2. Table 13. CR4: HBx CALIBRATION CONTROL REGISTER WD CR4 D10 D9 WD D8 D7 D6 CAL_DLY[3:0] D5 D4 CAL_PC[3:0] Table 14. CR4 INSTRUCTION DEFINITIONS Mnemonic Value Comment CAL_DLY[3:0] 0000 Delay time: end of rising|falling slope 0.35 ms (default). 0001 Delay time: end of rising|falling slope 0.55 ms. 0010 Delay time: end of rising|falling slope 0.75 ms. 0011 Delay time: end of rising|falling slope 0.95 ms. 0100 Delay time: end of rising|falling slope 1.15 ms. 0101 Delay time: end of rising|falling slope 1.35 ms. 0110 Delay time: end of rising|falling slope 1.55 ms. 0111 Delay time: end of rising|falling slope 1.75 ms. 1000 Delay time: end of rising|falling slope 1.95 ms. 1001 Delay time: end of rising|falling slope 2.15 ms. 1010 Delay time: end of rising|falling slope 2.35 ms. 1011 Delay time: end of rising|falling slope 2.55 ms. 1100 Delay time: end of rising|falling slope 2.75 ms. 1101 Delay time: end of rising|falling slope 2.95 ms. 1110 Delay time: end of rising|falling slope 3.15 ms. 1111 Delay time: end of rising|falling slope 3.35 ms. 0000 Pre−charge time: start of rising|falling slope 50 ns (default). 0001 Pre−charge time: start of rising|falling slope 150 ns. 0010 Pre−charge time: start of rising|falling slope 250 ns. CAL_PC[3:0] 0011 Pre−charge time: start of rising|falling slope 350 ns. 0100 Pre−charge time: start of rising|falling slope 450 ns. 0101 Pre−charge time: start of rising|falling slope 550 ns. 0110 Pre−charge time: start of rising|falling slope 650 ns. 0111 Pre−charge time: start of rising|falling slope 750 ns. 1000 Pre−charge time: start of rising|falling slope 850 ns. 1001 Pre−charge time: start of rising|falling slope 950 ns. 1010 Pre−charge time: start of rising|falling slope 1050 ns. 1011 Pre−charge time: start of rising|falling slope 1150 ns. 1100 Pre−charge time: start of rising|falling slope 1250 ns. 1101 Pre−charge time: start of rising|falling slope 1350 ns. 1110 Pre−charge time: start of rising|falling slope 1450 ns. 1111 Pre−charge time: start of rising|falling slope 1550 ns. www.onsemi.com 19 D3 D2 D1 CAL_SEL[2:0] D0 NCV7544 Table 14. CR4 INSTRUCTION DEFINITIONS Mnemonic Value Comment CAL_SEL[2:0] 000 Calibration unit disabled (default). 001 Select output HB1. 010 Select output HB2. 011 Select output HB3. 100 Select output HB4. 101 Calibration unit disabled 110 Calibration unit disabled 111 Calibration unit disabled Table 15. CR5A − CR8A: HBx CONFIGURATION A REGISTER CR5A – CR8A WD D10 WD 0 D9 D8 D7 BLANKx[1:0] D6 D5 D4 I_PCFx[2:0] D3 D2 I_PCRx[2:0] D1 D0 T_PCx[1:0] Table 16. CR5A − CR8A INSTRUCTION DEFINITIONS Mnemonic Value BLANKx[1:0] 00 Select cross−conduction blanking time 1 ms (default). 01 Select cross−conduction blanking time 2 ms. 10 Select cross−conduction blanking time 3 ms. 11 Select cross−conduction blanking time 4 ms. I_PCFx[2:0] I_PCRx[2:0] T_PCx[1:0] Comment 000 Select falling slope pre−charge current 28.88mA (default). 001 Select falling slope pre−charge current 35.63 mA. 010 Select falling slope pre−charge current 42.00 mA. 011 Select falling slope pre−charge current 48.38 mA. 100 Select falling slope pre−charge current 55.13mA. 101 Select falling slope pre−charge current 61.50 mA. 110 Select falling slope pre−charge current 67.88 mA. 111 Select falling slope pre−charge current 74.63 mA. 000 Select rising slope pre−charge current 1.50 mA (default). 001 Select rising slope pre−charge current 5.25 mA. 010 Select rising slope pre−charge current 8.63 mA. 011 Select rising slope pre−charge current 12.38 mA. 100 Select rising slope pre−charge current 16.50 mA. 101 Select rising slope pre−charge current 20.25 mA. 110 Select rising slope pre−charge current 24.00 mA. 111 Select rising slope pre−charge current 28.13 mA. 00 Select rising/falling slope pre−charge time 100 ns (default). 01 Select rising/falling slope pre−charge time 200 ns. 10 Select rising/falling slope pre−charge time 300 ns. 11 Select rising/falling slope pre−charge time 400 ns. Table 17. CR5B − CR8B: HBx CONFIGURATION B REGISTER CR5B – CR8B WD D10 WD 1 D9 D8 D7 D6 VDSx[2:0] D5 D4 T_DLY[3:0] www.onsemi.com 20 D3 D2 D1 SR_CTRL[2:0] D0 NCV7544 Table 18. CR5B − CR8B INSTRUCTION DEFINITIONS Mnemonic Value VDSx[2:0] 000 Select static VDS sense threshold 300 mV (default). 001 Select static VDS sense threshold 400 mV. 010 Select static VDS sense threshold 500 mV. T_DLY[3:0] SR_CTRL[2:0] Comment 011 Select static VDS sense threshold 600 mV. 100 Select static VDS sense threshold 700 mV. 101 Select static VDS sense threshold 800 mV. 110 Select static VDS sense threshold 900 mV. 111 Select static VDS sense threshold 1000 mV. 0000 Select rising/falling slope dynamic overload detect delay 0.35 ms (default). 0001 Select rising/falling slope dynamic overload detect delay 0.55 ms. 0010 Select rising/falling slope dynamic overload detect delay 0.75 ms. 0011 Select rising/falling slope dynamic overload detect delay 0.95 ms. 0100 Select rising/falling slope dynamic overload detect delay 1.15 ms. 0101 Select rising/falling slope dynamic overload detect delay 1.35 ms. 0110 Select rising/falling slope dynamic overload detect delay 1.55 ms. 0111 Select rising/falling slope dynamic overload detect delay 1.75 ms. 1000 Select rising/falling slope dynamic overload detect delay 1.95 ms. 1001 Select rising/falling slope dynamic overload detect delay 2.15 ms. 1010 Select rising/falling slope dynamic overload detect delay 2.35 ms. 1011 Select rising/falling slope dynamic overload detect delay 2.55 ms. 1100 Select rising/falling slope dynamic overload detect delay 2.75 ms. 1101 Select rising/falling slope dynamic overload detect delay 2.95 ms. 1110 Select rising/falling slope dynamic overload detect delay 3.15 ms. 1111 Select rising/falling slope dynamic overload detect delay 3.35 ms. 000 Select rising/falling slope slew phase current 1.5 mA (default). 001 Select rising/falling slope slew phase current 2.25 mA. 010 Select rising/falling slope slew phase current 3.38 mA. 011 Select rising/falling slope slew phase current 5.25 mA. 100 Select rising/falling slope slew phase current 7.88 mA. 101 Select rising/falling slope slew phase current 11.63 mA. 110 Select rising/falling slope slew phase current 17.25 mA. 111 Select rising/falling slope slew phase current 25.50 mA. Table 19. CR12: HBx DIAGNOSIS CONTROL REGISTER CR12 WD D10 D9 D8 D7 D6 WD 0 0 0 X X D5 Table 20. CR12 INSTRUCTION DEFINITIONS Mnemonic TST_LSx TST_HSx Value Comment 0 Disable low−side test current (default). 1 Enable low−side test current. 0 Disable high−side test current (default). 1 Enable high−side test current. www.onsemi.com 21 D4 TST_LS3 TST_LS1 D3 D2 X X D1 D0 TST_HS3 TST_HS1 NCV7544 Table 21. CR14: HBx PWM DE−GLITCH CR14 WD D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 WD 0 0 0 0 X X X DGL4 DGL3 DGL2 DGL1 D3 D2 D1 D0 Table 22. CR14 INSTRUCTION DEFINITIONS Mnemonic Value DGLx Comment 0 Type 1 de−glitch: tPWM_DGL = tBLANKx + tPRCx + tDLYx (default). 1 Type 2 de−glitch: tPWM_DGL = tPRCx + tDLYx Table 23. CR15: TEST MODE REGISTER WD CR15 D10 D9 D8 D7 D6 WD D5 D4 Factory Use Only SPI Diagnosis Set The first 3 bits D[15:13] serve as address bits, while the 13 bits D[12:0] are used as data bits. Output data for “not used” register adresses is D[11:0] = 0. The address of the Status Register (SRx) accessed for status information to be retrieved via a subsequent SPI frame is selected by the control register bits CR0.SRA_MODE and CR0.SRA[2:0] (see Table 5, Table 6). Two different reading modes are provided depending on the SRA_MODE bit: • when CR0.SRA_MODE = 0, the SRx address selected via bits CR0.SRA[1:0] will be used for a single status read command and the SR address returns to SR0 (device status register, default state) after reading; • when CR0.SRA_MODE = 1, the SRx address selected via bits CR0.SRA[1:0] will be used for the next and all further status read commands until a new address or mode is selected. All status diagnosis bits are initialized to logic 0 after a reset event and in normal operation except: • the NORMAL MODE (NM) bit indicates NORMAL MODE when SRx.NM = 1; • the Register Clear Flag (RCF) bit is set (SR0.RCF = 1) after a mode change to NORMAL MODE (see § Operating Modes). The RCF bit indicates that all input and output registers were initialized; the bit is cleared after SR0 is read. All status diagnosis bits are latched with the exception of the SR5.D[3:0] bits (see § Output Status Monitoring). To de−latch a diagnosis: • the referring failure has to be removed; • the referring failure bit has to be read by SPI diagnosis. Refer to § Protection and Diagnosis to restart the outputs after a fault condition. The SPI diagnosis set (output data map) and output data structure prototype are shown in the following tables. The default reading mode and address after VCC POR or wake−up is CR0.SRA_MODE = 0, CR0.SRA[1:0] = 00. Table 24. SPI OUTPUT DATA FORMAT Status Output Message Format MSB LSB B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A2 A1 A0 NM D11 D10 D9 D8 D7 D5 D5 D4 D3 D2 D1 D0 3−bit REGISTER ADDRESS NORMAL MODE 12−bit OUTPUT DATA Table 25. OUTPUT DATA STRUCTURE PROTOTYPE Output Data Prototype SRx NM D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NM ? ? ? ? ? ? ? ? ? ? ? ? www.onsemi.com 22 NCV7544 Table 26. SPI OUTPUT REGISTER DEFINITIONS Defined Status Output Registers (SRx) D15 D14 D13 D12 Register Name Alias A2 A1 A0 NM Device Status SR0 0 0 0 HB 1…4 Status Monitor SR1 0 0 1 Not Used SR2 0 1 0 HB 1…4 VDS Monitor SR3 0 1 1 HB 1…4 Calibration Result SR4 1 0 0 HB 1…4 Output Status SR5 1 0 1 Not Used SR6 1 1 0 Device ID/Test Mode SR7 1 1 1 NM Table 27. SR0: DEVICE STATUS REGISTER SR0 NM D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NM TM RCF FSM SPIF CPL CPF UVF OVF 0 0 HB_QSB 0 Table 28. SR0 RESPONSE DEFINITIONS Mnemonic Value Comment 0 Test mode inactive (default). 1 Test mode active. 0 Registers not cleared (command input and status output registers). 1 Registers cleared (after mode change to “NORMAL”). 0 FSM input pin = 0 (FSM not asserted). 1 FSM input pin = 1 (FSM asserted). 0 SPI message correct. 1 SPI message failure. 0 Charge pump in regulation 1 V(CP, VS) < CPLOW −OR− VS < VSPWM (Charge Pump Low). 0 Half bridge high−side pre−driver activation allowed. 1 Half bridge high−side pre−driver activation not allowed (Charge Pump Fail). 0 VS supply in normal range. 1 VS supply below normal range. 0 VS supply in normal range. 1 VS supply above normal range. D3 0 Not used. D2 0 Not used. 0 VDS normal − no static or dynamic overload detected. 1 VDS failure – static or dynamic overload detected (VDS_Hx or VDS_Lx). 0 Not used. TM RCF FSM SPIF CPL CPF UVF OVF HB_QSB D0 Table 29. SR1: HBx STATUS MONITOR REGISTER SR1 NM D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NM 0 0 0 0 SWH4 SWL4 SWH3 SWL3 SWH2 SWL2 SWH1 SWL1 www.onsemi.com 23 NCV7544 Table 30. SR1 RESPONSE DEFINITIONS Mnemonic Value SWHx SWLx Comment 0 GHx output is “low” (default). 1 GHx output is “high”. 0 GLx output is “low” (default). 1 GLx output is “high”. Table 31. SR3: HBx VDS MONITOR REGISTER SR3 NM D11 D10 D9 D8 NM 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 VDS_H4 VDS_L4 VDS_H3 VDS_L3 VDS_H2 VDS_L2 VDS_H1 VDS_L1 Table 32. SR3 RESPONSE DEFINITIONS Mnemonic Value VDS_Hx VDS_Lx Comment 0 HBx high−side power switch normal – no static or dynamic overload detected (default). 1 HBx high−side power switch failure – static or dynamic overload detected. 0 HBx low−side power switch normal – no static or dynamic overload detected (default). 1 HBx low−side power switch failure – static or dynamic overload detected. Table 33. SR4: HBx CALIBRATION RESULT REGISTER SR4 NM D11 D10 D9 D8 NM 0 0 0 CAL_READY D7 D6 CAL_DLY_R[1:0] D5 D4 CAL_PC_R[1:0] D3 D2 CAL_DLY F[1:0] D1 D0 CAL_PC _F[1:0] Table 34. SR4 RESPONSE DEFINITIONS Mnemonic Value 0 CAL_READY 1 CAL_DLY_R[1:0] CAL_PC_R[1:0] CAL_DLY_F[1:0] CAL_PC _F[1:0] Comment Calibration result not ready or has been read via SPI (default). Calibration is successfully performed with a valid result (the bit is reset after SPI read command). 00 Rising slope result: VHBx < 15% (default). 01 Rising slope result: 15% < VHBx < 85%. 10 Rising slope result: 85% < VHBx < 95 %. 11 Rising slope result: VHBx >95%. 00 Rising slope result: VHBx < 5% (default). 01 Rising slope result: 5% < VHBx < 15%. 10 Rising slope result: 15% < VHBx < 85 %. 11 Rising slope result: VHBx > 85%. 00 Falling slope result: VHBx > 85% (default). 01 Falling slope result: 85% > VHBx > 15%. 10 Falling slope result: 15% > VHBx > 5%. 11 Falling slope result: VHBx < 5%. 00 Falling slope result: VHBx > 95% (default). 01 Falling slope result: 95% > VHBx > 85%. 10 Falling slope result: 85% > VHBx > 15%. 11 Falling slope result: VHBx < 15%. www.onsemi.com 24 NCV7544 Table 35. SR5: HBx OUTPUT STATUS REGISTER SR5 NM D11 D10 D9 D8 D7 D6 D5 D4 NM 0 0 0 0 0 0 0 0 D3 D2 D1 D0 HB_OUT4 … HB_OUT1 Table 36. SR5 RESPONSE DEFINITIONS Mnemonic Value HB_OUTx Comment 0 Output < VHBTHR (default). 1 Output > VHBTHR. Table 37. SR7: TEST MODE STATUS REGISTER − SR0.TM = 1: TEST MODE FORMAT SR7 NM D11 D10 D9 D8 D7 D6 NM D5 D4 D3 D2 D1 D0 D1 D0 Factory Use Only Table 38. SR7: DEVICE ID/TEST MODE STATUS REGISTER − SR0.TM = 0: DEVICE ID FORMAT SR7 NM NM D11 D10 D9 DEV_ID[11:9] D8 D7 D6 D5 DEV_ID[8:6] D4 DEV_ID[5:3] D3 D2 DEV_ID[2:0] Table 39. SR7 RESPONSE DEFINITIONS: DEVICE ID FORMAT Mnemonic DEV_ID[11:9] ID Type Device Name Value 000 NCV7547 001 NCV7544 010 NCV7546 011−111 000 DEV_ID[8:6] DEV_ID[5:3] Generation Silicon Revision 001−110 Mask Revision etc. Generation 0 Generation 1 etc. 111 Generation 0 (NCV7547) 000 First Silicon (REV_n.m) 001 Second Silicon (REV_n+1.m) 010−111 DEV_ID[2:0] Comment etc. 000 Initial Mask Revision (REV_n.m) 001 First Mask Revision (REV_n.m+1) 010−111 etc. When not in test mode (SR0.TM = 0), a status request via CR0.D[10:7] returns SR7.D[11:0] = DEV_ID[11:0] as defined in Table 39. The default content of SR7 after VCC POR or wake−up is SR7.D[11:0] = 0. The DEV_ID[5:0] revision value may be changed based on whether the entire die (silicon) or intermediate layer (mask) is affected. The revisions can be e.g. classified accordingly: • silicon revision: defined area changed (isolation pocket or other boundary, bond pad etc. changed/moved) or • digital core changed (isolation pocket changed or unchanged); mask revision: interconnect changed (metal and/or polysilicon/contact/via). The mask revision value is set to DEV_ID[2:0] = 000 whenever the die revision is incremented. Table 40 shows how the value encoding scheme is used to indicate the device revision level. www.onsemi.com 25 NCV7544 Table 40. DEVICE REVISION LEVEL ENCODING Silicon Revision The CR1.HB_MODEx bits are used to control the polarity of the selected half−bridge: • when CR1.HB_MODEx=0, the low−side driver (PDL) is in an ON state (i.e. GLx = VGS ≈ VPDLX, see § Electrical Characteristics: Half−Bridge Pre−Driver Outputs); • when CR1.HB_MODEx=1, the high−side driver (PDH) is in an ON state (i.e. GHx = VGS ≈ VPDHX, see § Electrical Characteristics: Half−Bridge Pre−Driver Outputs). Mask Revision DEV_ID[5:3] LEVEL DEV_ID[2:0] LEVEL 000 A 000 0 001 B 001 1 010 C 010 2 011 D 011 3 100 E 100 4 101 F 101 5 110 G 110 6 111 H 111 7 The CR2.HB_PWMx bits are used to enable PWM mode control of the selected half−bridge: • when CR2.HB_PWMx=0, an output is in 100% ON state according to its CR1.HB_MODEx bit; • when CR2.HB_PWMx=1, an output is in PWM with state according to its CR1.HB_MODEx bit. Half−bridge Gate Drivers The half−bridge drivers are used to control the gates of external logic−level NMOS power switches. The device is initialized at power−up into a reduced power state (CR1.DRV_EN = 0, see Table 7, Table 8): • the charge pump is disabled; • all gate drive currents are disabled. • HBx diagnostic test currents are available (see § Monitoring of Half−bridge Drivers in OFF−state). The application of a PWM mode selected via the CR2.HB_PWMx bits to the corresponding output is performed asynchronous to the PWMx input (i.e. a change is applied after the rising edge of the CSB signal). Each half−bridge can be controlled in PWM mode by one of the PWMx inputs as selected via the CR3.PWMx[1:0] bits according to Table 41 (see also Table 11, Table 12): The device is placed into a full power state when CR1.DRV_EN = 1. The half−bridges are held in high−impedance state (external NMOS are off) via gate pull−down structures which are activated during power−up, while in reduced power state, or when in sleep mode. Table 41. CR3A/CR3B: PWM SOURCE SELECTION Control of Half−bridge Drivers The operation of the drivers is controlled by SPI configuration individually for each driver. All half−bridges can be operated in 100% “ON” mode as well as in PWM mode. The control schema is shown in Table 42 (see also § SPI Control Set): The CR0.HB_ENx bits are used to enable the operation of the selected half−bridges and to re−start the drivers after a fault condition: • when CR0.HB_ENx=0, the GHx and GLx outputs are disabled (i.e. VGS ≈ 0 V); • when CR0.HB_ENx=1, the GHx and GLx outputs are enabled. PWMx0 PWM Source Selection 0 Output PWM source is input PWM1 1 Output PWM source is input PWM2 The application of a selected PWMx input signal routing to the corresponding output is performed asynchronous to the PWMx input (i.e. a change is applied after the rising edge of the CSB signal). The selected output is controlled via the selected positive−logic PWMx input (see Figure 8): • when input PWMx=0, the driver defined by its HB_MODEx bit is turned OFF (i.e. VGS ≈ 0 V) and its complementary gate driver is turned ON (i.e. VGS ≈ VPDHX or VGS ≈ VPDLX); Table 42. HBx DRIVER CONTROL Output HB1 … HB4 CR0 HB_ENx CR1 HB_MODEx CR2 HB_PWMx Power Switches Operation Mode Comment 0 X X HBx “OFF” Disable 1 0 0 Low−side “ON” 1 1 0 High−side “ON” 1 0 1 Low−side PWM 1 1 1 High−side PWM www.onsemi.com 26 100% “ON” PWM Mode NCV7544 • when input PWMx=1, the driver defined by its Switching Behavior of Half−bridge Drivers The external high−side NMOS switches are controlled with gate pre−charge and slew phases, while the external low−side switches are controlled via simple drive stages supplying a nominal 4x multiple of the selected high−side driver slew current (see Figure 9 and § Electrical Characteristics: Pre−driver Slope Control). The timing for the gate drivers is provided by the digital logic, where the key parameters can be programmed via SPI in order to adapt different MOSFET types and application switching speeds. Each individual half−bridge can be programmed via three configuration registers, e.g. CR5A and CR5B for HB1, and CR14 (see § SPI Control Set, Table 15 − Table 17 and Table 21, summarized in Table 43): HB_MODEx bit is turned ON (i.e. VGS ≈ VPDHX or VPDLX) and its complementary gate driver is turned OFF (i.e. VGS ≈ 0 V). When multiple PWMx inputs are needed to be active, the scheduled PWM signals should be offset in time to avoid degradation of the VDS overload detection due to crosstalk (see § Overload Protection). The minimum offset should be based on the tPWM_DGL times appropriate for the respective channels (see § Switching Behavior of Half−bridge Drivers, Figure 10 and Figure 11). NOTE: The PWM source selection logic does not prevent more than one half−bridge output to be controlled by the same PWMx input. Table 43. HALF−BRIDGE CONFIGURATION REGISTERS CR5A – CR8A CR5B – CR8B CR14 D9 D8 D7 D10 WD 0 WD D10 WD 1 WD D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 WD 0 0 0 0 X X X DGL4 DGL3 DGL2 DGL1 BLANKx[1:0] D9 D8 D6 D5 D4 I_PCFx[2:0] D7 D6 D2 D1 I_PCRx[2:0] D5 VDSx[2:0] D3 D0 WD D4 D3 T_PCx[1:0] D2 T_DLY[3:0] D1 D0 SR_CTRL[2:0] GHx GLx 0 time PWMx HB_PWMx HB_MODEx HB_ENx Low-side ON High-side ON High-side PWM Low-side PWM 0 time Note 1. GLx and GHx are for the same HBx output control (e.g. HB1: GL1, GH1). Note 2. GLx and GHx time offset from PWMx via adaptive PWM input de-glitch not shown. Figure 8. Gate Drive Operation in PWM Mode www.onsemi.com 27 {02/06/18} NCV7544 For each individual half−bridge: Please refer to § Electrical Characteristics for defined blanking (tBLANKX), pre−charge (tPRCX, IPRCX_R, IPRCX_F), slew (ISRX), delay (tDLYX) and VDS threshold (VDSTHRX) parametric values. • cross−conduction blanking time is selected via the • • • • • • BLANKx[1:0] bits; pre−charge current is selected via the I_PCRx[2:0] bits for the rising slope and via the I_PCFx[2:0] bits for the falling slope; pre−charge time for both slopes is selected via the T_PCx[1:0] bits; slew current for both slopes is selected via the SR_CTRLx[2:0] bits – this parameter controls the external NMOS switches’ rise/fall times to adopt proper EMC performance and minimize switching losses; VDS overload detection delay is selected via the T_DLYx[3:0] bits – this parameter controls when the VDS overload detection is performed (see § Overload Protection); VDS overload detection threshold is selected via the VDSx[2:0] bits – this parameter controls the VDS monitoring comparator threshold (see Table 17, Table 18); adaptive PWM input de−glitch construction when in half−bridge configuration is selected by DGLx[6:0] bits (see Figure 10, Figure 11, Table 21 and Table 22). NOTE: A proper initial switching parameter set (e.g. VDSTHRX, tPRCX, IPRCX_R, ISRX, IPRCX_F) for a chosen MOSFET has to be evaluated for a desired switching speed (see also § Overload Protection). When operated in PWM mode, the PWMx input signals are each provided with a symmetrical de−glitch within a half− bridge’s control logic. The de−glitch time (tPWM_DGL) is adapted to the SPI settings tBLANKX, tPRCX, tDLYX and DGLx as selected for each channel (see § Electrical Characteristics: Half−Bridge Pre−Driver Outputs & Pre−driver Slope Control). The adapted tPWM_DGL avoids mistreatment of the half−bridge drivers by ensuring that a complete turn−on or turn−off sequence is executed (erratic pulse widths are thereby avoided) and assures correct operation of the VDS overload protection (see § Overload Protection) PWMx_DGL 1 < DEGLITCHED INTERNAL SIGNAL > time 0 tBLANK I(GHx) −IPRCX_R tBLANK tPRCx tBLANK tPRCx tTIMEOUT −ISRX 0 −IGHx_SS time +ISRX +IPRCX_F I(GLx) −ILSX 0 time +ILSX {02/06/2018} Figure 9. Gate Drive Current Evolution www.onsemi.com 28 NCV7544 In order to not overload the charge pump circuit in case of loss of VS or in case of a disconnected security switch, the steady state output current of the high−side gate drivers is limited to IGHX_SS after tTIMEOUT (see I(GHx) in Figure 12 and § Electrical Characteristics: Half−Bridge Pre−Driver Outputs). NOTE: Driver turn−ON/OFF via SPI (i.e. CR1.HB_MODEx bits) includes both the pre−charge and slew phases, but adapted de−glitch strategy is not applied. Type 2 de−glitch is selected when CR14.DGLx = 1 (see Figure 11) and the adapted time is given by: t PWM_DGL + t PRCX ) t DLYX NOTE: To avoid synchronization issues, the de−glitch type must be selected before beginning PWM of a load. Once a switching parameter set for EMC optimization and stable VDS overload detection has been chosen, the allowable duty ratio (D) is bounded by the selected adaptive de−glitch type and PWM frequency such that: When operating in PWM mode, type 1 de−glitch is selected when CR14.DGLx = 0 (see Figure 10) and the adapted time is given by: t PWM_DGL + t BLANKX ) t PRCX ) t DLYX (eq. 2) f PWM t PWM DGL ǒ v D v 1 * f PWM t PWM 1 time 0 tPRCx tDLYx tBLANKX tPWM_DGL tPRCx tDLYx tPWM_DGL PWMx_DGL 1 < DEGLITCHED INTERNAL SIGNAL > time 0 Type 1 PWM De−glitch tPWM_DGL = tBLANKX + tPRCX + tDLYX {03/06/15} Figure 10. Type 1 PWMx Input De−glitch − CR14.DGLx = 0 PWMx 1 time 0 tPRCx (eq. 3) When operating in PWM mode, the timing of the gate drivers is according to Figure 12. (eq. 1) PWMx tBLANKX Ǔ DGL tDLYx tPRCx tPWM_DGL tDLYx tPWM_DGL PWMx_DGL 1 < DEGLITCHED INTERNAL SIGNAL > time 0 Type 2 PWM De−glitch tPWM_DGL = tPRCX + tDLYX Figure 11. Type 2 PWMx Input De−glitch − CR14.DGLx = 1 www.onsemi.com 29 {03/06/15} NCV7544 PWMx_DGL 1 < DEGLITCHED INTERNAL SIGNAL > 0 time tBLANK tBLANK V(GHx) tPRCx tPRCx VPDHX VGSP V(HBx) time V(GLx) VPDLX PGND time tDLYx V(HBx) tBLANK tDLYx VS 0.9 VS 0.5 VS VHBTHR 0.1 VS time GND High−side VDS Overload Detection Low−side VDS Overload Detection {02/08/2018} Figure 12. HBx Output Switching in Half−Bridge Configuration parameter set and to verify proper setting of the high−side gate drivers (GHx). The calibration assists optimizing EMC performance and alignment of the GHx switching slopes with the VDS overload detection delay time and threshold to assure stable behavior of the protection strategy (see § Overload Protection). A calibration detection unit, consisting of 4 multiplexed high−speed comparators, samples the voltage at the desired HBx input at a selected calibration sample time (see tCAL_PCx, tCAL_DLYx in § Electrical Characteristics: Slope Control Calibration Unit). A complete calibration cycle consists of sampling both the rising and falling switching slopes, and the encoded calibration result is stored in the device’s calibration register (SR4). In the pre−charge phase (VGHX < VGSP) the GHx output delivers the selected rise (IPRCX_R) or fall (IPRCX_F) current for the selected time (tPRCx), and in the slew phase (VGSP ≤ VGHX ≤ VPDHX) the GHx output delivers the selected current (ISRX) for up to the gate drive timeout time (tTIMEOUT). After tTIMEOUT, the GHx output delivers the timeout current (IGHx_SS). The GLx output always delivers a multiple (ILSX) of the selected slew current (see Figure 9 and § Electrical Characteristics: Half− Bridge Pre−Driver Outputs, Pre−driver Slope Control). Slope Control Calibration Unit A slope control calibration unit is implemented in order to allow adjustments to a selected MOSFET’s initial switching www.onsemi.com 30 NCV7544 Calibration is enabled when the calibration register (CR4) is written (summary Table 44 − see also Table 13): • the desired HBx input is selected by the CR4.CAL_SEL[2:0] bits where the resulting binary code refers directly to the selected half−bridge (e.g. 100 = HB4); • the detection pre−charge and delay sample times (tCAL_PCx and tCAL_DLYx ) for calibration of the desired input are selected individually by the CR4.CAL_PC[3:0] bits and by the CR4.CAL_DLY[3:0] bits for both the rising and falling slopes. and falling edges are completed (see Figure 13). The detection results are stored in the calibration result register SR4 (summary Table 44 − see also Table 33): The CAL_READY bit indicates that when: • SR4.CAL_READY = 0, calibration has not been executed OR the calibration result has been read; • SR4.CAL_READY = 1, successful detection was performed for both slopes AND a valid comparator output state is delivered. As long as the CAL_READY bit is not set (≠ 1), the calibration of a particular slope for the selected channel may be repeated. Calibration may be terminated by sending CR4.CAL_SEL[2:0] = 000. The calibration result is encoded in the SR4. CAL_PC_R[1:0] bits and the SR4.CAL_DLY_R[1:0] bits for the rising slope and in the SR4. CAL_PC_F[1:0] bits and the SR4.CAL_DLY_F[1:0] bits for the falling slope according to Table 45. The calibration unit is turned off when CR4.CAL_SEL[2:0] = 000 (POR default) is selected (see also Table 14). Detection is started with the next edge of a routed PWMx input signal (see § Control of Half−bridge Drivers) on the selected channel and detection is finished when both rising Table 44. HBx CALIBRATION CONTROL AND RESULT REGISTERS WD CR4 SR4 D10 D9 WD D8 D7 D6 CAL_DLY[3:0] D5 D4 D3 D2 CAL_PC[3:0] NM D11 D10 D9 D8 D7 NM 0 0 0 CAL_READY D6 CAL_DLY_R[1:0] D5 D4 CAL_PC_R[1:0] D1 D3 D2 CAL_DLY F[1:0] D1 Value Relative HBx Level Detected at Selected Sample Times Comment Start of Rising Slope CAL_PC_R[1:0] 00 VHBx < 5% Pre−charge too low. 01 5% < VHBx < 15% Pre−charge within target. 10 15% < VHBx < 85% Pre−charge too high. 11 VHBx > 85% Pre−charge far too high. End of Rising Slope CAL_DLY_R[1:0] 00 VHBx < 15% Transition far too slow. 01 15% < VHBx < 85% Transition slightly too slow. 10 85% < VHBx < 95 % Gate drive setting correct. 11 VHBx >95% Transition too fast. Start of Falling Slope CAL_PC _F[1:0] 00 VHBx > 95% Pre−charge too low. 01 95% > VHBx > 85% Pre−charge within target. 10 85% > VHBx > 15% Pre−charge too high. 11 VHBx < 15% Pre−charge far too high. End of Falling Slope CAL_DLY_F[1:0] 00 VHBx > 85% Transition far too slow. 01 85% > VHBx > 15% Transition slightly too slow. 10 15% > VHBx > 5% Gate drive setting correct. 11 VHBx < 5% Transition too fast. www.onsemi.com 31 D0 CAL_PC _F[1:0] Table 45. CALIBRATION RESULT RELATIVE TO HBx SAMPLE TIME Mnemonic D0 CAL_SEL[2:0] NCV7544 • the ISRX slew phase current setting. The temporal position (see Figure 13) of the target transition detection point (e.g. 10%, 90%) with respect to tCAL_PCx or tCAL_DLYx (or in normal operation, tDLYX) of the channel selected for calibration is dependent upon: • the PWMx_DGL resulting from the channel’s operating configuration (see § Switching Behavior of Half−bridge Drivers, Figure 10 and Figure 11); • the tBLANKX cross−conduction blank time setting as applicable; • the tPRCX, IPRCX_R and IPRCX_F pre−charge phase time and current settings; Calibration may be performed at the application level during module end−of−line (EOL) test where the (adjusted) settings may be stored in a microcontroller’s EEPROM. In order to maintain stable function and proper EMC performance with temperature drift and output load variations, the calibration can be verified/updated on a sample basis during normal application operation. PWMx_DGL < DEGLITCHED INTERNAL SIGNAL > PWMx_DGL tBLANKx BLANK tBLANKx tBLANKx tPRCx tPRCx PRE−CHARGE SLEW tDLYx tDLYx (High−side Overload) (Low−side Overload) time V(HBx) VCALR_U 95% 90% VCALR_L 85% FALLING SLOPE RISING SLOPE VCALF_U 15% 10% VCALF_L 5% time CALx CAL PRE−CHARGE CAL SLEW CAL_PC_R[1:0] CAL_DLY_R[1:0] CAL_PC_F[1:0] CAL_DLY_F[1:0] CAL_READY tCAL_PCx tCAL_PCx tCAL_DLYx tCAL_DLYx ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍ ËËËËËËËËË ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ “01” “10” “01” “10” “1” time Figure 13. HBx Slope Control Calibration www.onsemi.com 32 {02/07/2018} NCV7544 OVERLOAD PROTECTION Static Overload Protection delay, CMP2 and CMP3 in Figure 14). A single detection delay time (tDLYX) is used during switching of each of the high−side and the low−side external MOS. The detection delay at each input is selected individually by the T_DLY[3:0] bits in the HBx configuration “B” registers (see § SPI Control Set). The detection delay tDLYX is chosen based on the value of tCAL_R for the rising slope of the high−side MOS as determined from the calibration result (see CAL_DLYR[3:0] in § Slope Control Calibration Unit). The appropriate latch is set (after the adapted tPWM_DGL − see Figure 10 and Figure 11) at the start of the switch activation (see V(HBx) in Figure 12). In the case of the high−side MOS, the delay time tDLYX is started at the end of the pre−charge time (tPRCX). In the case of the low−side MOS, the delay time tDLYX is started concurrent with the GLx turn−on current (see I(GLx) in Figure 11). At the end of time tDLYX the switching node voltage is compared with the appropriate VDSTHR_R or VDSTHR_F overload detection threshold (see § Electrical Characteristics: Half−Bridge Diagnostics). When a switch is being activated and: • the output voltage has not crossed the appropriate threshold by the end of tDLYX, the latch is reset after the de−glitch time tDGL_DYN and both high and low−side power switches are deactivated and the appropriate status bit (see § SPI Diagnosis Set) is latched in the corresponding VDS monitor register (overload detected); • the output voltage has crossed the appropriate threshold by the end of tDLYX, the latch stays in set condition and the power switches remain activated (no overload detected). A static VDS monitoring technique is used to protect the external MOS power switches in case of overload resulting from short circuit conditions applied after activation of the power switches (“short circuit 2” condition). The thresholds of the VDS monitoring comparators (CMP1 and CMP4 in Figure 14) are SPI programmable (see § Electrical Characteristics: Half−Bridge Diagnostics) for each individual half−bridge via the VDSx[2:0] bits in the HBx configuration “B” registers (see Table 17, Table 18). When a switch is in the ON−state (t > tDLYx after end of the pre−charge phase) and its drain−source voltage exceeds the programmed VDS threshold: • the corresponding half−bridge’s GHx and GLx drivers are latched off immediately after a de−glitch time ( see tDGL_STAT in § Electrical Characteristics: Half−Bridge Diagnostics); • the SR0.HB_QSB Quick Status Bits and the appropriate VDS_Hx or VDS_Lx bit is latched in the corresponding VDS monitor status register (see Table 31 and Table 32) Please refer to § Output Fault (Local) Protection to restart the half−bridge drivers after a shutdown event. NOTE: Additional protection via use of current sensing in the low−side path of the power MOSFETs (see Figure 2) may be necessary in order to avoid destruction due to soft short condition. Dynamic Overload Protection A dynamic switching slope monitoring technique is used to protect the external MOS power switches in case of overload resulting from short circuit conditions applied before or during activation of the power switches (“short circuit 1” condition). The output voltage at the switching nodes (HBx) is monitored during each of the GHx and the GLx turn−on phases by a high speed comparator (< 100 ns propagation Please refer to § Output Fault (Local) Protection to restart the half−bridge drivers after a shutdown event. NOTE: The same VDS_Hx and VDS_Lx status bits in register SR3 are used to report either static or dynamic overload condition. www.onsemi.com 33 NCV7544 HBx Diagnostic & Overload Protection VDSTHR_S CR1.D[3:0] STATIC VDS HB_MODEx + CMP1 tDGL_STAT − 3 x tDLY VDSTHR_R tDLY VS + tDGL_DYN CMP2 SECURITY SWITCH − DYNAMIC VDS (reset dominant) R Q LATCH Q S PDH HBx VDS_HX VBAT_P GHx LOAD SR3.D[7:0] VDS_LX S Q LATCH R Q GLx PDL (reset dominant) DYNAMIC VDS + PGND CMP3 tDGL_DYN 3−5 m − tDLY VDSTHR_F 3 x tDLY + tDGL_STAT CMP4 − STATIC VDS VDSTHR_S + SR5.D[3:0] HB_OUTx CMP5 − TRANSPARENT VS/2 VHBTHR = INDIRECT PATH {08/12/2015} Figure 14. HBx Diagnostic and Overload Protection Gate Protection Features OFF−state Monitoring of Half−bridge Drivers The half−bridge gate drivers provide integrated gate protection features for the external power MOSFETs: • a passive pull−down resistor RGSX keeps the MOSFET in OFF−state, when no control of the device is available (see § Package Pin Description and § Electrical Characteristics: Half−Bridge Pre−Driver Outputs); • a clamping structure limits the gate−source voltage to +VGSX_CLP or to −VGSX_CLN in order to protect the power MOSFETs from destruction via e.g. gate oxide failure (see § Electrical Characteristics: Half−Bridge Pre−Driver Outputs). In order to support functional safety and to avoid unintended motor activation, the status of each of the half−bridge gate drivers can be monitored by SPI diagnosis (see § Gate Driver Status Monitoring). The switch nodes (i.e. HBx) status can be monitored by SPI communication via the half−bridge output status register (SR5.D[7:0] − see Table 35, Table 36). The system response depends on the load configuration; the test procedure has to be provided by the supervising microcontroller. Several test current sources (ITST – see § Electrical Characteristics: Half−Bridge Diagnostics) and comparators are implemented in order to provide OFF−state diagnosis of the power MOSFET half−bridges. The resistors and clamping structures are available in all operating modes, including SLEEP MODE and in case of loss of supply voltage. www.onsemi.com 34 NCV7544 Operating Modes The diagnostic consists of (see Figure 14 and Figure 15): • a high−side and a low−side test current source at each • The operating modes of the device are shown in the diagram of Figure 16. The logic input pin pull up / pull down resistors and the integrated gate protection pull−down resistors and clamping structures (see § Gate Protection Features) are available in all operating modes. The SLEEP MODE is the default mode after applying VCC (VCC < VCCPORF) and while VCC > VCCPORR (power−on reset) prior to wake−up of the device. During SLEEP MODE: • the device is inactive and all outputs are disabled. odd−numbered HBx feedback input; a comparator (CMP5) at each HBx feedback input. Provided the device is in NORMAL MODE (see § Operating Modes) and no global failure (see § Device Fault (Global) Protection) has been detected, the test current sources can be activated individually by the TST_HSx and TST_LSx bits in the HB diagnosis register (CR12.D[5:0] − see Table 19, Table 20). Active pull−down current sources are disabled in all GHx when any test current is activated via CR12. Passive pull−down structures are always present. The device enters NORMAL MODE after applying the wake−up signal (i.e. RSTB 0 → 1). During NORMAL MODE: • the device is active (RSTB = 1); • the entire device functionality is available; • the SPI can be used to provide control and diagnosis of the device. NOTE: Both TST_HSx and TST_LSx test currents can be turned on simultaneously. HBx OFF−State Diagnostic When the device enters NORMAL MODE the internal registers and settings are cleared to default values and the SR0.RCF bit inside the device status register is set (see Table 27, Table 28). The device enters FAILSAFE MODE when the device is active and either a SPI failure condition is detected or the external fail input (FSM) is activated i.e. FAILSAFE = (RSTB = 1) AND [(SPIF=1) –OR– (FSM=1)]. In FAILSAFE MODE: • the half−bridge gate drive outputs (GHx, GLx) are disabled immediately; • the HBx test currents (see § OFF−state Monitoring of Half−bridge Drivers) are disabled immediately; • the CPSW output is deactivated (the external MOS half−bridge switches may be locked additionally by an optional external security switch which can be under control of a separate supervisory microcontroller (see “WD_EN” in Figure 2) in order to support functional safety even in case of logic issues/single point failures); • the charge pump is disabled; • SPI control is not possible. VS R ITST HB1, HB3 CR12.TST_HSx + SR5.D[3:0] HB_OUTx HB1 ... HB4 CMP5 R VHBTHR ITST HB1, HB3 CR12.TST_LSx AGND = INDIRECT PATH PGND {08/07/2018} Figure 15. Half−bridge OFF−state Diagnostic www.onsemi.com 35 NCV7544 VCC < VCCPOR VCC > 0 SLEEP MODE VCC < VCC POR −OR− RSTB = 0 VCC < VCC POR −OR− RSTB = 0 VCC>VCC POR −AND− RSTB=1 FAILSAFE MODE NORMAL MODE FSM = 0 −AND− SPIF = 0 SRx.NM = 0 SRx.NM = 1 FSM = 1 −OR− SPIF = 1 Figure 16. Operating Modes State Diagram Re−entering NORMAL MODE after FAILSAFE MODE is achieved by toggling the WD bit while FSM = 0. After this mode change the internal registers and settings are cleared and the SR0.RCF bit inside the device status register is set (see Table 27, Table 28). Although SPI control of the outputs is not possible in the status registers are not cleared during the transition from NORMAL MODE to FAILSAFE MODE. The device status therefore is accessible in FAILSAFE MODE as long as the SPI interface is available (i.e. as long as VCC is present). The SPI can thus be used in FAILSAFE MODE to provide limited diagnosis of the device (CR0.SRA_MODE, CR0.SRA[2;0]) and to re−enter NORMAL MODE. FAILSAFE MODE, PROTECTION AND DIAGNOSIS again and the restart will not be successful. The restart will be only successful after the error condition is removed. It is recommended to use OFF state diagnosis (see § OFF−state Monitoring of Half−bridge Drivers) to check the HBx node for any failure condition before restarting the output. NOTE: An external aluminum electrolytic capacitor at the VS terminal is necessary to handle the turn−off energy of the motors in emergency condition. Output Fault (Local) Protection The external power MOSFET switches are protected against overload condition (see § Overload Protection) in NORMAL MODE by VDS monitoring. In case of a VDS overload failure, the corresponding pre−driver outputs are latched off (GHx = L AND GLx = L) after a de−glitch time and the status is reported in the VDS monitor register SR3 (see Table 32). To restart a faulted half−bridge: • the diagnosis has to be de−latched by reading the corresponding failure flag; • the output has to be restarted via the corresponding bits in the CR0.HB_ENx register (see § SPI Control Set). Device Fault (Global) Protection As long as a failure flag is not de−latched via SPI status read, a faulted output cannot be turned back on. If the failure condition is still present at a restart, the error flag will be set The high−side pre−driver outputs are protected by charge pump monitoring (see § Charge Pump, Figure 5 and Figure 6): The device is protected against all relevant failure conditions inside the automotive application. In case of a fault condition, the affected outputs are latched off immediately after a de−glitch time and the status is reported the device status register (SR0 − see Table 27, Table 28). To restart the device: • the diagnosis has to be de−latched by reading the corresponding failure flag (see § SPI Diagnosis Set); • the functionality has to be restarted by use of the corresponding control bit (see § SPI Control Set). Charge Pump Monitoring www.onsemi.com 36 NCV7544 • when the battery supply voltage VS is below the • • • • • • GHX pull−down current is reduced to 1 mA minimum supply voltage for a regulated charge pump voltage OR V(CP,VS) drops below the minimum output voltage CPLOW this status is reported by the SR0.CPL bit in the device status register immediately after a de−glitch time tCPL_DGL (see Table 27, Table 28). During this condition it should be considered for the microcontroller to adopt a PWM duty ratio management schema in order to minimize charge pump loading while ensuring smooth motor operation. when the charge pump output voltage V(CP, VS) drops below the charge pump fail threshold CPFAIL, the half bridge high−side and low−side gate drivers are latched off immediately after a de−glitch time tCPF_DGL and the status is reported by the SR0.CPF bit in the device status register (see Table 27, Table 28). when the battery supply voltage VS is in the nominal operation range VSPWM < VS < VSOVSDR the full PWM operation of the GHx and GLx outputs is allowed; when the battery supply voltage is in over−voltage condition VS > VSOVSDR, the SR0.CPF bit is masked; when the battery supply voltage is in over−voltage condition VSOVSDF < VS < CPOV the charge pump − including the CPSW output − is functional but the GHx outputs are shut down; when the battery supply voltage exceeds the maximum supply voltage for the charge pump VS > CPOV the charge pump is disabled and the charge pump buffer capacitor is discharged to VS in order to protect the device from destruction. • typ.(register contents are not changed − the current will revert to its prior value after VS over−voltage is resolved); the HBx test currents (see § OFF−state Monitoring of Half−bridge Drivers) are disabled immediately. The VS over−voltage condition is reported by the SR0.OVF bit in the device status register (see Table 27, Table 28). When the battery supply voltage is in over−voltage condition VS > VSOVSDR the SR0.CPF bit is masked. Please refer to § Device Fault (Global) Protection to restart the outputs after a shutdown event. A VCC overvoltage condition can occur during breakdown of the external voltage regulator. Please refer to § Failure of External Voltage Regulator for details. Under Voltage Condition In case of VS under voltage condition: • all outputs (GHx, GLx) are disabled immediately after the de−glitch time tUVDGL and the condition is reported by the SR0.UVF bit in the device status register (see Table 27, Table 28); • the charge pump circuit and the switched charge pump output (CPSW) are still functional in order to keep the optional reverse battery and security switches active. Please refer to § Device Fault (Global) Protection to restart the outputs after a shutdown event. In case of VCC under voltage condition (power−on reset condition, VCC < VCCPOR): • the device enters SLEEP MODE immediately without de−glitch time; • logic input pull−up/down resistors, GHx & GLx output pull−down resistors, and VCC under voltage lockout assure safe operating states for all outputs. Please refer to § Device Fault (Global) Protection to restart the outputs after a shutdown event. Over−voltage Condition During VS over−voltage, the behavior of the gate drivers (GHx and GLx) depends on the programmed operation mode: • the high side gate drivers (GHx) are latched off immediately after de−glitch time tOVDGL (see § Electrical Characteristics: VS Supply) in order to protect the application from over load condition; while the low−side gate driver outputs (GLx) are operable in order to provide controlled braking (e.g. for lift gate motors); To restart the device after this condition a wake−up sequence is necessary (see § Operating Modes). Logic I/O Plausibility Check The logic I/O pins are protected against mistreatment by input de−glitch circuits. The de−glitch circuits are implemented digitally, refer to § Electrical Characteristics: Digital I/O for values. www.onsemi.com 37 NCV7544 FUNCTIONAL SAFETY SUPPORT STRATEGY microcontroller by means of the SPI communication (see Figure 14 and § SPI Diagnosis Set): The output voltage levels of the half−bridge switches are monitored by the transparent VS/2 comparators. The comparator states are not latched and the current node states are indicated by the HB_OUTx bits in the SR5 half−bridge output status register. The controller can use the motor status information for correlation of the operating mode, OFF state diagnosis, or for controlled brake activation. The device uses a closed−loop verification strategy in order to avoid mistreatment of the outputs and to support functional safety. The verification strategy is implemented based on the features in the following sections. SPI Communication Monitoring The SPI is protected against communication errors by use of the WD toggle bit and protocol check features (see § SPI Interface). In case of SPI communication error the device enters FAILSAFE MODE immediately (see § Operating Modes). A correct communication is reported in the NM bit (see § SPI Diagnosis Set). External Fail Mode Activation The FAILSAFE MODE can be also activated by an external signal (e.g. watchdog circuitry) via the FSM input. In case of a malfunction of the microcontroller, an external watchdog can cause the device to enter FAILSAFE MODE (see § Operating Modes). Gate Driver Status Monitoring The correct activation of the half−bridge drivers can be monitored by the microcontroller by means of SPI communication (see § SPI Diagnosis Set). The switching status of the output drivers is indicated by the SWLx and SWHx bits in the half− bridge status monitor register SR1. The bit value corresponds to the logic status of the driver. In PWM mode, both SWHx = 1 and SWLx = 1. In case of a discrepancy between control data and status information from the device, the microcontroller has to drive the device into FAILSAFE MODE in order to avoid mistreatment of the motor drives, then transition the device to NORMAL MODE for reprogramming. Failure of External Voltage Regulator In case of breakdown of the external voltage regulator, the device and the application’s VCC node may be protected against overload by use of an optional external voltage limiter circuit which must limit the voltage to VCCMAX (see Figure 2 and § MAXIMUM RATINGS). The SPI port’s SO pin is protected against reverse biasing by use of a back−to−back switch. The reverse voltage for this condition is limited to V_SOMAX (see § MAXIMUM RATINGS). Output Status Monitoring The status of the MOS switches and the motor connection lines can be monitored during NORMAL MODE by the FLEXMOS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 38 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5x5, 0.5P (PUNCHED) CASE 485CZ ISSUE A DATE 29 JUL 2013 SCALE 2:1 PIN ONE REFERENCE ÉÉÉ ÉÉÉ ÉÉÉ L A B D L DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e L 0.15 C 0.15 C 0.10 C TOP VIEW (A3) DETAIL B A DETAIL B ALTERNATE CONSTRUCTION 0.08 C SIDE VIEW NOTE 4 A1 C 0.10 SEATING PLANE GENERIC MARKING DIAGRAM* C A B M 1 D2 DETAIL A 32X 9 L XXXXXXXX XXXXXXXX AWLYYWWG G 8 E2 1 24 32 32X e e/2 BOTTOM VIEW 0.10 b M 0.10 M C A B 0.05 M C XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) C A B NOTE 3 RECOMMENDED SOLDERING FOOTPRINT 5.30 32X 3.60 0.50 PITCH DOCUMENT NUMBER: DESCRIPTION: *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 0.62 3.60 PKG OUTLINE (0.15) (0.10) MILLIMETERS MIN MAX 0.80 0.90 −−− 0.05 0.20 REF 0.20 0.30 5.00 BSC 3.20 3.40 5.00 BSC 3.20 3.40 0.50 BSC 0.30 0.50 5.30 32X 0.30 DIMENSIONS: MILLIMETERS 98AON87072E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. QFN32 5x5, 0.5P (PUNCHED) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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