12 Channels 60 mA LED
Linear Current Driver I2C
Controllable for Automotive
Applications
NCV7685
www.onsemi.com
The NCV7685 consists of twelve linear programmable constant
current sources with common reference. The part is designed for use in
the regulation and control of LED for automotive applications. The
NCV7685 allows 128 different duty cycle levels adjustable using
pulse width modulation (PWM) independently for each output
channel programmable via I2C serial interface. PWM frequency can
be chosen in four different configurations up to 1200 Hz. The device
can be used with micro−controller applications using the I2C bus or in
stand−alone applications where a choice could be done in between 2
different static configuration settings. The IC also provides 3.3 V
voltage reference to the application for loads up to 1 mA.
LED brightness level is easily programmed using an external
resistor. Each channel has an internal circuitry to detect open−load
conditions with an optional auto−recovery mode. If one driver is in
open−load condition, all other channels could be turned off according
to the programmable bit setting.
The device is available in small body size SSOP24−EP package.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
12 Common Current Programmable Sources up to 60 mA
Independent PWM Duty Cycle Control for each Channel via PC
Common PWM Duty Cycle Control via I2C
On−Chip 150, 300, 600 and 1200 Hz PWM
Open LED String Diagnostics
Low Dropout Operation for Pre−Regulator Applications
Single Resistor for Current Set Point
Voltage Reference 3.3 V/1 mA
8 Bits I2C Interface with CRC8 Error Detection
OTP Bank for Stand−Alone Operation (2 Configurations)
Output Enable Pin
Detection and Protection Against Open Load and Under−Voltage
Over Temperature Detection and Protection
Low Emission with Spread Spectrum Oscillator
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
SSOP24−EP Packaging
SSOP24−NB EP
CASE 940AQ
MARKING DIAGRAM
NCV7685
AWLYYWW
G
NCV7685 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
NCV7685DQR2G
SSOP24−EP
(Pb−Free)
2500/
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications
•
•
•
•
•
•
Dashboard Applications
Rear Combination Lamps (RCL)
Daytime Running Lights (DRL)
Fog Lights
Center High Mounted Stop Lamps (CHMSL) Arrays
Turn Signal and Other Externally Modulated Applications
© Semiconductor Components Industries, LLC, 2017
October, 2020 − Rev. 2
1
Publication Order Number:
NCV7685/D
NCV7685
VS
OUT1
OUT12
Life Support
3V3
REG
Vint.
REG
Vint.
REG
ctrl
Iset
60mA
VDD
OEN
Iset
60 mA
Vint.
ctrl
Iset
DIAG
Diagnostic control
SCL
Iset
GNDP
I2C
Registers
DIAGEN
SDA
PWM Registers
CONF
OTP
NCV7685
GND
EXPOSED PAD
ISET
CONF
DIAG
DIAGEN
VS
OEN
OUTx
Figure 1. Block Diagram
VCC
VCC
VDD
SCL
SDA
GND
Figure 2. ESD Schematic
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2
GNDP
NCV7685
OUT1
VDD
OUT2
SCL
OUT3
SDA
OUT4
OEN
OUT6
G
OUT7
OUT8
NCV7685
AWLYYWW
OUT5
DIAG
GNDP
DIAGEN
VS
OUT9
VCC
OUT10
CONF
OUT11
ISET
OUT12
GND
Figure 3. Pinout Diagram
Vsupply
MRA4003T3G
LDO
or
DC/DC
I2 C
Micro−
controller
OUT1
OUT12
VCC
ctrl
Iset
VDD
CVDD
100nF
4.7K
R5
R6 R7
4.7K 10K
{
COEN
10nF
OEN
ctrl
Iset
SCL
SDA
CONF
R1
Iset
DIAG
DIAGEN
NCV7685
EXPOSED
PAD
GND
GNDP
This GND−track is exclusively
for COEN connection. (to avoid
common impedance coupling from
other GND−currents)
Figure 4. Application Diagram with Micro−controller (I2C Mode)
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3
Iset 2.2K
R4
10K
60 mA
Open Drain
GPIO structure
VS
60mA
3.3V/5V
LDO
C2
1 nF
C OUT12
(optional)
1nF
C OUT1
(optional)
1nF
C1
100 nF
e.g. sensor
Optional connection if MCU
control of OEN input is required.
V STRING
C DIAG
(optional)
1nF
VCC
R2
10K
R3
2.2K
NCV7685
Vsupply
MRA4003T3G
LDO
or
DC/DC
V STRING
COUT1
(optional)
1nF
C1
100nF
e.g. sensor
C2
1nF
VS
COUT12
(optional)
1nF
OUT12
OUT1
VCC
R1
ctrl
Iset
Iset
60mA
VDD
VS
Vsupply
R4
10K
ctrl
Iset
OEN
60 mA
R7
10 K
Iset 2.2K
SCL
SDA
CONF
COEN
10 nF
NCV7685
EXPOSED
PAD
GND
R2
10K
DIAG
DIAGEN
GNDP
R3
2.2K
CDIAG
(optional)
1 nF
This GND−track is exclusively for
COEN connection. (to avoid
common impedance coupling from
other GND−currents)
Figure 5. Application Diagram without Micro−controller (Stand Alone Mode)
Table 1. PIN FUNCTION DESCRIPTION
Pin #
Label
1
OUT1
Channel 1 Current Output to LED
2
OUT2
Channel 2 Current Output to LED
3
OUT3
Channel 3 Current Output to LED
4
OUT4
Channel 4 Current Output to LED
5
OUT5
Channel 5 Current Output to LED
6
OUT6
Channel 6 Current Output to LED
7
OUT7
Channel 7 Current Output to LED
8
OUT8
Channel 8 Current Output to LED
9
OUT9
Channel 9 Current Output to LED
10
OUT10
Channel 10 Current Output to LED
Description
11
OUT11
Channel 11 Current Output to LED
12
OUT12
Channel 12 Current Output to LED
13
GND
Signal Ground
14
ISET
Current Setting/EoL Enable Pin
15
CONF
16
VCC
17
VS
18
DIAGEN
19
GNDP
Power Ground for output drivers
20
DIAG
Open−drain diagnostic input/output.
Reporting Open Circuit and thermal shutdown.
Normal Operation = HIGH
Stand Alone Mode Selection Bank
3.3 V Voltage Reference Output (Needs External Decoupling Capacitor)
Supply Voltage Input
Diagnostic Voltage Sensing Node for VSTRING Via Resistor Divider
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4
NCV7685
Table 1. PIN FUNCTION DESCRIPTION (continued)
Pin #
Label
Description
21
OEN
Output Enable Input
22
SDA
I2C Serial Data
23
SCL
I2C Serial Clock
24
VDD
Digital Supply Voltage Input
epad
epad
True Ground
Do NOT Connect to PCB Traces other than GND
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Unit
VMAX_VS
Power supply voltage:
Continuous supply voltage
Transient Voltage (t < 500 ms, “load dump”)
−0.3
−0.3
28
40
V
V
VMAX_INx
Input pin voltage (DIAGEN, DIAG, CONF, OEN)
−0.3
40
V
VMAX_OUTx
Continuous Output Pin voltage
Transient Voltage (t < 500 ms, “load dump”) or during PWM
period = OFF
−0.3
−0.3
28
40
V
V
VMAX_VCC
Stabilized supply voltage
−0.3
3.6
V
VMAX_VDD
Digital input supply voltage
−0.3
5.5
V
DC voltage at pins (VDD, SCL, SDA)
−0.3
5.5
V
VMAX_IO
VMAX_ISET
DC voltage at pin ISET
−0.3
3.6
V
IMAX_GNDP
Maximum Ground Current
−
750
mA
TJMAX
Junction Temperature, TJ
−40
150
°C
TA_zap
OTP Zap Ambient Temperature
10
30
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are
considered as outside normal operating range. Protection functions are not designed for continuous repetitive operation.
Table 3. ATTRIBUTES
Parameter
ESD Capability (Note 2)
ESD Voltage, HBM (Human Body Model); (100 pF, 1500 W)
− All pins
− Output pins OUTx to GND
ESD according to CDM (Charge Device Model)
− All pins
− Comer pins
ESD according to MM (Machine Mode)
− All pins
Moisture sensitivity (SSOP24−EP) (Note 3)
Value
Unit
±2
±4
kV
kV
±500
±750
V
V
±150
V
MSL2
Storage Temperature
Package Thermal Resistance (SSOP24−EP) (Note 4)
− Junction to Ambient, RqJA
− Junction to Board, RqJB
− Junction to Case (Top), RqJC
−55 to 150
°C
45.8
8.8
10.1
°C/W
°C/W
°C/W
2. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD CDM tested per EIA/JES D22/C101, Field Induced Charge Model
ESD MM according to AEC−Q100
3. For additional information, see or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D,
and Application Note AND8003/D.
4. Values represent thermal resistances under natural convection are obtained in a simulation on a JEDEC−standard, 2S2P; High Effective
Thermal Conductivity Test Board as specified in JESD51−7, in an environment described in JESD51−2a.
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5
NCV7685
Table 4. ELECTRICAL CHARACTERISTICS
(5 V < VS < 18 V, 3.15 V < VDD < 5.5 V, R1 = 1.82 kΩ, −40°C ≤ TJ ≤ 150°C, unless otherwise specified)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
VS_EXT
Functional extended range (limited temperature)
5
−
28
V
VS_OP
Parametric operation
GENERAL
Supply Voltage
Supply Under−Voltage
Supply range during
OTP zapping
Supply Under−Voltage
hysteresis
Supply Current (Vs)
VSUV
VS_OTPzap
5
−
18
V
VS rising
3.8
4.1
4.4
V
2.5 V ≤ ISET ≤ 3.3 V;
VS current peak capability ≥ 70 mA
13
−
18
V
−
200
−
mV
−
−
1.2
2.2
1.5
2.5
mA
mA
Active Mode
VS = 16 V, Vcc unloaded
OUTx = 1 V, R1 = 2 kW
−
7
10
mA
I2C mode, VS = 12 V
VSUVhys
Is(error mode)
all OUTx OFF except channel in open load
SCL = SDA = 0
Iout_VCC = 0 mA
Iout_VCC = 1 mA
Is(active)
Digital supply current
IDD
−
0.24
2
mA
VDD Under Voltage
detection
VDDUV_R
VDD rising
−
−
2.9
V
VDDUV_F
VDD falling
2
−
−
V
IOUThot
OUTx = 1 V, Tj = 150°C
50
55
60
mA
IOUTcold
OUTx = 0.5 V, Tj = −40°C
50
55
60
mA
ImatchCold
Tj = −40°C (Note 5)
−7
0
7
%
Imatch
Tj = 25°C (Note 5)
−6
0
6
%
ImatchHot
CURRENT SOURCE OUTPUTS
Output current
Current Matching from
channel to channel
Tj = 150°C (Note 5)
−5
0
5
%
Current Slew Rate
ISRx
10% to 90%
−
30
−
mA/ms
Open Circuit Detection
Threshold
OLDT
IOUTx > 20mA
30
50
70
% of output
current
Open load recovery in
auto−recovery mode
OLR
5
10
15
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Matching formulas:
ƪ
ƫ
2IOUTx(min)
*1
IOUTx(min) ) IOUTx(max)
100 and
ƪ
ƫ
2IOUTx(max)
*1
IOUTx(min) ) IOUTx(max)
100
Table 5. ELECTRICAL CHARACTERISTICS
(5 V < VS < 18 V, 3.15 V < VDD < 5.5 V, R1 = 1.82 kΩ, −40°C ≤ TJ ≤ 150°C, unless otherwise specified)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
I_VCC ≤ 1 mA
3.20
3.30
3.45
V
−
−
−1
mA
ESR < 200 mW
0.9
1.0
2.5
nF
VOLTAGE REFERENCE
V_VCC
Output Voltage Tolerance
Iout_VCC
Output Current
Cload_VCC
Load Capacitor
INPUTS: OEN, CONF
VinL
Input Low Level
0.7
1.0
−
V
VinH
Input High Level
−
1.25
1.66
V
Vin_hyst
Input Hysteresis
100
250
400
mV
Input Pull−down Resistor
120
200
280
kW
−
−
0.3×VDD
V
Rin_pd
INPUTS: SCL, SDA
VinL
Input Low Level
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NCV7685
Table 5. ELECTRICAL CHARACTERISTICS (continued)
(5 V < VS < 18 V, 3.15 V < VDD < 5.5 V, R1 = 1.82 kΩ, −40°C ≤ TJ ≤ 150°C, unless otherwise specified)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
0.7×VDD
−
−
V
0.05×VDD
−
−
V
3
−
−
mA
INPUTS: SCL, SDA
VinH
Input High Level
Vin_hyst
Input Hysteresis
Iout_SDA
Output Current
V (SDA) = 0.4 V
DIAGEN PIN
VDiagenTH
VS Diagnostic Enable Threshold
1.9
2.0
2.1
V
Rdiagen_pd
Input Pull−down Resistor
120
200
280
kW
−
0.2
0.4
V
DIAG PIN
VoutL
Output Low Level
Diagnostic Activated,
Idiag = 1 mA
DiagRes
Diagnostic Reset Voltage
1.65
1.80
1.95
V
tp_DIAG
Filter Time to Set the DIAG Fail Pin in
Failure Mode
Idiag = 1 mA
−
10
20
ms
DIAG Output Leakage
VDIAG = 5 V
−
−
10
mA
0.94
1.0
1.06
V
−
100
−
−
VS > 5 V
−
−
50
ms
DIAG_leak
ISET INPUT PIN
VISET
K
tsetupISET
Global Current Setting
IOUT ISET Factor
Setup−up Time to 90% of the ISET
Regulated Value
INTERNAL PWM CONTROL UNIT (OUT1− OUT12)
Symbol
PWM1
Parameter
PWM1 Frequency, I2C Mode
I2C
Mode
Test Conditions
Min
Typ
Max
Unit
Configuration Via I2C
132
150
168
Hz
I2C
PWM2
PWM2 Frequency,
264
300
336
Hz
PWM3
PWM3 Frequency, I2C Mode
Configuration Via
Configuration Via I2C
528
600
672
Hz
PWM4
PWM4 Frequency, I2C Mode
Configuration Via I2C
1056
1200
1344
Hz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 6. THERMAL WARNING AND THERMAL SHUTDOWN PROTECTION
Symbol
Tjwar_on
TSD
Tjsd_hys
Parameter
Min
Typ
Thermal Warning Threshold (Junction Temperature)
Max
Unit
−
TSD−30
−
°C
Thermal Shutdown Threshold (Junction Temperature)
TJ Increasing
160
−
180
°C
Thermal Shutdown Hysteresis
10
−
15
°C
General
Output Current Programming (ISET/IOUTx)
The NCV7685 is a twelve channel LED driver. Each
output can drive currents up to 60 mA/channel and are
programmable via an external resistor. The target
applications for the device are in automotive rear lighting
systems and dashboard applications. The device can be used
with micro−controller applications using the I2C bus or in
stand−alone applications. In both cases it is mandatory to
supply the LED channels by an external ballast transistor, or
by an LDO or a DC/DC to have low voltage drop on the
outputs which will lead to a decrease in power dissipation in
the device. In order to have very low electromagnetic
emission, this device has an embedded spread spectrum
oscillator.
The maximum current can be defined with the Iset input
pin. The equations below can be used to calculate this
maximum output current:
(eq. 1)
Iset + 1 VńR1
IOUTx + K
Iset
(eq. 2)
Example:
R1 = 2 kΩ
using eq. 1 → Iset = 500 μA
and using eq. 2 → IOUTx = 50 mA
To avoid potential disturbances when all drivers are
activated at the same time, a typical activation delay of
400 ns between groups of 2 consecutive outputs is
implemented (see Figure 6).
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7
NCV7685
PWM period counter
PWM signal
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
driver 1
driver 2
driver 3
driver 4
driver 5
driver 6
driver 7
driver 8
driver 9
driver 10
driver 11
driver 12
Figure 6.
Power Supply and Voltage Reference (VS, VCC, VDD)
ISET resistor is connected to the ISET pin, the access to the
OTP registers is not possible. Zapping is only possible with
VS above 13 V. The outputs are disabled as soon as 2.5 V is
applied to the ISET pin. After the ID_LOCK_OTP I2C
message is properly received, no further OTP zapping is
possible.
VS is the analog power supply input of the device. VS
supply is monitored with respect to the crossing of VSUV
level (typ. 4.1 V). When VS rises above VSUV, the device
starts the power−up state. When VS is above the VS_OP
minimum level (typ. 5 V), the device can work properly.
VCC is a voltage reference providing 3.3 V derived from
the VS main supply. It is able to deliver up to 1 mA and is
primarily intended to supply 3.3 V loads. If VCC output
reference is not used, then the VCC capacitor can be omitted.
VDD is the digital power supply input of the device.
Output Enable (OEN)
When the OEN input voltage is high, all output channels
are programmed according to the I2C or SAM
configuration. When OEN voltage is below 0.7 V, all
outputs are disabled in the SAM or I2C mode regardless on
the registers setting. If the OEN pin is left floating, the
internal pull down resistor will cause switching off all
channels. The OEN pin has to have max slope of 5 mV for
first 10 ms until VCC is activated. The recommended
examples are shown in Figure 4 and Figure 5. The Figure 11
shows the example of the driving multiple NCV7685 drivers
from one MCU.
5V
VS
VDD
Activation of the VDD can be
before or after VS supply
Configuration (CONF)
*) VCC is internally
derived from VS
When the CONF input voltage will be below 0.7 V the
configuration 1 will be selected (One Time Programmable
OTP 1 register called SAM_CONF_1) and when the CONF
input voltage will be above 1.66 V the configuration 2 will
be selected (OTP 2 register called SAM_CONF_2). There
is ability to change the configuration in error mode (either
with CONF in SAM or through I2C in I2C mode).
VCC
tsetupISET is up to 50 μs
OEN
OEN pin has to have max slope of
5 mV/10 μs until VCC is activated.
Slope on the OEN pin has to be slower
than slope on the VS or slope on VDD
(depends on what comes first)
I2C Bus (SCL, SDA)
The I2C bus consists of two wires, Serial Data (SDA) and
Serial Clock (SCL), carrying information between the
devices connected on the bus. Each device connected to the
bus is recognized by a unique address and operates as either
a transmitter or receiver, depending on the function of the
device. The NCV7685 can both receive and transmit data
with CRC8 error detection algorithm. The NCV7685 is a
slave device.
SDA is a bi−directional line connected to a positive supply
voltage via an external pull−up resistor. When the bus is free
both lines are HIGH. The output stages of the devices
connected to the bus must have an open drain to perform the
Figure 7. Power−up Sequence for OEN pin
Ground Connections (GND: Pin 13 and GNDP Pin 19)
The device ground connection is split to two pins called
GND and GNDP. Both pins have to be connected on the
application PCB.
Chip Select for OTP Programing (Using ISET)
The device can be programmed using the I2C bus in End
of Line cases. When the voltage on the ISET pin is pulled
higher than 2.5 V, the device can be set in OTP control mode
via the I2C bus. During normal mode where only an external
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8
NCV7685
wired−AND function. Data on the I2C bus can be transferred
up to 400 kb/s.
Diagnostic Enabling (DIAGEN)
The device is capable to detect for each independent
channel an open load condition. Versus the number of LEDs
and the Vstring voltage supply, a wrong open load condition
can be detected if the fault detection is activated when there
is not enough voltage across the LEDs. This threshold can
be programmable thanks to an external divider connected to
the DIAGEN pin. When the divided voltage is below a
typical value of 2 V, the LED diagnostic is disabled. When
the divided voltage is above the typical value of 2 V, the LED
diagnostic is enabled.
Diagnostic Feedback (DIAG)
The DIAG is an open drain output pin who can alert a
microcontroller as soon as one of the outputs is in error mode
(DIAG Low = open load or thermal shut−down or ISET
shorted). Forcing the DIAG pin below 1.8 V will force a
fault condition if the DIAGEN input pin is above a typical
value of 2 V. If the DIAGEN input pin is below the typical
value of 2 V then forcing the DIAG input pin will not have
any effect.
Due to certain sensitivity on the DIAG pin during the
startup, it is recommended to have the pull−up resistor
connected to the VCC supply. In case if the application
deviate from the proposal mentioned in the Figure 4 or
Figure 5, the power−up sequence has to follow the timing
diagrams in the Figure 8 or Figure 9.
Figure 9. Power−up Sequence for DIAG pin. VDD is
supplied first, VS comes up later or equal.
Parallel Outputs
The maximum rating per output is 60 mA. In order to
increase system level LED string current, parallel
combinations of any number of outputs is allowed.
Combining all 12 outputs will allow for a maximum system
level string current design of 720 mA.
Required Time Delay for OTP Zapping
As soon as the ID_LOCK_OTP message is received, the
I2C acknowledge is immediately sent out to the MCU.
However, the internal circuitries still requires 500 ms time
delay to complete the OTP zapping of one OTP bit.
Therefore, no I2C confirmation is send. The number of OTP
bits that are zapped corresponds with each change from the
default values. It is needed 16.5 ms in total to successfully
finish the zapping sequence of all 32 customer bits + one
internal bit. The verification of the OTP banks can be done
by readout of the ID_READ_OTP I2C message after
zapping delay.
5V
VS
DIAG
*) VCC is internally
derived from VS
VCC
VDD
tsetupISET is up to 50 ms t ≥ 0 ms
Figure 8. Power−up Sequence for DIAG pin. VS is
supplied first, VDD comes up later.
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9
NCV7685
V BAT
VSUPPLY
MRA4003T3G
C1
100nF
LDO
or
DC/DC
Open Drain
GPIO structure
I2C
{
Micro−
controller
C VDD
100nF
VCC
VS
OUT1
VDD
ROEN
NCV7685
59K OEN
SCL
SDA
CONF
COEN
EP GND GNDP
100nF
R6
R5
4.7K 4.7K
This GND−track is exclusively for
COEN connection. (to avoid
common impedance coupling from
other GND−currents)
COUT12
(optional)
1nF
OUT12
Iset
C2
1nF
R1
2.2K
VCC_U1
_
R4
R2
100K
10K
DIAG
DIAGEN
C DIAG
R3
33nF
2.2K
U1
COUT1
(optional)
1nF
C1
100nF
To VDD supply
ROEN
59K
CVDD
100nF
To MCU
C OEN
100nF
VCC
VS
VDD
OUT1
ctrl
OUT12
Iset
NCV7685
OEN
SCL
SDA
CONF
EP GND GNDP
This GND−track is exclusively
for COEN connection. (to avoid
common impedance coupling from
other GND−currents)
DIAG
Figure 10. Example of using Multiple NCV7685 Drivers Controlled from One MCU
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10
COUT12
(optional)
1nF
R1
2.2K
mA
3.3V/5V
LDO
R7
5K
V SUPPLY
COUT1
(optional)
1nF
VCC_U1
C2
1nF
V STRING
VSTRING
DIAG
DIAGEN
U2
C DIAG
(optional)
1nF
R2
10K
R3
2.2K
NCV7685
DIGITAL PART AND I2C REGISTERS
The I2C bus consists of two wires, serial data (SDA) and
serial clock (SCL), carrying information between the
devices connected on the bus. Each device connected to the
bus is recognized by a unique address. The NCV7685 can
both receive and transmit data with CRC8 error detection
algorithm. The NCV7685 is a slave device only. Generation
of the signals on the I2C bus is always the responsibility of
the master device.
They are multiple kinds of message structure possible
versus ID code received.
Table 7. IDENTIFIER ADDRESSING (ID) MESSAGE
Name
ID
Access type
ID_I2C_CONF
00
W
I2C_CONF
Name of Register Addressed
ID_PWM
01
W
PWM_DUTY
ID_PWM_CONF
02
W
PWM_CONF, PWM_DUTY_EN
ID_PWM_ALL
03
W
PWM_D1, PWM_D2, PWM_D3, PWM_D4, PWM_D5, PWM_D6,
PWM_D7, PWM_D8, PWM_D9, PWM_D10, PWM_D11, PWM_D12
ID_WRITEALL
04
W
I2C_CONF, PWM_CONF, PWM_DUTY_EN
ID_STATUS
08
R
I2C_STATUS
ID_FAULT
09
R
FAULT_STATUS
ID_READALL
0A
R
I2C_CH_STATUS, I2C_STATUS, FAULT_STATUS
ID_SET_OTP
20
W
SAM_CONF_1, SAM_CONF_2, ADD_SAM_SET
ID_LOCK_OTP
21
W
SAM_CONF_1, SAM_CONF_2, ADD_SAM_SET
ID_READ_OTP
28
R
ID_VERS_1, ID_VERS_2, SAM_CONF_1, SAM_CONF_2, ADD_SAM_SET
Volatile Registers:
I2C_CONF
I2C_STATUS
I2C_CH_STATUS
FAULT_STATUS
PWM_DUTY
PWM_D1 − PWM_D12
PWM_DUTY_EN
PWM_CONF
There are 3 kinds of registers, Hard Coding, OTP and
volatile registers.
Hard Coding Registers:
ID_VERS_1
ID_VERS_2
OTP Registers:
ADD_SAM_SET
SAM_CONF_1
SAM_CONF_2
Format of the I2C frames
S
NCV7685 address
0
A
NCV7685 address
A
ID
A
Data
A
CRC
Data
A
A
P
N bytes +
acknowledge
‘0’ = Write
S = Start condition
P = Stop condition
A = Acknowledge
A* = Not acknowledge
From master to NCV7685
From NCV7685 to master
Figure 11. Format of I2C Write Access Frames
S
NCV7685
address
0 A
NCV7685
address
A
ID
A
CRC
A* Sr
‘0’ = Write
NCV7685
address
1 A
‘1’ = Read
From master to NCV7685
S = Start condition
N bytes +
acknowledge
Sr = Repeated start condition
P = Stop condition
From NCV7685 to master
A = Acknowledge
A* = Not acknowledge
Figure 12. Format of I2C Read Access Frames
Remark: CRC byte is not transmitted when CRC
protection is turned off (ERREN = 0)
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11
CRC
A* P
Figure 13. Format of I2C Frames
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12
NCV7685 address
NCV7685 address
NCV7685 address
S NCV7685 address 0
NCV7685 address
S NCV7685 address 0
S NCV7685 address 0
NCV7685 address
S NCV7685 address 0
S NCV7685 address 0
NCV7685 address
S NCV7685 address 0
ID_READ_OTP
ID_LOCK_OTP
ID_SET_OTP
CRC
CRC
CRC
CRC
PWM_D9
PWM_D10
PWM_D11
PWM_D5
P
From NCV7685 to master
From master to NCV7685
ID_VERS_1
From NCV7685 to master
From master to NCV7685
Sr NCV7685 address 1
CRC
CRC
P
P
P
P
CRC
P
ADD_SAM_SET
FAULT_STATUS[15:8] FAULT_STATUS[7:0]
CRC
PWM_D12
PWM_D6
SAM_CONF_1[15:8] SAM_CONF_1[7:0] SAM_CONF_2[15:8] SAM_CONF_2[7:0]
Acknowledges are ommited
S = Start condition
Sr = Repeated start condition
P = Stop condition
ID_VERS_2
ADD_SAM_SET
ADD_SAM_SET
Acknowledges are ommited
S = Start condition
Sr = Repeated start condition
P = Stop condition
CRC
CRC
PWM_DUTY_EN[15:8] PWM_DUTY_EN[7:0]
P
I2C_STATUS
SAM_CONF_1[15:8] SAM_CONF_1[7:0] SAM_CONF_2[15:8] SAM_CONF_2[7:0]
CRC
CRC
PWM_D4
Sr NCV7685 address 1 I2C_CH_STATUS[15:8] I2C_CH_STATUS[7:0]
I2C_STATUS
PWM_CONF
P
Sr NCV7685 address 1 FAULT_STATUS[15:8] FAULT_STATUS[7:0]
Sr NCV7685 address 1
I2C_CONF[7:0]
PWM_D3
SAM_CONF_1[15:8] SAM_CONF_1[7:0] SAM_CONF_2[15:8] SAM_CONF_2[7:0]
ID_READALL
ID_FAULT
ID_STATUS
I2C_CONF[15:8]
PWM_D8
ID_WRITEALL
P
PWM_DUTY_EN[15:8] PWM_DUTY_EN[7:0]
PWM_D7
NCV7685 address
S NCV7685 address 0
PWM_CONF
...
NCV7685 address
CRC
I2C_CONF[7:0]
PWM_D2
ID_PWM_CONF
NCV7685 address
S NCV7685 address 0
S NCV7685 address 0
PWM_DUTY
I2C_CONF[15:8]
PWM_D1
ID_PWM
NCV7685 address
S NCV7685 address 0
ID_PWM_ALL
ID_I2C_CONF
NCV7685 address
S NCV7685 address 0
CRC
CRC
P
P
NCV7685
Figure 14. Format of I2C OTP Frames
NCV7685
There is a safety mechanism implemented by repeating
the address. Since the I2C address is 7 bits long, first bit of
the second address byte starts with a “0” in the repeated byte
(see tables below).
Table 8.
1st byte
7
6
5
4
I2C
3
2
1
0
device Address
R/W Bit
2nd byte
7
6
5
4
3
2
1
0
I2C device Address
CRC ERROR DETECTION ALGORITHM
0
Example of the CRC used in the I2C message with
I2C_CONF byte = 0xCFFF and with I2C address 0x60
(0xC0) is 0x2E.
The CRC protection is turned off by default. It can be
enabled by activation of the OTP ERREN bit (ERREN = 1).
The every I2C byte including both addresses with R/W flag
are calculated using CRC8 algorithms. The CRC
polynomial is following: x8 + x5 + x3 + x2 + x + 1.
HARD CODING REGISTERS
Table 9. HARD CODING REGISTERS
Bit
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
ID_VERS_1
Access type
Bit name
Reset value
ID1[7:0]
0
1
0
0
0
0
1
1
R
R
R
R
R
R
R
R
0
0
0
0
0
1
0
0
ID_VERS_2
Access type
Bit name
Reset value
ID2[7:0]
1. ID1[7:0] = 43h (ON Semiconductor device identifier)
ID2[7:0] = 04h (The actual version)
OTP REGISTERS
Table 10. ADD_SAM_SET
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Access type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AUTOR
DETONLY
ERREN
0
1
0
0
0
Bit name
Reset value
ADD[4:0]
0
0
0
DETONLY: When DETONLY=1, open load diagnostic is
performed. When a fault is detected, the DIAG pin is set
without taking any action on the current regulation. When
fault is recovered, DIAG is reset. If the DIAG pin is
triggered externally, no action is taken.
When AUTOR = DETONLY = 0, no diagnostic performed
When AUTOR = DETONLY = 1, no change
(same as previously setting).
ERREN: When ERREN = 1, CRC error detection
algorithm is activated for I2C communication.
ADD[4:0] are the programmable BUS address registers
(in I2C mode ADD[6:5] = 11).
AUTOR: When AUTOR=1 (and DIAGEN is high), open
load diagnosis is performed. When a fault is detected, the
DIAG pin is set and LED driver imposes a low current on the
faulty branch alone, switching off the others. When fault is
recovered, LED driver returns to normal operation after
resetting the DIAG pin. If the DIAG pin is triggered
externally, LED driver outputs are switched off and the low
power mode is entered.
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13
NCV7685
Table 11. SAM_CONF
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit name
−
−
−
−
Reset value
0
0
0
0
0
0
0
0
0
Access type
R
R
R
R
R/W
R/W
R/W
R/W
R/W
Bit name
−
−
−
−
Reset value
0
0
0
0
SAM_CONF_1
SAM1conf[11:0]
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
SAM_CONF_2
SAM2conf[11:0]
1
1
1
1
1
1
1
1. SAM1conf[x] = 0 means channel is OFF and SAM1conf[x] = 1 means channel is ON
SAM2conf[x] = 0 means channel is OFF and SAM2conf[x] = 1 means channel is ON
VOLATILE REGISTERS
Table 12. I2C_CONF
Bit
Access type
Bit name
Reset value
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
I2CFLAG
I2CautoR
I2CdOnly
PWMEN
0
0
0
0
0
0
0
0
0
I2Cconf[11:0]
0
0
0
0
0
0
0
I2CdOnly: When I2CdOnly =1, open load diagnostic is
performed. When a fault is detected, the DIAG pin is set
without taking any action on the current regulation. When
fault is recovered, DIAG is reset. If the DIAG pin is
triggered externally, no action is taken.
When I2CautoR = I2CdOnly = 0, no diagnostic
performed.
When I2CautoR = I2CdOnly = 1, no change (same as
previously setting).
PWMEN: When PWMEN = 1, PWM is activated, when
PWMEN = 0 the content of the complete register
PWM_DUTY_EN is not reset and PWM is disabled.
I2Cconf[x] = 0 means channel is OFF and I2Cconf[x] = 1
means channel is ON.
I2CFLAG: the I2CFLAG should be reset whenever
standalone mode is entered. When I2CFLAG=1 and when
VDD is high, the I2C mode is activated, in all other
conditions the device is in Stand Alone Mode.
I2CautoR: When I2CautoR=1 (and DIAGEN is high),
open load diagnosis is performed. When a fault is detected,
the DIAG pin is set and LED driver imposes a low current
on the faulty branch alone, switching off the others. When
fault is recovered, LED driver returns to normal operation
after resetting the DIAG pin. If the DIAG pin is triggered
externally, LED driver outputs are switched off and the low
power mode is entered. Whenever the device is configured
in autorecovery (AUTOR in standalone mode or I2CautoR
in I2C mode), it is not allowed to put PWMDUTY = 0 or
PWMDx = 0 to a channel which has detected an open load.
Table 13. I2C_STATUS
Bit
Access type
Bit name
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
SC_Iset
I2Cerr
UV
diagRange
TW
TSD
DIAGERR
OL
0
0
0
0
0
0
0
0
diagRange: when diagRange = 1 the divided voltage is
above the typical value of 2 V (LED diagnostic is enabled),
diagRange = 0 means the divided voltage is below the
typical value of 2 V (LED diagnostic is disabled).
TW: when TW=1 the device is in the thermal warning
range (typ 140°C), this flag is just a warning no action is
foreseen on the output drivers. TW=0 means the device is
below the thermal warning range.
SC_Iset: SC_Iset = 1 means there is short−circuit on the
external resistor on ISET pin and drivers are switched OFF
and DIAG pin is set. SC_Iset=0 no short−circuit.
I2Cerr: I2Cerr=1 means an error has been detected during
the I2C communication, I2Cerr=0 means no error during
I2C communication has been detected.
UV: the device is in under voltage condition (VS is below
VSUV threshold, all channels OFF).
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14
NCV7685
TSD: when TSD = 1 the device is in the Thermal shutdown
range, TSD = 0 means the device is below the thermal
shutdown range.
DIAGERR: DIAGERR = 1 means an error is detected by
DIAG pin forced externally.
OL: OL = 1 means at least one channel is in Open Load
condition, OL = 0 no Open Load.
Table 14.
set when a short−circuit on the external resistor on ISET pin, latched if permanent after 10 ms.
Reset in case of short−circuit disappear permanently for at least 10ms.
SC_Iset
set if an error has been detected during the I2C communication.
Reset on register reading.
I2Cerr
set when device is in under voltage condition (VS is below VSUV, all channels OFF).
UV
set when divided voltage is above the VDiagenTH threshold.
Reset when the divided voltage is below the VDiagenTH threshold.
diagRange
TW
set when junction temperature is above the Tjwar_on threshold.
Reset on register reading AND temperature is below the (Tjwar_on − Tjsd_hys) threshold
TSD
set when junction temperature is above the TSD threshold.
Reset on register reading AND temperature is below the TSD − Tjsd_hys) threshold
set by DIAG pin forced low externally, latched if permanent after 10 ms.
Reset in case DIAG pin is not forced permanently for at least 10 ms.
DIAGERR
set in Open Load condition and DIAGEN is high, latched if permanent after 10 ms.
Reset if Open Load disappear permanently for at least 10 ms.
Fault information is maintained on falling DIAGEN threshold exceeded
OL
Table 15. I2C_CH_STATUS
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
I2CFLAG
I2CautoR
I2CdOnly
PWMEN
0
0
0
0
0
0
0
0
Access type
Bit name
Reset value
I2C_CH_STATUS[11:0]
0
0
0
0
0
0
0
0
Remark: When NCV7685 is configured in I2C mode and
output channel OUTx is configured to operate in PWM
mode, I2C_CH_STATUS[x] shall contain value ‘1’.
I2CFLAG: same as I2C_CONF register
I2CautoR: same as I2C_CONF register
I2CdOnly: same as I2C_CONF register
PWMEN: same as I2C_CONF register
I2C_CH_STATUS[11:0]: same as I2C_CONF[11:0] bits
in I2C mode or same as SAM_CONF_1[11:0],
SAM_CONF_2[11:0] bits in Standalone mode.
Table 16. FAULT_STATUS
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit name
−
−
−
−
Reset value
0
0
0
0
0
0
0
0
0
FAULT[11:0]
0
0
0
0
FAULT[11:0]: when FAULT[x] = 1 the OUTx channel is
in fault mode (Open Load latched when the duration is
longer than 10 ms), when FAULT[x] = 0 the OUTx channel
0
0
0
is working properly. The register is reset on each read
operation.
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15
NCV7685
Table 17. PWM_DUTY
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Access type
−
W
W
W
W
W
W
W
Bit Name
−
Reset Value
0
0
0
0
PWMDUTY[6:0]
0
0
0
0
When PWMDUTY = 0 all channels are switched off.
Whenever the device is configured in autorecovery
(AUTOR in standalone mode or I2CautoR in I2C mode), it
is not allowed to put PWMDUTY = 0 or PWMDx = 0 to a
channel which has detected an open load.
Transmitting PWM_DUTY via I2C will cause setting the
value to all channels.
PWMDUTY[6:0]: logarithmic (or linear) common
dimming for all channels via embedded PWM generator
(128 steps). Following formula applies when logarithmic
dimming is selected: Duty_Cycle_Percent = 100 × α(N−i)
where α = 0.9471 and N = 127 rounded with an accuracy
of 400 ns.
When PWMDUTY = 127 all channels ar fully switched
on.
Table 18. PWM_Dx
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Access type
−
W
W
W
W
W
W
W
Bit Name
−
Reset Value
0
0
0
0
PWMDx[6:0]
0
0
0
0
Whenever the device is configured in autorecovery
(AUTOR in standalone mode or I2CautoR in I2C mode), it
is not allowed to put PWMDUTY = 0 or PWMDx = 0 to a
channel which has detected an open load.
To set independent PWM Duty Cycle value to each
channel simultaneously, all twelve PWM_Dx bytes has to be
transferred via I2C bus in ID_PWM_ALL message. If
PWM_DUTY register is updated, all PWM_Dx bytes will
be overwritten by the same value from PWM_DUTY
register.
PWMDx[6:0]: logarithmic (or linear) independent PWM
dimming for each OUTx channel via embedded PWM
generator (128 steps). Following formula applies when
logarithmic dimming is selected: Duty_Cycle_Percent =
100 × α(N−i) where α = 0.9471 and N = 127 rounded with
an accuracy of 400 ns.
When PWMDx = 127 the OUTx channel is fully switched
on.
When PWMDx = 0 the OUTx channel is switched off.
Table 19. PWM_DUTY_EN
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
−
−
−
−
W
W
W
W
W
W
W
W
W
W
W
W
Bit name
−
−
−
−
Reset value
0
0
0
0
0
0
0
0
0
PWMDUTYen[11:0]
0
0
0
0
PWMDUTYen[11 :0] : when PWMDUTYen[x] = 1,
PWM dimming is enabled for OUTx channel, when
PWMGAINen[x] = 0 means PWM dimming is disabled for
0
0
0
OUTx channel. When the PWM dimming is disabled, the
output channel is programmed according to the I2Cconf[x]
settings.
Table 20. PWM_CONF
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Access type
W
W
W
W
W
W
W
W
Bit Name
−
−
−
−
−
PWMLIN
PWMF2
PWMF1
Reset Value
0
0
0
0
0
0
0
0
PWMLIN bit shall select between between logarithmic
(PWMLIN=0) and linear (PWMLIN=1) translation of
PWMDUTY bits to duty cycle of internal PWM signal.
PWMF2 and PWMF1 bits set typical PWM frequency
settings according to the Table 21.
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16
NCV7685
Table 21. TYPICAL PWM FREQUENCY SETTINGS
PWMF2
PWMF1
typ. PWM frequency [Hz]
0
0
150
0
1
300
1
0
600
1
1
1200
Figure 15. Output Duty Cycle vs. Register Setting
Figure 16. Output Duty Cycle vs. Register Setting
− Detail
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
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17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SSOP−24 NB EP
CASE 940AQ
ISSUE O
SCALE 1:1
DATE 18 AUG 2017
2X
0.20 C A-B
NOTE 4
NOTE 6
D
D
A
2X
L1
H
13
24
L2
0.20 C
NOTE 5
E1
ÉÉ
ÉÉ
PIN 1
REFERENCE
e
GAUGE
PLANE
E
L
DETAIL A
A1
C
NOTE 7
1
12
B
24X
NOTE 6
TOP VIEW
SEATING
PLANE
0.20 C
b
0.12
2X 12 TIPS
M
C A-B D
DETAIL A
A
A2
0.10 C
h
h
M
0.10 C
24X
SIDE VIEW
0.15
M
C A-B D
A1
C
SEATING
PLANE
c
END VIEW
NOTE 8
D2
0.15
E2
M
C A-B D
NOTE 8
BOTTOM VIEW
24X
1.15
2.20 6.40
1
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
--1.75
0.00
0.10
1.10
1.65
0.19
0.30
0.09
0.20
8.64 BSC
2.50
2.70
6.00 BSC
3.90 BSC
1.80
2.00
0.65 BSC
0.25
0.50
0.40
0.85
1.00 REF
0.25 BSC
0_
8_
XXXXXXXXXG
AWLYYWW
3.00
0.40
DIM
A
A1
A2
b
c
D
D2
E
E1
E2
e
h
L
L1
L2
M
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
24X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
BE 0.10 MAX. AT MMC. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OF THE
FOOT. DIMENSION b APPLIES TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.10 TO 0.25
FROM THE LEAD TIP.
4. DIMENSION D DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 PER SIDE. DIMENSION D IS
DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25 PER
SIDE. DIMENSION E1 IS DETERMINED AT DATUM PLANE H.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
8. CONTOURS OF THE THERMAL PAD ARE UNCONTROLLED WITHIN THE REGION DEFINED
BY DIMENSIONS D2 AND E2.
98AON73645G
SSOP−24 NB EP
XXXX = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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