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product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
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regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
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NCV7718B, NCV7718C
Hex Half-Bridge Driver
The NCV7718B/C is a Hex Half−Bridge Driver with protection
features designed specifically for automotive and industrial motion
control applications. The NCV7718B/C has independent controls and
diagnostics. The device can be operated in forward, reverse, brake,
and high impedance states. The drivers are controlled via a 16 bit SPI
interface and are daisy chain compatible.
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Features
• Low Quiescent Current Sleep Mode
• High−Side and Low−Side Drivers Connected in a Half−Bridge
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Configuration
Integrated Freewheeling Protection (LS and HS)
0.55 A Peak Current
RDS(on) = 1 W (typ)
5 MHz SPI Control
Compliance with 5 V and 3. 3 V Systems
Undervoltage and Overvoltage Lockout
Discriminated Fault Reporting
Overcurrent Protection
Overtemperature Protection
Under Load Detection (LS)
Daisy Chain Compatible with Multiple of 8 bit Devices
16−Bit Frame Detection
Available SSOP24 Package Options:
♦ NCV7718B, NCV7718C − Exposed Pad Package
♦ NCV7718C − Standard Package
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
SSOP−24 NB
DP SUFFIX
CASE 565AL
SSOP24 NB EP
DQ SUFFIX
CASE 940AK
MARKING DIAGRAM
NCV7718x
AWLYWWG
NCV7718x = Specific Device Code
(x = B or C)
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 26 of this data sheet.
Typical Applications
• Automotive
• Industrial
• DC Motor Management for HVAC Application
© Semiconductor Components Industries, LLC, 2014
October, 2018 − Rev. 3
1
Publication Order Number:
NCV7718B/D
NCV7718B, NCV7718C
Shown below is a typical application for the NCV7718B/C configuration.
MRA4003T3
Watchdog
13.2V
NCV7718B/C
Power On
Reset
SO
SI
16−Bit
Serial
Data
Interface
SCLK
CSB
uC
Logic
Control
Protection:
Under Load
Over Temperature
Under−voltage
Over−voltage
Over Current
VS1
VS2
GND
EN
GND
GND
Voltage
Regulator
High
Side
Switch
High
Side
Switch
High
Side
Switch
High
Side
Switch
High
Side
Switch
High
Side
Switch
Low
Side
Switch
Low
Side
Switch
Low
Side
Switch
Low
Side
Switch
Low
Side
Switch
Low
Side
Switch
VCC
OUT1
OUT2
OUT3
OUT4
Figure 1. Typical Application
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2
OUT5
OUT6
GND
NCV7718B, NCV7718C
VS1
DRIVE1
VS
EN
ENABLE
High Side
Driver
VS
Vcc
Vref1
POR
BIAS
Vref2
Fault
Reporting
Wave Shaping
OUT1
Control
Logic
Wave Shaping
VS
Low Side
Driver
SO
SPI
SCLK
LS Underload
16 Bit Logic
and Latch
Fault
SI
Overcurrent
Thermal Warning &
Shutdown
CSB
VS
VS
DRIVE2
OUT2
DRIVE3
OUT3
DRIVE4
OUT4
DRIVE5
OUT5
DRIVE6
OUT6
VS1 & VS2
Vref1
Over Voltage
Lockout
VS
VS
VS1 & VS2
Vref2
Under Voltage
Lockout
VS
GND GND GND GND
VS2
Figure 2. Block Diagram
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3
NCV7718B, NCV7718C
GND
1
24
GND
OUT1
2
23
OUT2
OUT5
3
22
NC
NC
4
21
VS1
SI
VCC
5
20
SCLK
6
19
CSB
SO
7
18
RESERVED
EN
8
17
RESERVED
NC
9
16
VS2
OUT6
10
15
NC
OUT4
11
14
OUT3
GND
12
13
GND
Figure 3. Pinout − SSOP24 NB and SSOP24 NB EP (Top View)
PACKAGE PIN DESCRIPTION: SSOP24 NB, SSOP24 NB EP
Pin #
Symbol
Description
1
GND
Ground. Shorted to pin 24 internally.
2
OUT1
Half Bridge Output 1
3
OUT5
Half Bridge Output 5
4
NC
No Connection. This pin should be isolated from any traces or via on the PCB board.
5
SI
Serial Input. 16 bit serial communications input. 3.3 V/5 V (TTL) Compatible. Internally pulled down.
6
VCC
7
SO
Serial Output. 16 bit serial communications output. 3.3 V/5 V Complaint
8
EN
Enable. Input high wakes the IC up from a sleep mode. 3.3 V/5 V (TTL) Compatible. Internally pulled down.
9
NC
No Connection. This pin should be isolated from any traces or via on the PCB board.
10
OUT6
Half Bridge Output 6
11
OUT4
Half Bridge Output 4
12
GND
Ground. Shorted to pin 13 internally.
13
GND
Ground. Shorted to pin 12 internally.
14
OUT3
Half Bridge Output 3
15
NC
No Connection. This pin should be isolated from any traces or via on the PCB board.
16
VS2
Voltage Power Supply input for the Drivers 3, 4 and 6. This pin must be connected to VS1 externally.
17
Reserved
Factory use − connect to GND or leave unconnected − internally pulled down.
18
Reserved
Factory use − connect to GND or leave unconnected − internally pulled down.
19
CSB
Chip Select Bar. Active low serial port operation. 3.3V/5V (TTL) Compatible. Internally pulled up.
20
SCLK
Serial Clock. Clock input for use with SPI communication. 3.3 V/5 V (TTL) Compatible. Internally pulled down.
21
VS1
Voltage Power Supply input for the Drivers 1, 2 and 5, all the pre−drivers and the charge pump. This pin
must be connected to VS2 externally.
22
NC
No Connection. This pin should be isolated from any traces or via on the PCB board.
23
OUT2
Half Bridge Output 2
24
GND
Ground. Shorted to pin 1 internally.
EPAD
Exposed Pad
Power supply input for Logic.
Connect to GND or leave unconnected (SSOP24 NB EP package option).
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4
NCV7718B, NCV7718C
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage (VS1, VS2)
(DC)
(AC), t < 500ms, Ivsx > −2A
VsxdcMax
VSXac
Output Pin OUTx
(DC)
(AC), t< 500ms, IOUTx > −1.1A
(AC), t< 500ms, IOUTx < 1A
VoutxDc
VoutxAc
Pin Voltage (Logic Input pins, SI, SCLK, CSB, SO, EN, VCC)
VioMax
−0.3 to 5.5
V
Output Current (OUT1, OUT2, OUT3, OUT4, OUT5, OUT6)
IoutxImax
−2.0 to 2.0
A
Electrostatic Discharge, Human Body Model, VSx, OUTx (AEC−Q100−002)
Vesd4k
≥ ±4.0
kV
Electrostatic Discharge, Human Body Model, all other pins (AEC−Q100−002)
Vesd2k
≥ ±2.0
kV
Electrostatic Discharge, Charged Device Model (AEC−Q100−011)
VesdCDM
Level C4B
−
Short Circuit Reliability Characterization
AECQ10x
Grade A
−
Tj
−40 to 150
°C
Storage Temperature Range
Tstr
−55 to 150
°C
Moisture Sensitivity Level (MAX 260°C Processing)
SSOP24 NB, SSOP24 NB EP
MSL
2
−
Operating Junction Temperature
V
−0.3 to 40
−1.0
V
−0.3 to 40
−1.0
1.0
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
THERMAL INFORMATION (Note 1)
Rating
Package Thermal Resistance − Still−air
Junction−to−Ambient
Junction−to−Board
Junction−to−Lead
1.
2.
3.
4.
Symbol
(Note 2)
(Note 3)
(Note 4)
(Note 2)
(Note 3)
(Note 4)
RqJA
RqJA
RqJA
RyJBOARD
RyJBOARD
RyJL
SSOP24 NB EP
SSOP24 NB
56
22
−
28
12
−
−
−
95
−
−
62
Unit
°C/W
Thermal Information is based on having 3 high side and 3 low side drivers dissipating 80 mW each.
2S0P 2−layer PCB based on JESD51−3, 1.2 mm thick FR4, with 2 oz. copper and 18 thermal vias to 600 mm2 spreader on bottom layer.
2S2P 4−layer PCB based on JESD51−7, 1.2 mm thick FR4, with 2 oz. copper and 18 thermal vias to 80x80 mm 1 oz. internal planes.
2S0P 2−layer PCB based on JESD51−3, 1.2 mm thick FR4, with 2 oz. copper to 600 mm2 spreader on top layer.
RECOMMENDED OPERATING CONDITIONS
Value
Symbol
Min
Max
Unit
Digital Supply Input Voltage
VccOp
3.15
5.25
V
Battery Supply Input Voltage
VsxOp
5.5
28
V
DC Output Current
IxOp
−
0.55
A
Junction Temperature
TjOp
−40
125
°C
Rating
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
NCV7718B, NCV7718C
ELECTRICAL CHARACTERISTICS
(−40°C < TJ < 150°C, 5.5 V < VSx < 40 V, 3.15 V < VCC < 5.25 V, EN = VCC, unless otherwise specified)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
Supply Current (VS1 + VS2)
Sleep Mode
IqVsx85
VS1 = VS2 = 13.2 V, VCC = 0 V −40°C to 85°C
No Load
−
1.0
2.5
mA
Supply Current (VS1 + VS2)
Active Mode
IvsOp
EN = VCC, 5.5 V < VSx < 28 V No Load
−
2.5
5.0
mA
IqVCC
CSB = VCC, EN = SI = SCLK = 0 V
(−40°C to 85°C)
EN = CSB = VCC, SI = SCLK = 0 V
No Load
−
1.0
2.5
mA
−
1.5
3.0
mA
Sleep Mode, −40°C to 85°C, No Load
−
2
5
mA
GENERAL
Supply Current (VCC)
Sleep Mode
Active Mode
Total Sleep Mode Current
I(VS1) + I(VS2) + I(VCC)
IVCCOp
IqTot
VCC Power−On−Reset Threshold
VCCpor
VCC increasing
−
2.55
2.9
V
VSx Undervoltage Detection
Threshold
VsXuv
VSx decreasing
3.7
4.1
4.5
V
VSx Undervoltage Detection
Hysteresis
VsXuHys
100
−
450
mV
VSx Overvoltage Detection
Threshold
VsXov
32
36
40
V
VSx Overvoltage Detection
Hysteresis
VsXoHys
1
2.5
4
V
120
140
170
°C
VSx increasing
THERMAL RESPONSE
Thermal Warning
Twr
Not ATE tested
TwHy
Not ATE tested
−
20
−
°C
Tsd
Not ATE tested
150
175
200
°C
TsdHy
Not ATE tested
−
20
−
°C
RDSonHS
Iout = −500 mA, VSx = 13.2 V, VCC = 3.15 V
−
1
2.25
W
Output Low RDS(on) (sink)
RDSonLS
Iout = 500 mA, VSx = 13.2 V, VCC = 3.15 V
−
1
2.0
W
Output Path RDS(HSx+LSx)
RDSonPath
Iout = ⎮500⎜ mA
−
−
4.0
IsrcLkg13.2
IsrcLkg28
VCC = 5 V, OUT(1−6) = 0 V, −40°C to 85°C;
VSx = 13.2 V
VSx = 28 V
IsnkLkg13.2
IsnkLkg28
Overcurrent Shutdown Threshold (Source)
Overcurrent Shutdown Threshold (Sink)
Thermal Warning Hysteresis
Thermal Shutdown
Thermal Shutdown Hysteresis
OUTPUTS
Output High RDS(on) (source)
Source Leakage Current
Sink Leakage Current
W
mA
−1.0
−2.0
−
−
−
−
VCC = 5 V;
OUT(1−6) = VSx = 13.2 V
OUT(1−6) = VSx = 28 V
−
−
−
−
1.0
2.0
IsdSrc
VCC = 5 V, VSx = 13.2 V
−2.0
−1.2
−0.8
A
IsdSnk
VCC = 5 V, VSx = 13.2 V
0.8
1.2
2.0
A
10
25
50
ms
mA
Over Current Delay Timer
TdOc
Under Load Detection Threshold (Low Side)
IuldLS
VCC = 5 V, VSx = 13.2 V
2.0
11
20
mA
Under Load Detection Delay
Time
TdUld
VCC = 5 V, VSx = 13.2 V
200
350
600
ms
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6
NCV7718B, NCV7718C
ELECTRICAL CHARACTERISTICS
(−40°C < TJ < 150°C, 5.5 V < VSx < 40 V, 3.15 V < VCC < 5.25 V, EN = VCC, unless otherwise specified)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
−
0.9
1.3
V
2.0
−
−
−
−
0.6
BODY DIODE
Power Transistor Body Diode
Forward Voltage
VbdFwd
If = 500 mA
LOGIC INPUTS (EN, SI, SCLK, CSB)
Input Threshold
High
Low
VthInH
VthInL
V
Input Hysteresis (SI, SCLK,
CSB)
VthInHys
50
150
300
mV
Enable Hysteresis
VthENHys
150
400
800
mV
EN = SI = SCLK = VCC
50
125
200
kW
CSB = 0 V
50
125
250
kW
Cinx
Not ATE tested
−
−−
15
pF
Output High
VsoH
ISOURCE = −1 mA
VCC –
0.6
−
−
V
Output Low
VsoL
ISINK = 1.6 mA
−
−
0.4
V
Input Pull−down Resistance
(EN, SI, SCLK)
Input Pull−up Resistance
(CSB)
Input Capacitance
Rpdx
RpuCSB
LOGIC OUTPUT (SO)
Tri−state Leakage
ItriStLkg
CSB = 5 V
−5
−
5
mA
Tri−state Output Capacitance
ItriStCout
CSB = VCC, 0 V < VCC < 5.25 V
Not ATE tested
−
−
15
pF
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7
NCV7718B, NCV7718C
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 5.5 V < VSx < 40 V, 3.15 < Vcc < 5.25 V, EN= Vcc, unless otherwise
specified)
Characteristic
Symbol
Conditions
Timing
Chart
Min
Typ
Max
Unit
DRIVER OUTPUT TIMING SPECIFICATIONS
High Side Turn On Time
ThsOn
VSx = 13.2 V, Rload = 39 W
−
7.5
13
ms
High Side Turn Off Time
ThsOff
VSx = 13.2 V, Rload = 39 W
−
3.0
6.0
ms
Low Side Turn On Time
TlsOn
VSx = 13.2 V, Rload = 39 W
−
6.5
13
ms
Low Side Turn Off Time
TlsOff
VSx = 13.2 V, Rload = 39 W
−
2.0
6.0
ms
High Side Rise Time
ThsTr
VSx =13.2 V, Rload = 39 W
−
4.0
8.0
ms
High Side Fall Time
ThsTf
VSx = 13.2 V, Rload = 39 W
−
2.0
4.0
ms
Low Side Rise Time
TlsTr
VSx = 13.2 V, Rload = 39 W
−
1.0
3.0
ms
Low Side Fall Time
TlsTf
VSx = 13.2 V, Rload = 39 W
−
1.0
3.0
ms
High Side Off to Low Side On
Non−Overlap Time
ThsOffLsOn
VSx = 13.2 V, Rload = 39 W
1.5
−
−
ms
Low Side Off to High Side On
Non−Overlap Time
TlsOffHsOn
VSx = 13.2 V, Rload = 39 W
1.5
−
−
ms
SERIAL PERIPHERAL INTERFACE
SCLK Frequency
Fclk
VCC = 5 V
VCC = 3.15 V
−
−
−
−
5.0
2.0
MHz
SCLK Clock Period
TpClk
VCC = 5 V
VCC = 3.15 V
200
500
−
−
−
−
ns
SCLK High Time
TclkH
1
85
−
−
ns
SCLK Low Time
TclkL
2
85
−
−
ns
SCLK Setup Time
TclkSup
3
4
85
85
−
−
−
−
ns
SI Setup Time
TsiSup
11
50
−
−
ns
SI Hold Time
TsiH
12
50
−
−
ns
TcsbSup
5
6
100
100
−
−
−
−
ns
CSB High Time (Note 5)
TcsbH
7
5.0
−
−
ms
SO enable after CSB falling
edge
TenSo
VCC = 5 V
8
−
−
200
ns
SO disable after CSB rising
edge
TdisSo
VCC = 5 V
9
−
−
200
ns
CSB Setup Time
SO Rise Time
TsoR
Cload = 40 pF
Not ATE tested
−
−
10
25
ns
SO Fall Time
TsoF
Cload = 40 pF
Not ATE tested
−
−
10
25
ns
SO Valid Time
TsoV
Cload = 40 pF
SCLK ↑ to SO 50%,
Not ATE tested
10
−
20
50
ns
EN Low Valid Time (Note 6)
TenL
VCC = 5 V
EN going low 50% to
OUTx turing off 50%
10
−
−
ms
TenHspiV
−
−
100
ms
Tsrr
150
−
−
ms
EN High to SPI Valid
SRR Delay Between Two
Consecutive Frame (Note 7)
5. This is the minimum time the user must wait between SPI commands.
6. This is the minimum time the user must wait before bringing EN up.
7. This is the minimum time the user must wait to send a SRR command between consecutive frames. If Tsrr time is not met the SRR request
is ignored.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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8
NCV7718B, NCV7718C
ELECTRICAL CHARACTERISTIC TIMING DIAGRAMS
TlsTr
90%
TlsOff
10%
LS Turn OFF
TlsOff
HsOn
90%
10%
HS Turn ON
ThsTr
90%
ThsOn
CSB
LS Turn On
TlsTf
90%
TlsOn
10%
HS Turn Off
ThsOff
LsOn
90%
10%
ThsTf
90%
ThsOff
CSB
Figure 4. Detailed Driver Timing
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9
NCV7718B, NCV7718C
4
7
CSB
6
5
SCLK
3
2
1
CSB
SO
8
9
SI
12
SCLK
10
11
SO
Figure 5. Detailed SPI Timing
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10
NCV7718B, NCV7718C
5.0
4.5
VSx = 13.2 V
ACTIVE MODE VCC CURRENT (mA)
IqTot, TOTAL SLEEP MODE CURRENT (mA)
TYPICAL PERFORMANCE GRAPHS
VCC = 3.15 V
4.0
3.5
3.0
VCC = 5.25 V
2.5
2.0
VCC = 5 V
1.5
1.0
0.5
0
−50 −30 −10
10
30
50
70
90
110 130 150
25°C
2.20
2.15
2.10
−40°C
3.0
3.5
4.0
4.5
5.0
5.5
4.1
VSx = 13.2 V
I(OUTx) = 0.5 A
3.6
PATH RDS(on) (W)
RDS(on) (W)
125°C
2.25
Figure 7. I(VCC) Active Mode vs. V(VCC)
HSx
1.2
LSx
1.0
VSx = 13.2 V
I(OUTx) = 0.5 A
3.1
2.6
HSx + LSx
2.1
1.6
1.1
0.8
0
50
100
0.6
−50
150
0
50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. RDS(on) vs. Temperature
Figure 9. RDS(on) vs. Temperature
150
2.0
1.2
IsdSrc, IsdSnk OVERCURRENT (A)
BODY DIODE FORWARD VOLTAGE (V)
2.30
Figure 6. IqTot vs. Temperature
1.4
If = 0.5 A
1.1
1.0
LSx
0.9
HSx
0.8
−50
150°C
VCC VOLTAGE (V)
1.6
0.6
−50
VSx = 13.2 V
2.35
TEMPERATURE (°C)
2.0
1.8
2.40
0
50
100
1.5
0.5
0
VS = 13.2 V
VCC = 5.0 V
−0.5
−1.0
−1.5
−2.0
−50
150
LSx
1.0
HSx
0
50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. Body Diode vs. Temperature
Figure 11. Overcurrent vs. Temperature
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11
150
NCV7718B, NCV7718C
IsrcLkg, IsnkLkg LEAKAGE CURRENT (mA)
TYPICAL PERFORMANCE GRAPHS
0.2
0
HSx
LSx
−0.2
−0.4
VSx = 13.2 V
−0.6
−0.8
−1.0
−50
0
50
100
TEMPERATURE (°C)
Figure 12. Source−Sink Leakage vs.
Temperature
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12
150
NCV7718B, NCV7718C
OPERATING DESCRIPTION
General Overview
SPI Communication
The NCV7718B/C is comprised of twelve DMOS power
drivers (six PMOS High Side Driver and six NMOS Low
Side Driver) configured as six half bridges that enables three
independent Full Bridge operations. Each output drive is
characterized for a max 550 mA DC load and has a typical
2 A surge capability (at VSx =13.2 V). Strict adherence to
integrated circuit die temperature is necessary. Maximum
die temperature is 150°C. This may limit the number of
drivers enabled at one time. Output drive control and fault
reporting is handled via the SPI (Serial Peripheral Interface)
port.
An Enable function (EN) provides a low quiescent sleep
current mode when the device is not being utilized. No data
is stored when the device is in sleep mode. An internal pull
down resistor is provided on the EN input to ensure the
device is off if the input signal is lost. De−asserting the EN
signal clears all the registers and resets the driver. When the
EN signal is asserted the IC will proceed with the VCC POR
cycle and brings the drivers into normal operation.
16−bit full duplex SPI communication has been
implemented for the communication of this IC for device
configurations, driver controls and reading the diagnostic
data. In addition to the 16−bit diagnostic data, a pseudo bit
(PRE_15) can also be retrieved from the SO register. The
part is required to be enabled (EN active high) for SPI
communication. The inputs for the SPI are TTL logic
compatible and are specified by the VthInH and VthInL
thresholds. The active low CSB input has a pull up resistor
and the remaining SPI inputs have pull−down resistors to
bias them to a known state when SPI is not active.
Reference the SPI communication frame format diagram
in Figure 13 for the 16 bit SPI implementation. Tables 1
and 2 define the programming bits and diagnostic bits
shown in Figure 13.
SPI COMMUNICATION FRAME FORMAT
CSB
SSR
SI
SCLK
SO
15
TSD
OCS
HBSEL
14
PSF
ULD
HBEN6 – HBEN1
HBCNF6 – HBCNF1
OVLO
0
13
HBx[1:0]
ULD
TW
Figure 13. SPI Communication Frame Format
Communication is implemented as follows and is also illustrated in Figure 16:
1. SI and SCLK are set to low before the CSB cycle.
2. CSB goes low to allow serial data transfer.
3. SI data starting with the Most Significant bit (MSB) is shifted in first.
4. SI data is recognized on every falling edge of the clock.
5. Simultaneously, SO data from the previous frame starting with the MSB bit is shifted out on every rising edge of the
clock.
6. The input data is compared to a 16 bit counter for the initial 16 bits shifted into SI for frame detection error scheme.
7. The sequential input bits are compared to a n x 8 (n can take on the value of any integer) bit counter for daisy chain
operations and are monitored by the frame detection error scheme.
8. CSB goes high and the most recent 16 bits clocked into SI are transferred to the data register given that there is no
frame detection error. Otherwise the entire frame is ignored.
9. SO is tri−state when CSB is high.
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13
NCV7718B, NCV7718C
Table 1. SPI INPUT DATA FRAME
Input Data
Bit Number
Bit Name
Bit Description
Bit Status
15
SRR
Status Reset Register
When Asserted All Latched Faults are Cleared (TSD, OCS & ULD)
0 = No Reset
Half Bridge Selection
1 = Reset
14
HBSEL (Note 8)
Reserved
13
ULDSC
Under Load Detection Shutdown Control
Global Enable; Per Half Bridge Operation
0 = Disable
12
HBEN6
Half Bridge 6 Enable
0 = High Z
1 = Enable
1 = Enabled
11
HBEN5
Half Bridge 5 Enable
0 = High Z
1 = Enabled
10
HBEN4
Half Bridge 4 Enable
9
HBEN3
Half Bridge 3 Enable
0 = High Z
1 = Enabled
0 = High Z
1 = Enabled
8
HBEN2
Half Bridge 2 Enable
0 = High Z
1 = Enabled
7
HBEN1
6
HBCNF6
Half Bridge 1 Enable
0 = High Z
1 = Enabled
Half Bridge 6 Configuration Control
0 = LS6 ON & HS6 OFF
1 = LS6 OFF & HS6 ON
5
HBCNF5
Half Bridge 5 Configuration Control
0 = LS5 ON & HS5 OFF
1 = LS5 OFF & HS5 ON
4
HBCNF4
Half Bridge 4 Configuration Control
3
HBCNF3
Half Bridge 3 Configuration Control
0 = LS4 ON & HS4 OFF
1 = LS4 OFF & HS4 ON
0 = LS3 ON & HS3 OFF
1 = LS3 OFF & HS3 ON
2
HBCNF2
Half Bridge 2 Configuration Control
0 = LS2 ON & HS2 OFF
1 = LS2 OFF & HS2 ON
1
HBCNF1
Half Bridge 1 Configuration Control
0 = LS1 ON & HS1 OFF
1 = LS1 OFF & HS1 ON
0
OVLO
Over Voltage Lock Out
Global Effect
0 = Disable
1 = Enable
8. HBSEL enables bridge selection for the NCV7719 and NCV7720 devices. In the NCV7718B/C it is recommended to set the HBSEL to zero.
www.onsemi.com
14
NCV7718B, NCV7718C
Table 2. SPI OUTPUT DATA FRAME
Output Data
Bit Number
Bit Name
Bit Description
Bit Status
PRE_15
TSD
Latched Thermal Shutdown
0 = No Fault
1 = Fault
15
14
13
12
OCS
PSF
ULD
HBST6
Over Current Shutdown
Global Notification
0 = No Fault
Power Supply Failure on VS1 and/or VS2
Under Voltage and Over Voltage Monitoring
0 = No Fault
Under Load Detection
Global Notification
0 = No Fault
Half Bridge 6 Enable Status
0 = High Z
1 = Fault
1 = Fault
1 = Fault
1 = Enabled
11
HBST5
Half Bridge 5 Enable Status
0 = High Z
1 = Enabled
10
HBST4
Half Bridge 4 Enable Status
0 = High Z
1 = Enabled
9
HBST3
Half Bridge 3 Enable Status
0 = High Z
1 = Enabled
8
HBST2
Half Bridge 2 Enable Status
0 = High Z
1 = Enabled
7
HBST1
Half Bridge 1 Enable Status
0 = High Z
1 = Enabled
6
HBCR6
Half Bridge 6 Configuration Reporting
0 = LS6 ON & HS6 OFF
1 = LS6 OFF & HS6 ON
5
HBCR5
Half Bridge 5 Configuration Reporting
4
HBCR4
Half Bridge 4 Configuration Reporting
0 = LS5 ON & HS5 OFF
1 = LS5 OFF & HS5 ON
0 = LS4 ON & HS4 OFF
1 = LS4 OFF & HS4 ON
3
HBCR3
Half Bridge 3 Configuration Reporting
0 = LS3 ON & HS3 OFF
1 = LS3 OFF & HS3 ON
2
HBCR2
Half Bridge 2 Configuration Reporting
1
HBCR1
Half Bridge 1 Configuration Reporting
0 = LS2 ON & HS2 OFF
1 = LS2 OFF & HS2 ON
0 = LS1 ON & HS1 OFF
1 = LS1 OFF & HS1 ON
0
TW
Thermal Warning
Global Notification
0 = No Fault
1 = Fault
If the half−bridge enable status denotes a high impedance
latched thermal shutdown (TSD) information is available on
condition (HBSTx = 0), the corresponding half−bridge
SO after CSB goes low until the first rising SCLK edge. The
configuration reporting (HBCRx) should be ignored. The
following procedures must be met for a true TSD reading:
1. SCLK and SI are low before the CSB cycle. Violating these conditions will results in an undetermined SPI behavior
or/and an incorrect TSD reading.
2. CSB transitioning from high to low.
3. CSB setup time (TcsbSup) is satisfied and the data is captured before the first SCLK rising edge.
www.onsemi.com
15
NCV7718B, NCV7718C
Driver Control
The NCV7718B/C has the flexibility of controlling each
driver through the 16 bit SPI frame (Bits 12−1) and the logic
combination required for bridge control is defined in
Figure 14.
VS
HBCNFx
HSx
HBENx
OUTx
LSx
HBENx
HBCNFx
OUTx
0
‘X’
OUTx in High Impedance State
1
0
HSx Off and LSx On
1
1
HSx On and LSx Off
‘X’ = Don’t Care
Figure 14. Bridge Control Logic
Daisy Chain Operation
The digital design insures that the high side and low side
of the same half bridge will not be active at the same time.
Thus the device self protects from a current shoot through
condition. Delays (ThsOffLsOn and TlsOffHsOn) between
the high side and low side switching are implemented for
same reasons.
Daisy chain communications between multiple of 8−bit
SPI compatible IC’s is possible by connection of the serial
output pin (SO) to the input of the sequential IC (SI). The
clock phase and clock polarity respect to the data must be the
same for all the devices on the chain. Figure 15 illustrates the
hardware configuration of NCV7718B/C daisy chained
with a n*8 bit (ie n = 2; 16 bit) SPI device. The progression
of data from the MCU through the sequential devices is also
shown. Strict adherence to the frame format illustrated in
Figure 16 is required for the proper serial daisy chain
operations.
Frame Detection
To maintain the data integrity, the NCV7718B/C has 16
bit frame detection. A valid frame for a single CSB cycle
requires 16 bits to be clocked into SI for the initial 16 bits and
n x 8 bits thereafter. In an instance of an invalid SPI frame
the entire frame is ignored, but the previous states of the
corresponding outputs are maintained.
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16
NCV7718B, NCV7718C
MCU
8 bits
8 bits
8 bits
8 bits
MI
NCV7718B/C
16 Bit SPI
n*8 Bit SPI Device
(ie n=2; 16 bits)
CSB
CSB
CSB
SCLK
SCLK
SCLK
MO
Command Bits for the Device 2
Previous Diagnostic Bits from Device2
Command Bits for Device 1
Previous Diagnostic Bits From Device1
8 bits
8 bits
8 bits
8 bits
SI
SO
Device1
8 bits
8 bits
8 bits
8 bits
SI
SO
Device2
Figure 15. Serial Daisy Chain
detection counters. For these scenarios, invalid data is
accepted by NCV7718B/C and possibly by other devices on
the chain depending on their frame detection design. The
data shifted in will be transferred to the data registers of the
devices on the beginning of the chain and the devices at the
end of the chain will get the previous diagnostic data of the
preceding devices.
If Device 2 is a 16 bit IC, then a total of 32 bits must be
generated from the MCU for a complete transport of data in
the system. Monitoring of all the devices in the serial chain
must be employed on a system level architecture. Thus,
pre−cautious measure should be taken to avoid situations
where not enough frames were sent to the devices, but the
frames transmitted did not violate the internal frame
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17
NCV7718B, NCV7718C
24 bit Frame
Word B – 8 bits
Word A – 16 bits
CSB
SCLK
7
6
1
0
MSB
SI
15
8
7
0
LSB
MSB
LSB
LSB
MSB
LSB
SI data is recognized on the falling SCLK edge
.
SO
TSD
MSB
SO data is shifted out on the rising SCLK edge
.
Modulo16 counter begins on the first rising SCLK edge after CSB goes. low
Modulo16 counter ends– 16 bit word length valid
.
Modulo8 counter begins on the next rising SCLK edge
.
Modulo8 counter ends– 8 bit word length valid. Valid n*8 bit frame.
Figure 16. SPI Data Recognition and Frame Detection
The TSD bit is multiplexed with the SPI SO data and OR’d
with the SI input (Figure 17) to allow for reporting in a serial
daisy chain configuration in devices with the same SPI
protocol. A TSD error bit as a “1” automatically propagates
through the serial daisy chain circuitry from the SO output
of one device to the SI input of the next. This is shown in
Figures 18 and 19; first as the daisy chained devices
connected with no thermal shutdown latched fault
(Figure 18) and subsequently with a TSD fault in device 1
propagating through to device 2 (Figure 19).
SO
TSD
SO
SI SPI
S
Figure 17. TSD SPI Link
SI
SO
SI
SO
“0”
“0”
“0”
TSD
NCV7718B/C
TSD
“0” Device #1
NCV7718B/C “0”
Device #2
Figure 18. Daisy Chain No TSD Fault
SI
SO
SI
SO
“1”
“0”
“1”
TSD
NCV7718B/C “1”
TSD
Device #1
NCV7718B/C “0” Device #2
Figure 19. Daisy Chain TSD Error Propagation
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18
NCV7718B, NCV7718C
DEVICE PROTECTION, DIAGNOSTICS AND FAULT REPORTING
Power Up/Down Control
Under Voltage Shutdown
Each analog power pin (VS1 or VS2) powers their
respective output drivers. After a device has powered up and
the output drivers are allowed to turn on, the output drivers
will not turn off until the voltage on the supply pins is
reduced below the initial under voltage threshold, exceeds
the over voltage threshold or if shut down by either a SPI
command or a fault condition.
Internal power−up circuitry on the logic supply pin
supports a smooth turn on transition. VCC power up resets
the internal logic such that all output drivers will be off as
power is applied. All the internal counters, SI and SO along
with all the digital registers will be cleared on VCC POR.
Exceeding the under voltage lockout threshold on VCC
allows information to be input through the SPI port for turn
on control. Logic information remains intact over the entire
VS1 and VS2 voltage range.
An under voltage lockout circuit prevents the output
drivers from turning on unintentionally. This control is
provided by monitoring the voltages on the VS1, VS2 and
VCC pins. A built−in hysteresis on the under voltage
threshold is included to prevent an unknown region on the
power pins; VCC, VS1 and VS2. When the VCC goes below
the threshold, all outputs are turned off and the input and
output registers are cleared.
An under voltage condition on the VSx pins will result in
shutting off all the drivers and the status bit 14 (PSF) will be
set. The SPI port remains active during a VSx under−voltage
if proper VCC voltage is supplied. Also all driver states will
be maintained in the logic circuitry with the valid VCC
voltage. Once the input voltage VSx is above the under
voltage threshold level the drivers will return to
programmed operation and the PSF output register bit is
cleared.
Under−voltage timing diagram is provided in Figure 20.
SI
OUTx
LS
OUTx
LS
OUTx
LS
OUTx
LS
OUTx
HS
OUTx
HS
OUTx
HS
SO
X
No
Fault
PSF
No
Fault
Z
0x00
No
Fault
Status
?
No Fault
PSF
No
Fault
?
Output
State
?
OUTx GND
ALL
Z
OUTx GND
ALL
Z
³0x00
No
Fault
OUTx VS
VSx
VSUV
Vcc
VccUV
t
Figure 20. Under−Voltage Timing Diagram
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19
NCV7718B, NCV7718C
Over Voltage Shutdown
re−established, the programmed outputs will turn back on.
Over−voltage shutdown can be disabled by using the SPI
input bit 0 (OVLO = 0) to run through a load dump situation.
It is highly recommended to operate the part with OVLO bit
asserted to ensure that the drivers remain off during a load
dump scenario.
The table below describes the driver status when
enabling/disabling the over voltage lock out feature during
normal and overvoltage situations.
Over voltage shutdown circuitry monitors the voltage on
the VS1 and VS2 pins, which permits a 40 V maximum.
When the Over−voltage Threshold level has been breached
on the VS1or VS2 supply input, the output bit 14 (PSF) will
be set. Additionally, if the input bit 0 (OVLO) is asserted, all
outputs will turn off. During an Over Voltage Lockout
condition the turn on/off status is maintained in the logic
circuitry. When proper input voltage levels are
Table 3. OVER−VOLTAGE LOCK OUT (OVLO)
OVLO Input
Bit
VSx OVLO
Condition
Output Data Bit 14 Power Supply Fail (PSF) Status
OUTx Status
0
0
‘0’
Not in Overvoltage Outputs Unchanged
0
1
‘1’
(Clears when VSx within Operating Range)
In Overvoltage ³ Outputs Unchanged
1
0
‘0’
Not in Overvoltage Outputs Unchanged
1
1
‘1’
(Clears when VSx within Operating Range)
All Outputs Off (Remain off until VSx is out
of OVLO)
Over−voltage timing diagram is provided in Figure 21.
SI
OUTx ON
OVLO=0
OUTx
ON
OUTx
ON
OUTx ON
OVLO=1
OUTx
ON
OUTx
OFF
SO
X
No
Fault
PSF
No
Fault
PSF
No
Fault
No
Fault
PSF
No
Fault
PSF
No
Fault
No
Fault
ALL
Z
OUTx
ON
OUTx Z
Status
?
Output
State
?
VSx
OUTx
ON
VSOV
VSOV
t
Figure 21. Over−Voltage Timing Diagram
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20
NCV7718B, NCV7718C
Over Current Detection and Shutdown
to ‘1’ on the next SPI command. The event triggering the
over current shutdown condition must be resolved prior to
clearing the OCS bit to avoid repetitive stress on the drivers.
Failure to do so may result in non reversible fatal damage.
The SO data OCS shown on Figure 22 corresponds to both
the global SO bit #15 and the HBx OCS encoding state ‘01’.
Note: high currents could cause a high rise in die
temperature. Devices will turn off if the die temperature
exceeds the thermal shutdown temperature.
The NCV7718B/C offers over current shutdown
protection on the OUTx pins by monitoring the current on
the high side and low side drivers. If the over current
threshold is breached, the corresponding output is latched
off (HS and LS driver is latched off) after the specified
shutdown time, TdOc. Upon over current shutdown, the
serial output bit OCS will be set and the corresponding
HBx[1:0] will be changed to “01” to denote a high power
dissipation state. Devices can be turned back on via the SPI
port once the OCS condition is cleared by setting the SRR
SI
OUTx ON
SRR=0
OUTx
ON
OUTx
ON
OUTx ON
SRR=1
OUTx
ON
OUTx
ON
SO
No
Fault
No
Fault
OCS
OCS
No
Fault
OCS
Status
No
Fault
OCS
No
Fault
OCS
Output
State
OUTx
ON
OUTx Z
OUTx
ON
OUTx Z
TdOc
Output
Current
TdOc
IsdSxx
t
Figure 22. Over−Current Timing Diagram
Under Load Detection
Furthermore, if the Under−Load Detection Shutdown
Control (ULDSC bit # 13) input bit is set then the offending
half−bridge output will be turned off (HS and LS on the
driver will be latched off).
There is only one global under load timer for all the
drivers. If the TdUld timer is already activated due to one
under load, any subsequent under load delays will be the
remainder of the TdUld timer.
The under−load detection is accomplished by monitoring
the current from the low side drivers and one global output
bit is used for under load fault reporting. A minimum load
current (IuldLS − this is the maximum open circuit detection
threshold) is required when the drivers are turned on to avoid
an under−load condition. If the under−load detection
threshold has been breached longer than the specified
under−load timer (TdUld), the ULD output bit is set to ‘1’.
Table 4. UNDER−LOAD DRIVER STATUS
ULDSC Input
Bit 13
OUTx ULD
Condition
Output Data Bit Under Load Detect Status
OUTx Status
0
0
‘0’
Unchanged
0
1
‘1’
(Need SRR to reset)
Unchanged
1
0
‘0’
Unchanged
1
1
‘1’ (Need SRR to reset)
OUTx Latches off (Need SRR to reset)
The ULD SO data provided in the under load timing diagram in Figure 24 reflects the global ULD SO bit #13 and the HBx
ULD encoding state ‘10’.
www.onsemi.com
21
NCV7718B, NCV7718C
SI
LSx ON
ULDSC=0
LSx
ON
LSx ON
SRR=1
LSx ON
ULDSC=1
LSx ON
SRR=1
LSx
ON
SO
No
Fault
No
Fault
ULD
ULD
ULD
No
Fault
No Fault
Status
Output
State
ULD
OUTx
ON
No
Fault
No Fault
ULD
OUTx
Z
OUTx GND
TdUld
OUTx GND
TdUld
Output
Current
TdUld
IuldLS
t
Figure 23. LS Under−load Timing Diagram
Thermal Warning and Thermal Shutdown
thermal sensors detects a thermal shutdown level then the
drivers on the offending half bridge are latched off. The TSD
(PRE_15) bit is set to capture a thermal shutdown event. A
valid SPI command with SRR and temperature below the
Tsd threshold are required to clear the latched fault. Since
thermal warning precedes an over temperature shutdown,
software polling of this bit will allow load control and
possible prevention of over temperature shutdown
conditions.
The NCV7718B/C provides individual thermal sensors
for each half−bridge. Moreover, the sensor reports over
temperature warning level and an over temperature
shutdown level. The TW status bit (output bit 0) will be set
if the temperature exceeds the over temperature warning
level, but the drivers will remain active. Once the IC
temperature fall below the thermal warning threshold the
TW flag is automatically clearly. If any of the individual
SI
OUTx
ON
OUTx
ON
OUTx
ON
OUTx
ON
OUTx ON
SRR=1
OUTx ON
SRR=1
SO
No
Fault
TW
No
Fault
TW
TSD
TW
TW
Status
No
Fault
TW
No
Fault
TW
TSD
TW
Output
State
TW
OUTx Z
OUTx ON
TW
OUTx
ON
TJ
TSD
TWR
TsdHy
TwHy
t
Figure 24. Thermal Warning and Shutdown Timing Diagram
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22
NCV7718B, NCV7718C
Thermal Performance
3.0
110
SSOP24 NB EPAD Package
Spreader based on JESD51−3
1.0 oz
90
qJA (°C/W)
MAXIMUM POWER (W)
100
80
70
2.0 oz
60
50
40
100
200
300
400
500
600
700
800
900
2.5
2.0 oz
2.0
1.5
1.0 oz
1.0
0.5
SSOP24 NB EPAD Package
Spreader based on JESD51−3
100
COPPER HEAT SPREADER AREA (sq mm)
200
300
400
500
700
COPPER HEAT SPREADER AREA
800
900
(mm2)
Figure 26. Power vs. Cu Area: SSOP24 NB EP
Figure 25. qJA vs. Cu Area: SSOP24 NB EP
80
70
600
200 mm2
SSOP24 NB EPAD Package
2.0 oz. Spreader based on JESD51−3
R(t) (°C/W)
60
600 mm2
50
40
30
20
10
0
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
PULSE TIME (sec)
Figure 27. R(t) vs. Duty Cycle: SSOP24 NB EP
www.onsemi.com
23
10
100
1000
NCV7718B, NCV7718C
Thermal Performance
1.5
140
130
110
MAXIMUM POWER (W)
120
qJA (°C/W)
2.0 oz
1.0 oz
2.0 oz
100
90
80
70
60
SSOP24 NB Package
Spreader based on JESD51−3
50
40
100
200
300
400
500
600
700
800
900
1.3
1.0 oz
1.1
0.9
0.7
0.5
SSOP24 NB Package
Spreader based on JESD51−3
100
COPPER HEAT SPREADER AREA (sq mm)
200
300
400
500
700
COPPER HEAT SPREADER AREA
120
900
200 mm2
SSOP24 NB Package
2.0 oz. Spreader based on JESD51−3
90
R(t) (°C/W)
800
(mm2)
Figure 29. Power vs. Cu Area: SSOP24 NB
Figure 28. qJA vs. Cu Area: SSOP24 NB
105
600
600 mm2
75
60
45
30
15
0
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
PULSE TIME (sec)
Figure 30. R(t) vs. Duty Cycle: SSOP24 NB
www.onsemi.com
24
10
100
1000
NCV7718B, NCV7718C
Fault Handling
that is locked out during a fault conditions auto recovers to
the previous programmed state when the fault is resolved. A
latched fault flag on the serial output doesn’t always
translate an output latched off fault.
The summary of all fault conditions, the driver status and
the clear requirements are provided in Table 5.
At an event of a driver latched off fault, the offending
half−bridge driver is disabled and the half−bridge
configuration is defaulted to zero (HBENx =0, HBCNFx =
0). The user is required to clear the output register fault and
to resend the proper SPI frame to turn on the drivers. A driver
Table 5. FAULT SUMMARY
Driver
Condition after Parameters
Within Specified Limits
Fault Memory
Serial Output Bit
Driver
Condition During Fault
Under Load
(ULDSC = 0)
Latched
Outputs Unchanged.
Allowed to turn/ remain on
Allowed to turn/remain on
Valid SPI frame with
SRR set to 1
Under Load
(ULDSC = 1)
Latched (Note 9)
Offending Half−Bridge is
Latched Off (LS and HS)
Offending Half−Bridge is
Latched Off
(LS and HS)
Valid SPI frame with
SRR set to 1
Over Current
Latched (Note 9)
Offending Output is
Latched Off
(LS and HS)
Offending Output is Latched
Off
(LS and HS)
Valid SPI frame with
SRR set to 1
Non−Latched
Outputs Unchanged.
Allowed to turn/ remain on
provided that device is not
in thermal shutdown
Allowed to turn/remain on
Temp below (thermal
warning temp –
hysteresis)
Thermal Shutdown
Latched (Note 9)
Offending Half−Bridge
Drivers are Latched Off
(LS and HS)
Offending Half−Bridge is
Latched Off (LS and HS)
Valid SPI frame with
SRR set to 1.
Temperature blow
(thermal shutdown −
hysteresis)
VS Power Supply
Fail (Over−Voltage:
OVLO = 0)
Non−Latched
Outputs Unchanged.
Allowed to
turn/ remain on
Allowed to turn/remain on
VS below (Over Voltage
Threshold – hysteresis)
VS Power Supply
Fail (Over−Voltage:
OVLO = 1)
Non−Latched
All Drivers are Locked
Out.
Outx ³ High Z
Previous Half−Bridge status
and driver configuration is
maintained. Allowed to
turn/remain on
Auto Recovers if the VS
voltage is below
overvoltage threshold
VS Power Supply
Fail (Under
Voltage)
Non−Latched
All Drivers are Locked
Out.
Outx ³ High Z
Previous Half−Bridge status
and driver configuration is
maintained. Allowed to
turn/remain on
Auto Recovers if the VS
voltage is above the
Under Voltage
threshold
Fault
Thermal Warning
Output Register Clear
Requirement
9. Latched conditions are cleared via the SPI SRR input bit = 1, by cycling the EN pin or with a power−on reset of VCC.
www.onsemi.com
25
NCV7718B, NCV7718C
APPLICATION DIAGRAM
The application drawing below demonstrates the drive
capability of the NCV7718B/C. The VS1 and VS2 pins must
be tied together to avoid any potential difference in the
supply voltage.
MRA4003T3
13.2V
0.1uF
VS1
VS2
VIN
20k
VCC
VOUT
EN
NCV8518B
1.0uF
DELAY
120k
OUT1
GND
WDI
RESET
M1
OUT2
M5
OUT3
NCV7718B/C
IO
RESET
Hex Half Bridge
M2
OUT4
M4
VCC
OUT5
M3
uC
MOSI
SI
MISO
SO
SCLK
SCLK
CSB
CSB
EN
OUT6
EN
GND GND GND GND
Figure 31. Application Drawing
ORDERING INFORMATION
Package
Shipping†
NCV7718BDQR2G
SSOP24 NB EP
(Pb−Free)
2500 / Tape & Reel
NCV7718CDQR2G
SSOP24 NB EP
(Pb−Free)
2500 / Tape & Reel
NCV7718CDPR2G
SSOP24 NB
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
26
NCV7718B, NCV7718C
PACKAGE DIMENSIONS
SSOP24 NB EP
CASE 940AK
ISSUE O
2X
0.20 C A-B
NOTE 4
NOTE 6
D
D
A
2X
24
L1
H
13
L2
0.20 C
NOTE 5
GAUGE
PLANE
ÉÉÉ
ÉÉÉ
E1
PIN 1
REFERENCE
e
E
L
DETAIL A
A1
C
NOTE 7
1
12
B
SEATING
PLANE
0.20 C
2X 12 TIPS
b
0.12
24X
NOTE 6
TOP VIEW
C A-B D
M
A
DETAIL A
A2
h
h
0.10 C
M
0.10 C
24X
0.15
SIDE VIEW
M
C A-B D
A1
C
SEATING
PLANE
c
END VIEW
NOTE 8
D2
0.15
E2
M
C A-B D
NOTE 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
BE 0.10 MAX. AT MMC. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OF THE
FOOT. DIMENSION b APPLIES TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.10 TO 0.25
FROM THE LEAD TIP.
4. DIMENSION D DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 PER SIDE. DIMENSION D IS
DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25 PER
SIDE. DIMENSION E1 IS DETERMINED AT DATUM PLANE H.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
8. CONTOURS OF THE THERMAL PAD ARE UNCONTROLLED WITHIN THE REGION DEFINED
BY DIMENSIONS D2 AND E2.
DIM
A
A1
A2
b
c
D
D2
E
E1
E2
e
h
L
L1
L2
M
RECOMMENDED
SOLDERING FOOTPRINT*
BOTTOM VIEW
5.63
24X
1.15
2.84 6.40
1
24X
0.65
PITCH
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
27
MILLIMETERS
MIN
MAX
1.70
--0.00
0.10
1.10
1.65
0.19
0.30
0.09
0.20
8.64 BSC
5.28
5.58
6.00 BSC
3.90 BSC
2.44
2.64
0.65 BSC
0.25
0.50
0.40
0.85
1.00 REF
0.25 BSC
0_
8_
NCV7718B, NCV7718C
PACKAGE DIMENSIONS
SSOP24 NB
CASE 565AL
ISSUE O
0.20 C D
D
2X
D
A
13
24
0.20 C D
L2
2X
ÉÉ
ÉÉ
E1
PIN 1
REFERENCE
e
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION.
4. DIMENSION D DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.15 PER SIDE.
DIMENSION E1 DOES NOT INLCUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 PER SIDE. D AND E1 ARE DETERMINED AT DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
E
L
C
DETAIL A
1
12
B
24X
TOP VIEW
GAUGE
PLANE
SEATING
PLANE
0.25 C D
b
0.25
A
2X 12 TIPS
M
C A-B D
A2
h
x 45°
H
0.10 C
M
0.10 C
24X
SIDE VIEW
A1
C
c
SEATING
PLANE
END VIEW
DETAIL A
DIM
A
A1
A2
b
c
D
E
E1
e
h
L
L2
M
MILLIMETERS
MIN
MAX
1.75
1.35
0.10
0.25
1.25
1.50
0.20
0.30
0.19
0.25
8.65 BSC
6.00 BSC
3.90 BSC
0.65 BSC
0.22
0.50
0.40
1.27
0.25 BSC
0_
8_
RECOMMENDED
SOLDERING FOOTPRINT
24X
24X
0.42
24
13
1.12
6.40
1
12
0.65
PITCH
DIMENSIONS: MILLIMETERS
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