NCV8133
500 mA, Very Low Dropout
Bias Rail CMOS Voltage
Regulator
The NCV8133 is a 500 mA VLDO equipped with NMOS pass
transistor and a separate bias supply voltage (VBIAS). The device
provides very stable, accurate output voltage with low noise suitable
for space constrained, noise sensitive applications. In order to
optimize performance for battery operated portable applications, the
NCV8133 features low IQ consumption. The XDFN6 1.2 mm x
1.2 mm package is optimized for use in space constrained
applications.
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T
MARKING
DIAGRAM
XDFN6
CASE 711AT
XX M
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Voltage Range: 0.8 V to 5.5 V
Bias Voltage Range: 2.4 V to 5.5 V
Fixed Output Voltage Device
Output Voltage Range: 0.8 V to 2.1 V
±1.5% Accuracy over Temperature, 0.5% VOUT @ 25°C
Ultra−Low Dropout: Typ. 140 mV at 500 mA
Very Low Bias Input Current of Typ. 80 mA
Very Low Bias Input Current in Disable Mode: Typ. 0.5 mA
Logic Level Enable Input for ON/OFF Control
Output Active Discharge Option Available
Stable with a 2.2 mF Ceramic Capacitor
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable; Device Temperature Grade 1: −40°C to
+125°C Ambient Operating Temperature Range
These are Pb−Free Devices
XX = Specific Device Code
M = Date Code
PIN CONNECTIONS
OUT
1
NC
2
EN
3
GND
6
IN
5
GND
4
BIAS
(Top VIew)
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
Typical Applications
• Automotive, Consumer and Industrial Equipment Point of Load
•
•
•
•
Regulation
Battery−powered Equipment
FPGA, DSP and Logic Power Supplies
Switching Power Supply Post Regulation
Cameras, DVRs, STB and Camcorders
VBIAS
>2.7 V
NCV8133
100 nF
BIAS
VIN
1.5 V
1 mF
VOUT
1 V up to 500 mA
OUT
IN
2.2 mF
EN
GND
VEN
Figure 1. Typical Application Schematics
© Semiconductor Components Industries, LLC, 2017
July, 2017 − Rev. 1
1
Publication Order Number:
NCV8133/D
NCV8133
CURRENT
LIMIT
IN
EN
BIAS
OUT
ENABLE
BLOCK
UVLO
150 W
VOLTAGE
REFERENCE
+
−
THERMAL
LIMIT
*Active
DISCHARGE
GND
*Active output discharge function is present only in NCV8133AMXyyyTCG devices.
yyy denotes the particular output voltage option.
Figure 2. Simplified Schematic Block Diagram
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2
NCV8133
PIN FUNCTION DESCRIPTION
Pin No.
XDFN6
Pin Name
1
OUT
Regulated Output Voltage pin
2
N/C
Not internally connected (Note 1)
3
EN
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into
shutdown mode.
4
BIAS
Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage
Lockout Circuit.
5
GND
Ground
6
IN
Description
Input Voltage Supply pin
Pad
Should be soldered to the ground plane for increased thermal performance.
1. True no connect. Printed circuit board traces are allowable
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN
−0.3 to 6
V
VOUT
−0.3 to (VIN+0.3) ≤ 6
V
VEN, VBIAS
−0.3 to 6
V
Output Short Circuit Duration
tSC
unlimited
s
Maximum Junction Temperature
TJ
150
°C
TSTG
−55 to 150
°C
ESD Capability, Human Body Model (Note 3)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 3)
ESDMM
200
V
Input Voltage (Note 2)
Output Voltage
Chip Enable, Bias and Adj Input
Storage Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
3. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002
ESD Machine Model tested per AEC−Q100−003
Latchup Current Maximum Rating ≤ 150 mA per AEC−Q100−004.
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Min
Max
Unit
Input Voltage
VIN
(VOUT + VDO_IN)
5.5
V
Bias Voltage
VBIAS
(VOUT + 1.4) ≥ 2.4
5.5
V
TJ
−40
+125
°C
Junction Temperature
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
THERMAL CHARACTERISTICS
Rating
Thermal Characteristics, XDFN6 1.2 mm x 1.2 mm
Thermal Resistance, Junction−to−Air
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3
Symbol
Value
Unit
RqJA
170
°C/W
NCV8133
ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 125°C; VBIAS = 2.7 V or (VOUT + 1.6 V), whichever is greater, VIN = VOUT(NOM) +
0.3 V, IOUT = 1 mA, VEN = 1 V, unless otherwise noted. CIN = 1 mF, COUT = 2.2 mF. Typical values are at TJ = +25°C. Min/Max values are
for −40°C ≤ TJ ≤ 125°C unless otherwise noted. (Note 4)
Test Conditions
Symbol
Min
Operating Input Voltage
Range
VIN
Operating Bias Voltage
Range
VBIAS
Parameter
Undervoltage Lock−out
VBIAS Rising
Hysteresis
Output Voltage Accuracy
Typ
Max
Unit
VOUT +
VDO
5.5
V
(VOUT +
1.40) ≥ 2.4
5.5
V
UVLO
1.6
0.2
V
VOUT
±0.5
%
Output Voltage Accuracy
−40°C ≤ TJ ≤ 125°C, VOUT(NOM) + 0.3 V ≤ VIN ≤
VOUT(NOM) + 1.0 V, 2.7 V or (VOUT(NOM) +
1.6 V), whichever is greater < VBIAS < 5.5 V,
1 mA < IOUT < 500 mA
VIN Line Regulation
VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.0 V
LineReg
0.01
%/V
VBIAS Line Regulation
2.7 V or (VOUT(NOM) + 1.6 V), whichever is
greater < VBIAS < 5.5 V
LineReg
0.01
%/V
Load Regulation
IOUT = 1 mA to 500 mA
LoadReg
1.5
mV
VIN Dropout Voltage
IOUT = 150 mA (Note 5)
VDO
37
90
IOUT = 500 mA (Note 5)
VDO
140
300
VBIAS Dropout Voltage
IOUT = 500 mA, VIN = VBIAS (Notes 5, 6)
VDO
1.1
1.5
V
Output Current Limit
VOUT = 90% VOUT(NOM)
Bias Pin Operating Current
VBIAS = 2.7 V
Bias Pin Disable Current
VOUT
ICL
−1.5
550
+1.5
%
mV
800
1100
mA
IBIAS
80
110
mA
VEN ≤ 0.4 V
IBIAS(DIS)
0.5
1.5
mA
Vinput Pin Disable Current
VEN ≤ 0.4 V
IVIN(DIS)
0.5
1.5
mA
EN Pin Threshold Voltage
EN Input Voltage “H”
VEN(H)
EN Input Voltage “L”
VEN(L)
V
0.9
0.4
VEN = 5.5 V
IEN
0.3
Turn−On Time
From assertion of VEN to VOUT =
98% VOUT(NOM). VOUT(NOM) = 1.0 V
tON
150
ms
Power Supply Rejection
Ratio
VIN to VOUT, f = 1 kHz, IOUT = 150 mA,
VIN ≥ VOUT +0.5 V
PSRR(VIN)
70
dB
PSRR(VBIAS)
80
dB
VN
40
mVRMS
°C
VBIAS to VOUT, f = 1 kHz, IOUT = 150 mA,
VIN ≥ VOUT +0.5 V
Output Noise Voltage
VIN = VOUT +0.5 V, VOUT(NOM) = 1.0 V,
f = 10 Hz to 100 kHz
Thermal Shutdown
Threshold
Temperature increasing
160
Temperature decreasing
140
Output Discharge
Pull−Down
VEN ≤ 0.4 V, VOUT = 0.5 V, NCV8133A options
only
RDISCH
150
1.5
mA
EN Pull Down Current
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA = 25°C.
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
5. Dropout voltage is characterized when VOUT falls 3% below VOUT(NOM).
6. For output voltages below 0.9 V, VBIAS dropout voltage does not apply due to a minimum Bias operating voltage of 2.4 V.
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4
NCV8133
TYPICAL CHARACTERISTICS
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
200
180
160
+125°C
+85°C
140
120
100
−40°C
80
60
40
+25°C
20
0
0
100
200
400
300
500
IOUT = 100 mA
180
160
140
120
100
80
+125°C
+85°C
60
+25°C −40°C
40
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Figure 3. VIN Dropout Voltage vs. IOUT and
Temperature TJ
Figure 4. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
VBIAS − VOUT (V)
300
IOUT = 300 mA
250
200
150
+125°C
+85°C
+25°C
100
−40°C
50
0
0.5
200
IOUT, OUTPUT CURRENT (mA)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
4.5
500
450
IOUT = 500 mA
400
350
300
+125°C
250
+85°C
200
+25°C
150
−40°C
100
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VBIAS − VOUT (V)
VBIAS − VOUT (V)
Figure 5. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
Figure 6. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
4.5
140
1500
1400
120
+125°C
1300
+85°C
+125°C
100
−40°C
IBIAS (mA)
VDO (VBIAS − VOUT) DROPOUT VOLTAGE (mV)
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 2.7 V, VEN = VBIAS, VOUT(NOM) = 1.0 V, IOUT = 500 mA,
CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 2.2 mF (effective capacitance), unless otherwise noted.
1200
+25°C
80
60
−40°C
1100
+25°C
40
+85°C
1000
20
0
900
0
50
100
150
200
250
300
0
50
100 150 200
250 300 350 400 450 500
IOUT, OUTPUT CURRENT (mA)
IOUT, OUTPUT CURRENT (mA)
Figure 7. VBIAS Dropout Voltage vs. IOUT and
Temperature TJ
Figure 8. BIAS Pin Current vs. IOUT and
Temperature TJ
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NCV8133
TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 2.7 V, VEN = VBIAS, VOUT(NOM) = 1.0 V, IOUT = 500 mA,
CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 2.2 mF (effective capacitance), unless otherwise noted.
1000
180
900
ICL, CURRENT LIMIT (mA)
200
160
IBIAS (mA)
140
120
+125°C
+85°C
100
80
60
40
20
0
2.0
+25°C
−40°C
+125°C
800
700
+85°C
+25°C
600
−40°C
500
400
300
200
100
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5 5.0
VBIAS (V)
VBIAS − VOUT (V)
Figure 9. BIAS Pin Current vs. VBIAS and
Temperature TJ
Figure 10. Current Limit vs. (VBIAS − VOUT)
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NCV8133
TYPICAL CHARACTERISTICS
50 mV/div
VOUT
200 mA/div
tR = tF = 1 ms
IOUT
VOUT
tR = tF = 1 ms
IOUT
50 ms/div
Figure 12. Load Transient Response,
IOUT = 50 mA to 500 mA, COUT = 2.2 mF
50 mV/div
50 ms/div
Figure 11. Load Transient Response,
IOUT = 50 mA to 500 mA, COUT = 10 mF
VOUT
200 mA/div
200 mA/div
50 mV/div
200 mA/div
50 mV/div
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 2.7 V, VEN = VBIAS, VOUT(NOM) = 1.0 V, IOUT = 500 mA,
CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 2.2 mF (effective capacitance), unless otherwise noted.
tR = tF = 1 ms
IOUT
VOUT
tR = tF = 1 ms
IOUT
500 ms/div
500 ms/div
Figure 14. Load Transient Response,
IOUT = 1 mA to 500 mA, COUT = 2.2 mF
1 V/div
1 V/div
Figure 13. Load Transient Response,
IOUT = 1 mA to 500 mA, COUT = 10 mF
VENABLE
VENABLE
VOUT
200 mV/div
200 mA/div 200 mV/div
VOUT
IOUT
100 ms/div
100 ms/div
Figure 15. Enable Turn−on Response,
Output Resistive Load 500 mA, COUT = 10 mF
Figure 16. Enable Turn−on Response,
IOUT = 0 mA, COUT = 2.2 mF
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NCV8133
TYPICAL CHARACTERISTICS
10 mV/div
10 mV/div
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 2.7 V, VEN = VBIAS, VOUT(NOM) = 1.0 V, IOUT = 500 mA,
CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 2.2 mF (effective capacitance), unless otherwise noted.
VOUT
VOUT
tR = tF = 5 ms
1 V/div
1 V/div
tR = tF = 5 ms
VIN
VIN
20 ms/div
20 ms/div
Figure 17. VIN Line Transient Response,
VIN = 1.3 V to 2.3 V, IOUT = 100 mA, COUT = 10 mF
Figure 18. VIN Line Transient Response,
VIN = 1.3 V to 2.3 V, IOUT = 100 mA, COUT = 2.2 mF
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8
NCV8133
APPLICATIONS INFORMATION
VBAT
NCV8133
EN
Switch−mode DC/DC
VOUT = 1.5 V
IN
LX
EN
FB
Processor
BIAS
1.5 V
OUT
1.0 V
IN
LOAD
GND
GND
I/O
I/O
To other circuits
Figure 19. Typical Application: Low−Voltage DC/DC Post−Regulator with ON/OFF Functionality
The NCV8133 dual−rail very low dropout voltage
regulator is using NMOS pass transistor for output voltage
regulation from VIN voltage. All the low current internal
control circuitry is powered from the VBIAS voltage.
The use of an NMOS pass transistor offers several
advantages in applications. Unlike PMOS topology devices,
the output capacitor has reduced impact on loop stability.
Vin to Vout operating voltage difference can be very low
compared with standard PMOS regulators in very low Vin
applications.
The NCV8133 offers smooth monotonic start-up. The
controlled voltage rising limits the inrush current.
The Enable (EN) input is equipped with internal
hysteresis.
NCV8133 is a Fixed Voltage linear regulator.
example), the recommended CIN = 1 mF and CBIAS = 0.1 mF
or greater. Ceramic capacitors are recommended. For the
best performance all the capacitors should be connected to
the NCV8133 respective pins directly in the device PCB
copper layer, not through vias having not negligible
impedance.
When using small ceramic capacitor, their capacitance is
not constant but varies with applied DC biasing voltage,
temperature and tolerance. The effective capacitance can be
much lower than their nominal capacitance value, most
importantly in negative temperatures and higher LDO
output voltages. That is why the recommended Output
capacitor capacitance value is specified as Effective value in
the specific application conditions.
Dropout Voltage
The enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this data sheet. If the enable function is not to be used
then the pin should be connected to VIN or VBIAS.
Enable Operation
Because of two power supply inputs VIN and VBIAS and
one VOUT regulator output, there are two Dropout voltages
specified.
The first, the VIN Dropout voltage is the voltage
difference (VIN – VOUT) when VOUT starts to decrease by
percent specified in the Electrical Characteristics table.
VBIAS is high enough; specific value is published in the
Electrical Characteristics table.
The second, VBIAS dropout voltage is the voltage
difference (VBIAS – VOUT) when VIN and VBIAS pins are
joined together and VOUT starts to decrease.
Current Limitation
The internal Current Limitation circuitry allows the
device to supply the full nominal current and surges but
protects the device against Current Overload or Short.
Thermal Protection
Internal thermal shutdown (TSD) circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When TSD activated , the
regulator output turns off. When cooling down under the low
temperature threshold, device output is activated again. This
TSD feature is provided to prevent failures from accidental
overheating.
Input and Output Capacitors
The device is designed to be stable for ceramic output
capacitors with Effective capacitance in the range from
2.2 mF to 10 mF. The device is also stable with multiple
capacitors in parallel, having the total effective capacitance
in the specified range.
In applications where no low input supplies impedance
available (PCB inductance in VIN and/or VBIAS inputs as
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9
NCV8133
Power Dissipation
ambient temperature affect the rate of junction temperature
rise for the part. For reliable operation, junction temperature
should be limited to +125°C.
The maximum power dissipation supported by the device
is dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
ORDERING INFORMATION
Nominal
Output
Voltage
Marking
NCV8133BMX080TCG
0.80 V
JL
NCV8133BMX100TCG
1.00 V
JM
NCV8133BMX110TCG
1.10 V
JD
NCV8133BMX120TCG
1.20 V
JE
NCV8133BMX130TCG
1.30 V
JN
NCV8133BMX150TCG
1.50 V
JF
NCV8133BMX180TCG
1.80 V
JG
Device
Option
Package
Shipping†
Non−Active Discharge
XDFN6
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
To order other package and voltage variants, please contact your ON Semiconductor sales representative
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
XDFN6 1.20x1.20, 0.40P
CASE 711AT
ISSUE C
SCALE 4:1
D
PIN ONE
REFERENCE
DATE 04 DEC 2015
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO THE PLATED
TERMINALS.
4. COPLANARITY APPLIES TO THE PAD AS
WELL AS THE TERMINALS.
A
B
ÍÍÍ
ÍÍÍ
ÍÍÍ
E
L
TOP VIEW
DETAIL A
OPTIONAL
CONSTRUCTION
A
0.05 C
DIM
A
A1
b
D
D2
E
E2
e
L
L1
A1
GENERIC
MARKING DIAGRAM*
0.05 C
C
SIDE VIEW
NOTE 4
MILLIMETERS
TYP
MAX
0.37
0.45
0.03
0.05
0.18
0.23
1.20
1.25
0.94
1.04
1.20
1.25
0.40
0.30
0.40 BSC
0.15
0.20
0.25
0.05
0.00
0.10
MIN
0.30
0.00
0.13
1.15
0.84
1.15
0.20
SEATING
PLANE
XX M
D2
1
3
6X
L1
XX = Specific Device Code
M = Date Code
E2
6X
*This information is generic. Please refer
to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “
G”, may or may not be present.
L
6
DETAIL A
4
6X
e
b
0.10
BOTTOM VIEW
M
C A B
NOTE 3
RECOMMENDED
MOUNTING FOOTPRINT*
1.08
PACKAGE
OUTLINE
6X
0.37
1.40
0.40
1
0.40
PITCH
6X
0.24
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON76141F
XDFN6, 1.20 X 1.20, 0.40P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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