NCV8402ADDR2G

Dual Self-Protected Low-Side Driver with Temperature and Current Limit NCV8402D, NCV8402AD NCV8402D/AD is a dual protected Low−Side Smart Discrete device. The protection features include overcurrent, overtemperature, ESD and integrated Drain−to−Gate clamping for overvoltage protection. This device offers protection and is suitable for harsh automotive environments. • V(BR)DSS (Clamped) RDS(ON) TYP ID MAX 42 V 165 mW @ 10 V 2.0 A* *Max current limit value is dependent on input condition. Features • • • • • • • • www.onsemi.com Short−Circuit Protection Thermal Shutdown with Automatic Restart Overvoltage Protection Integrated Clamp for Inductive Switching ESD Protection dV/dt Robustness Analog Drive Capability (Logic Level Input) NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Drain Overvoltage Protection Gate Input ESD Protection Temperature Limit Current Limit Current Sense Source MARKING DIAGRAM Typical Applications • Switch a Variety of Resistive, Inductive and Capacitive Loads • Can Replace Electromechanical Relays and Discrete Circuits • Automotive / Industrial 8 SO−8 CASE 751 STYLE 11 8 1 xxxxxx ALYW G 1 xxxxxx A L Y W G = V8402D or 8402AD = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN ASSIGNMENT Source 1 Gate 1 Source 2 Gate 2 1 8 Drain 1 Drain 1 Drain 2 Drain 2 ORDERING INFORMATION Device Package Shipping† SOIC−8 2500/Tape & Reel NCV8402DDR2G NCV8402ADDR2G (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 October, 2019 − Rev. 6 1 Publication Order Number: NCV8402D/D NCV8402D, NCV8402AD MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Internally Clamped Symbol Value Unit VDSS 42 V VDGR 42 V Gate−to−Source Voltage VGS "14 V Continuous Drain Current ID Drain−to−Gate Voltage Internally Clamped (RG = 1.0 MW) Internally Limited Total Power Dissipation @ TA = 25°C (Note 1) @ TA = 25°C (Note 2) PD 0.8 1.62 W Maximum Continuous Drain, both channels on @ TA = 25°C (Note 1) @ TA = 25°C (Note 2) ID 1.87 2.65 A RqJA RqJA 157 77 °C/W Single Pulse Drain−to−Source Avalanche Energy (VDD = 32 V, VG = 5.0 V, IPK = 1.0 A, L = 300 mH, RG(ext) = 25 W) EAS 150 mJ Load Dump Voltage VLD 55 V TJ, Tstg −55 to 150 °C Thermal Resistance Junction−to−Ambient Steady State (Note 1) Junction−to−Ambient Steady State (Note 2) (VGS = 0 and 10 V, RI = 2.0 W, RL = 9.0 W, td = 400 ms) Operating Junction and Storage Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Surface−mounted onto min pad FR4 PCB, (Cu area = 40 sq. mm, 1 oz.). 2. Surface−mounted onto 1″ sq. FR4 board (Cu area = 625 sq. mm, 2 oz.). + ID DRAIN IG + VDS GATE SOURCE VGS − − Figure 1. Voltage and Current Convention www.onsemi.com 2 NCV8402D, NCV8402AD ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 3) Zero Gate Voltage Drain Current Test Condition Symbol Min Typ Max Unit VGS = 0 V, ID = 10 mA, TJ = 25°C V(BR)DSS 42 46 55 V 40 45 55 0.25 4.0 1.1 20 50 100 VGS = 0 V, ID = 10 mA, TJ = 150°C (Note 5) VGS = 0 V, VDS = 32 V, TJ = 25°C IDSS VGS = 0 V, VDS = 32 V, TJ = 150°C (Note 5) Gate Input Current VDS = 0 V, VGS = 5.0 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage VGS = VDS, ID = 150 mA Gate Threshold Temperature Coefficient Static Drain−to−Source On−Resistance Source−Drain Forward On Voltage VGS = 10 V, ID = 1.7 A, TJ = 25°C IGSSF VGS(th) 1.3 mA 1.8 2.2 V VGS(th)/TJ 4.0 6.0 −mV/°C RDS(on) mW 165 200 VGS = 10 V, ID = 1.7 A, TJ = 150°C (Note 5) 305 400 VGS = 5.0 V, ID = 1.7 A, TJ = 25°C 195 230 VGS = 5.0 V, ID = 1.7 A, TJ = 150°C (Note 5) 360 460 VGS = 5.0 V, ID = 0.5 A, TJ = 25°C 190 230 VGS = 5.0 V, ID = 0.5 A, TJ = 150°C (Note 5) 350 460 VGS = 0 V, IS = 7.0 A mA VSD 1.0 V SWITCHING CHARACTERISTICS (Note 5) Turn−On Time (10% VIN to 90% ID) ton 25 30 ms Turn−Off Time (90% VIN to 10% ID) toff 120 200 ms trise 20 25 ms tfall 50 70 ms Slew−Rate ON (70% VDS to 50% VDD) −dVDS/dtON 0.8 1.2 V/ms Slew−Rate OFF (50% VDS to 70% VDD) dVDS/dtOFF 0.3 0.5 3.7 4.3 5.0 2.3 3.0 3.7 VDS = 10 V, VGS = 10 V, TJ = 25°C 4.2 4.8 5.4 VDS = 10 V, VGS = 10 V, TJ = 150°C (Note 5) 2.7 3.6 4.5 150 175 200 150 165 Turn−On Rise Time (10% ID to 90% ID) Turn−Off Fall Time (90% ID to 10% ID) VGS = 10 V, VDD = 12 V, ID = 2.5 A, RL = 4.7 W SELF PROTECTION CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 4) Current Limit VDS = 10 V, VGS = 5.0 V, TJ = 25°C ILIM VDS = 10 V, VGS = 5.0 V, TJ = 150°C (Note 5) Temperature Limit (Turn−off) Thermal Hysteresis Temperature Limit (Turn−off) Thermal Hysteresis GATE INPUT CHARACTERISTICS (Note 5) Device ON Gate Input Current VGS = 5.0 V (Note 5) TLIM(off) VGS = 5.0 V DTLIM(on) VGS = 10 V (Note 5) TLIM(off) VGS = 10 V DTLIM(on) VGS = 5 V ID = 1.0 A IGON VGS = 5 V, VDS = 10 V VGS = 5 V, VDS = 10 V 50 IGCL 0.05 www.onsemi.com 3 mA 0.4 IGTL ESD ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 5) Electro−Static Discharge Capability ESD Human Body Model (HBM) 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Fault conditions are viewed as beyond the normal operating range of the part. 5. Not subject to production testing. mA 400 0.15 VGS = 10 V, VDS = 10 V Machine Model (MM) 185 15 VGS = 10 V, VDS = 10 V Thermal Limit Fault Gate Input Current °C 15 VGS = 10 V ID = 1.0 A Current Limit Gate Input Current A mA 0.7 4000 400 V NCV8402D, NCV8402AD TYPICAL PERFORMANCE CURVES 10 Emax (mJ) IL(max) (A) 1000 TJstart = 25°C 100 TJstart = 25°C TJstart = 150°C TJstart = 150°C 1 10 10 10 100 L (mH) Figure 2. Single Pulse Maximum Switch−off Current vs. Load Inductance 100 L (mH) Figure 3. Single Pulse Maximum Switching Energy vs. Load Inductance 1000 10 1 0.1 Emax (mJ) IL(max) (A) TJstart = 25°C TJstart = 150°C 1 100 TJstart = 150°C 10 10 TIME IN CLAMP (ms) TJstart = 25°C 1 Figure 4. Single Pulse Maximum Inductive Switch−off Current vs. Time in Clamp 8 8V TA = 25°C 7 8 −40°C 6 5V 4V 25°C ID (A) 5 3.5 V 4 3 100°C 4 3 2 3V 1 VGS = 2.5 V 0 VDS = 10 V 7 6V 5 ID (A) Figure 5. Single Pulse Maximum Inductive Switching Energy vs. Time in Clamp 10 V 6 10 TIME IN CLAMP (ms) 0 1 2 3 150°C 2 4 1 0 5 VDS (V) 1 3 VGS (V) Figure 6. On−state Output Characteristics Figure 7. Transfer Characteristics www.onsemi.com 4 2 4 5 NCV8402D, NCV8402AD TYPICAL PERFORMANCE CURVES 350 400 150°C, VGS = 5 V 150°C, ID = 0.5 A 300 RDS(on) (mW) 200 100°C, ID = 1.7 A 100°C, ID = 0.5 A 25°C, ID = 1.7 A 100 5 25°C, ID = 0.5 A −40°C, ID = 0.5 A −40°C, ID = 1.7 A 0 4 RDS(on) (mW) 150°C, ID = 1.7 A 300 100°C, VGS = 5 V 200 100°C, VGS = 10 V 25°C, VGS = 5 V 150 25°C, VGS = 10 V −40°C, VGS = 5 V 100 −40°C, VGS = 10 V 6 7 8 9 50 0.2 10 VGS (V) 1 1.2 ID (A) Figure 8. RDS(on) vs. Gate−Source Voltage Figure 9. RDS(on) vs. Drain Current 0.4 0.6 0.8 1.4 1.6 1.8 2 8 2 ID = 1.7 A 1.75 −40°C 7 VGS = 5 V 1.5 6 ILIM (A) RDS(on) (NORMALIZED) 150°C, VGS = 10 V 250 1.25 1 25°C 5 100°C 4 VGS = 10 V 150°C 3 0.75 0.5 −40 −20 0 20 40 60 T (°C) 80 100 120 2 140 VDS = 10 V 5 6 7 8 9 10 VGS (V) Figure 10. Normalized RDS(on) vs. Temperature Figure 11. Current Limit vs. Gate−Source Voltage 10 8 VGS = 0 V 7 VGS = 10 V IDSS (mA) 6 ILIM (A) 150°C 1 5 4 40 60 80 0.01 −40°C 0.001 3 20 100°C 25°C VGS = 5 V VDS = 10 V 2 −40 −20 0 0.1 100 120 0.0001 10 140 15 20 25 30 35 TJ (°C) VDS (V) Figure 12. Current Limit vs. Junction Temperature Figure 13. Drain−to−Source Leakage Current www.onsemi.com 5 40 NCV8402D, NCV8402AD TYPICAL PERFORMANCE CURVES 1.1 ID = 150 mA VGS = VDS 1.1 1 1 VSD (V) NORMALIZED VGS(th) (V) 1.2 0.9 −40°C 0.9 25°C 0.8 100°C 0.8 0.7 0.7 0.6 0.6 −40 0.5 150°C −20 0 20 40 60 80 100 120 140 VGS = 0 V 1 2 3 4 5 T (°C) Figure 14. Normalized Threshold Voltage vs. Temperature td(off) tf tr td(on) 3 4 5 6 7 VGS (V) 8 9 10 DRAIN−SOURCE VOLTAGE SLOPE (V/ms) TIME (ms) 100 50 9 10 ID = 2.5 A VDD = 12 V RG = 0 W 0.8 0.6 −dVDS/dt(on) 0.4 dVDS/dt(off) 0.2 0 3 Figure 16. Resistive Load Switching Time vs. Gate−Source Voltage 4 5 6 7 VGS (V) 8 9 10 Figure 17. Resistive Load Switching Drain−Source Voltage Slope vs. Gate−Source Voltage 100 75 td(off), (VGS = 10 V) tr, (VGS = 5 V) tf, (VGS = 10 V) 50 tf, (VGS = 5 V) td(off), (VGS = 5 V) 25 tr, (VGS = 10 V) 0 400 td(on), (VGS = 5 V) td(on), (VGS = 10 V) 800 1200 1600 2000 RG (W) DRAIN−SOURCE VOLTAGE SLOPE (V/ms) 1 ID = 2.5 A VDD = 12 V TIME (ms) 8 1 ID = 2.5 A VDD = 12 V RG = 0 W 150 0 7 Figure 15. Source−Drain Diode Forward Characteristics 200 0 6 IS (A) −dVDS/dt(on), VGS = 10 V 0.8 0.6 0.4 dVDS/dt(off), VGS = 5 V 0.2 0 dVDS/dt(off), VGS = 10 V −dVDS/dt(on), VGS = 5 V 0 Figure 18. Resistive Load Switching Time vs. Gate Resistance 500 1000 RG (W) ID = 2.5 A VDD = 12 V 1500 2000 Figure 19. Drain−Source Voltage Slope during Turn On and Turn Off vs. Gate Resistance www.onsemi.com 6 NCV8402D, NCV8402AD TYPICAL PERFORMANCE CURVES 1000 R(t) (°C/W) 100 10 1 Duty Cycle = 50% 20% 10% 5% 2% 1% 0.1 0.01 0.0000001 Single Pulse 0.000001 0.00001 0.0001 0.001 0.01 0.1 PULSE WIDTH (sec) Figure 20. Transient Thermal Resistance www.onsemi.com 7 1 10 100 1000 NCV8402D, NCV8402AD TEST CIRCUITS AND WAVEFORMS RL VIN + D RG VDD G DUT − S IDS Figure 21. Resistive Load Switching Test Circuit 90% VIN 10% td(ON) tr td(OFF) tf 90% 10% IDS Figure 22. Resistive Load Switching Waveforms www.onsemi.com 8 NCV8402D, NCV8402AD TEST CIRCUITS AND WAVEFORMS L VDS VIN D RG + VDD G DUT − S tp IDS Figure 23. Inductive Load Switching Test Circuit 5V VIN 0V Tav Tp V(BR)DSS Ipk VDD VDS VDS(on) IDS 0 Figure 24. Inductive Load Switching Waveforms www.onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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