NCV8403STT1G

DATA SHEET www.onsemi.com Self-Protected Low Side Driver with Temperature and Current Limit VDSS (Clamped) RDS(on) TYP ID MAX (Limited) 42 V 53 mW @ 10 V 15 A 42 V, 14 A, Single N-Channel Drain NCV8403A, NCV8403B NCV8403A/B is a three terminal protected Low-Side Smart Discrete device. The protection features include overcurrent, overtemperature, ESD and integrated Drain-to-Gate clamping for overvoltage protection. This device offers protection and is suitable for harsh automotive environments. Overvoltage Protection Gate Input ESD Protection Temperature Limit Current Limit Current Sense Features • • • • • • • • • Short Circuit Protection Thermal Shutdown with Automatic Restart Over Voltage Protection Integrated Clamp for Inductive Switching ESD Protection dV/dt Robustness Analog Drive Capability (Logic Level Input) NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Source 4 1 2 • Switch a Variety of Resistive, Inductive and Capacitive Loads • Can Replace Electromechanical Relays and Discrete Circuits • Automotive / Industrial DRAIN 4 3 SOT−223 CASE 318E STYLE 3 4 1 2 Typical Applications MARKING DIAGRAM AYW xxxxxG G 1 2 3 SOURCE GATE DRAIN GATE 3 DPAK CASE 369C DRAIN SOURCE 1 YWW NCV 3 xxxxxG 2 A = Assembly Location Y = Year W, WW = Work Week xxxxx = 8403A or 8403B G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. © Semiconductor Components Industries, LLC, 2016 August, 2022 − Rev. 14 1 Publication Order Number: NCV8403/D NCV8403A, NCV8403B MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage Internally Clamped VDSS 42 Vdc Gate−to−Source Voltage VGS "14 Vdc Drain Current Continuous ID Total Power Dissipation − SOT−223 Version @ TA = 25°C (Note 1) @ TA = 25°C (Note 2) Total Power Dissipation − DPAK Version @ TA = 25°C (Note 1) @ TA = 25°C (Note 2) PD Internally Limited 1.13 1.56 W 1.32 2.5 Thermal Resistance − SOT−223 Version Junction−to−Soldering Point Junction−to−Ambient (Note 1) Junction−to−Ambient (Note 2) Thermal Resistance − DPAK Version Junction−to−Soldering Point Junction−to−Ambient (Note 1) Junction−to−Ambient (Note 2) °C/W RqJS RqJA RqJA 12 110 80 RqJS RqJA RqJA 2.5 95 50 Single Pulse Inductive Load Switching Energy (VDD = 25 Vdc, VGS = 5.0 V, IL = 2.8 A, L = 120 mH, RG = 25 W) EAS 470 mJ Load Dump Voltage (VGS = 0 and 10 V, RI = 2.0 W, RL = 4.5 W, td = 400 ms) VLD 55 V Operating Junction Temperature TJ −40 to 150 °C Storage Temperature Tstg −55 to 150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Surface mounted onto minimum pad size (0.412″ square) FR4 PCB, 1 oz cu. 2. Mounted onto 1″ square pad size (1.127″ square) FR4 PCB, 1 oz cu. + ID DRAIN IG + VDS GATE SOURCE VGS − − Figure 1. Voltage and Current Convention www.onsemi.com 2 NCV8403A, NCV8403B MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 42 40 46 45 51 51 Vdc Vdc − − 0.6 2.5 5.0 − − 50 125 mAdc 1.0 − 1.7 5.0 2.2 − Vdc mV/°C − − 53 95 68 123 − − 63 105 76 135 − 0.95 1.1 OFF CHARACTERISTICS Drain−to−Source Clamped Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) (VGS = 0 Vdc, ID = 250 mAdc, TJ = −40°C to 150°C) (Note 3) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 32 Vdc, VGS = 0 Vdc) (VDS = 32 Vdc, VGS = 0 Vdc, TJ = 150°C) (Note 3) IDSS Gate Input Current (VGS = 5.0 Vdc, VDS = 0 Vdc) IGSS mAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 1.2 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 4) (VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 25°C) (VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 150°C) (Note 3) RDS(on) Static Drain−to−Source On−Resistance (Note 4) (VGS = 5.0 Vdc, ID = 3.0 Adc, TJ @ 25°C) (VGS = 5.0 Vdc, ID = 3.0 Adc, TJ @ 150°C) (Note 3) RDS(on) Source−Drain Forward On Voltage (IS = 7.0 A, VGS = 0 V) VSD mW mW V SWITCHING CHARACTERISTICS (Note 3) Turn−ON Time (10% VIN to 90% ID) tON 44 tOFF 84 tON 15 tOFF 116 −dVDS/dtON 2.43 dVDS/dtOFF 0.83 VIN = 0 V to 5 V, VDD = 25 V ID = 1.0 A, Ext RG = 2.5 W Turn−OFF Time (90% VIN to 10% ID) Turn−ON Time (10% VIN to 90% ID) VIN = 0 V to 10 V, VDD = 25 V, ID = 1.0 A, Ext RG = 2.5 W Turn−OFF Time (90% VIN to 10% ID) Slew−Rate ON (20% VDS to 50% VDS) Vin = 0 to 10 V, VDD = 12 V, RL = 4.7 W Slew−Rate OFF (80% VDS to 50% VDS) ms V/ms SELF PROTECTION CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 5) Current Limit VGS = 5.0 V, VDS = 10 V VGS = 5.0 V, TJ = 150°C (Note 3) ILIM 10 5.0 15 10 20 15 Adc Current Limit VGS = 10 V, VDS = 10 V VGS = 10 V, TJ = 150°C (Note 3) ILIM 12 8.0 17 13 22 18 Adc VGS = 5.0 Vdc (Note 3) TLIM(off) 150 175 200 °C VGS = 5.0 Vdc DTLIM(on) − 15 − °C VGS = 10 Vdc (Note 3) TLIM(off) 150 165 185 °C VGS = 10 Vdc DTLIM(on) − 15 − °C VGS = 5 V ID = 1.0 A IGON Temperature Limit (Turn−off) Thermal Hysteresis Temperature Limit (Turn−off) Thermal Hysteresis GATE INPUT CHARACTERISTICS (Note 3) Device ON Gate Input Current 400 VGS = 10 V ID = 1.0 A Current Limit Gate Input Current VGS = 5 V, VDS = 10 V IGCL VGS = 5 V, VDS = 10 V mA 0.1 0.6 VGS = 10 V, VDS = 10 V Thermal Limit Fault Gate Input Current mA 50 IGTL mA 0.45 1.5 VGS = 10 V, VDS = 10 V ESD ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 3) Electro−Static Discharge Capability Human Body Model (HBM) ESD 4000 − − V Electro−Static Discharge Capability Machine Model (MM) ESD 400 − − V 3. Not subject to production testing. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. 5. Fault conditions are viewed as beyond the normal operating range of the part. www.onsemi.com 3 NCV8403A, NCV8403B TYPICAL PERFORMANCE CURVES 1000 10 TJstart = 25°C Emax (mJ) ILmax (A) TJstart = 25°C TJstart = 150°C 1 10 100 100 10 100 L (mH) L (mH) Figure 2. Single Pulse Maximum Switch−off Current vs. Load Inductance Figure 3. Single−Pulse Maximum Switching Energy vs. Load Inductance 100 1000 TJstart = 25°C Emax (mJ) ILmax (A) TJstart = 150°C 10 TJstart = 25°C TJstart = 150°C TJstart = 150°C 1 10 TIME IN CLAMP (ms) Figure 4. Single Pulse Maximum Inductive Switch−off Current vs. Time in Clamp Figure 5. Single−Pulse Maximum Inductive Switching Energy vs. Time in Clamp 6V 7V 8V 20 9V −40°C VDS = 10 V 10 V 20 ID (A) 1 TIME IN CLAMP (ms) 25 25°C 15 5V 4V 15 Ta = 25°C 10 100°C 10 150°C 3V 5 5 0 100 10 ID (A) 1 VGS = 2.5 V 0 1 2 3 4 0 5 1.0 1.5 2.0 2.5 3.0 3.5 VDS (V) VGS (V) Figure 6. On−state Output Characteristics Figure 7. Transfer Characteristics www.onsemi.com 4 4.0 NCV8403A, NCV8403B TYPICAL PERFORMANCE CURVES 100 150 150°C 125 80 100 100°C 75 25°C 100°C, VGS = 5 V 100°C, VGS = 10 V 60 25°C, VGS = 5 V 50 25°C, VGS = 10 V −40°C, VGS = 5 V 30 −40°C 3 150°C, VGS = 10 V 70 40 50 25 150°C, VGS = 5 V 90 RDS(on) (mW) RDS(on) (mW) ID = 3 A 4 5 6 7 8 9 20 10 1 Figure 8. RDS(on) vs. Gate−Source Voltage Figure 9. RDS(on) vs. Drain Current 25 −40°C 1.75 20 25°C 1.50 1.25 ILIM (A) NORMALIZED RDS(on) −40°C, VGS = 10 V 7 9 8 10 6 ID (A) ID = 5 A VGS = 5 V 1.00 VGS = 10 V 0.75 15 100°C 10 150°C 5 VDS = 10 V 0.50 −40 −20 0 20 60 40 80 100 120 0 140 5 6 7 8 9 T (°C) VGS (V) Figure 10. Normalized RDS(on) vs. Temperature Figure 11. Current Limit vs. Gate−Source Voltage 25 100 VDS = 10 V 150°C 1 IDSS (mA) VGS = 5 V 10 0.1 100°C 0.01 25°C 0.001 5 10 VGS = 0 V 10 VGS = 10 V 20 ILIM (A) 5 4 VGS (V) 2.00 15 3 2 −40°C 0.0001 0 −40 −20 0 20 40 60 80 100 120 0.00001 140 10 15 20 25 30 35 TJ (°C) VDS (V) Figure 12. Current Limit vs. Junction Temperature Figure 13. Drain−to−Source Leakage Current www.onsemi.com 5 40 NCV8403A, NCV8403B TYPICAL PERFORMANCE CURVES 1.0 ID = 1.2 mA VDS = VGS 1.1 VSD (V) 1.0 0.9 0.7 0.8 25°C 0.7 100°C 0.6 150°C 0 20 40 80 60 100 0.5 120 140 DRAIN−SOURCE VOLTAGE SLOPE (V/ms) 100 td(off) 50 tf tr td(on) 4 5 6 7 8 9 10 7 9 8 10 3.0 VDD = 25 V ID = 5 A RG = 0 W 2.5 −dVDS/dt(on) 2.0 1.5 1.0 dVDS/dt(off) 0.5 0 3 4 5 6 7 8 9 10 Figure 16. Resistive Load Switching Time vs. Gate−Source Voltage Figure 17. Resistive Load Switching Drain−Source Voltage Slope vs. Gate−Source Voltage 75 VDD = 25 V ID = 5 A td(off), VGS = 5 V tf, VGS = 5 V tf, VGS = 10 V tr, VGS = 5 V td(on), VGS = 5 V td(on), VGS = 10 V 0 6 VGS (V) td(off), VGS = 10 V 0 5 VGS (V) 100 25 4 Figure 15. Source−Drain Diode Forward Characteristics 150 50 3 Figure 14. Normalized Threshold Voltage vs. Temperature VDD = 25 V ID = 5 A RG = 0 W 3 2 IS (A) 200 0 1 T (°C) 250 TIME (ms) −40°C VGS = 0 V 0.6 −40 −20 TIME (ms) 0.9 0.8 500 1000 tr, VGS = 10 V 1500 2000 DRAIN−SOURCE VOLTAGE SLOPE (V/ms) NORMALIZED VGS(th) (V) 1.2 2.50 −dVDS/dt(on), VGS = 10 V 2.25 2.00 VDD = 25 V ID = 5 A 1.75 1.50 1.25 dVDS/dt(off), VGS = 5 V 1.00 dVDS/dt(off), VGS = 10 V 0.75 0.50 −dVDS/dt(on), VGS = 5 V 0 500 1000 1500 2000 RG (W) RG (W) Figure 18. Resistive Load Switching Time vs. Gate Resistance Figure 19. Drain−Source Voltage Slope during Turn On and Turn Off vs. Gate Resistance www.onsemi.com 6 NCV8403A, NCV8403B 150 150 125 125 RqJA (°C/W) RqJA (°C/W) TYPICAL PERFORMANCE CURVES 100 PCB Cu thickness, 1.0 oz 75 100 75 PCB Cu thickness, 2.0 oz PCB Cu thickness, 1.0 oz 50 50 25 25 PCB Cu thickness, 2.0 oz 0 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 700 COPPER HEAT SPREADER AREA (mm2) COPPER HEAT SPREADER AREA (mm2) Figure 20. RqJA vs. Copper Area − SOT−223 Figure 21. RqJA vs. Copper Area − DPAK 800 1000 R(t) °C/W 100 10 1 50% Duty Cycle 20% 10% 5% 2% 1% 0.1 0.01 Single Pulse 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 10 100 1000 PULSE TIME (sec) Figure 22. Transient Thermal Resistance − SOT−223 Version 100 50% Duty Cycle R(t) °C/W 10 20% 10% 5% 1 2% 1% 0.1 0.01 Single Pulse 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 PULSE TIME (sec) Figure 23. Transient Thermal Resistance − DPAK Version www.onsemi.com 7 NCV8403A, NCV8403B TEST CIRCUITS AND WAVEFORMS RL VIN + D RG VDD G DUT − S IDS Figure 24. Resistive Load Switching Test Circuit 90% 10% VIN tON tOFF 90% 10% IDS Figure 25. Resistive Load Switching Waveforms www.onsemi.com 8 NCV8403A, NCV8403B TEST CIRCUITS AND WAVEFORMS L VDS VIN D RG + VDD G DUT − S tp IDS Figure 26. Inductive Load Switching Test Circuit 5V VIN 0V Tav Tp V(BR)DSS Ipk VDD VDS VDS(on) IDS 0 Figure 27. Inductive Load Switching Waveforms www.onsemi.com 9 NCV8403A, NCV8403B ORDERING INFORMATION Package Shipping† NCV8403ASTT1G SOT−223 (Pb−Free) 1000 / Tape & Reel NCV8403ASTT3G SOT−223 (Pb−Free) 4000 / Tape & Reel NCV8403ADTRKG DPAK (Pb−Free) 2500 / Tape & Reel NCV8403BDTRKG DPAK (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−223 (TO−261) CASE 318E−04 ISSUE R DATE 02 OCT 2018 SCALE 1:1 q q DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com SOT−223 (TO−261) CASE 318E−04 ISSUE R STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. ANODE CATHODE NC CATHODE STYLE 6: PIN 1. 2. 3. 4. RETURN INPUT OUTPUT INPUT STYLE 7: PIN 1. 2. 3. 4. ANODE 1 CATHODE ANODE 2 CATHODE STYLE 11: PIN 1. MT 1 2. MT 2 3. GATE 4. MT 2 STYLE 3: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 8: STYLE 12: PIN 1. INPUT 2. OUTPUT 3. NC 4. OUTPUT CANCELLED DATE 02 OCT 2018 STYLE 4: PIN 1. 2. 3. 4. SOURCE DRAIN GATE DRAIN STYLE 5: PIN 1. 2. 3. 4. STYLE 9: PIN 1. 2. 3. 4. INPUT GROUND LOGIC GROUND STYLE 10: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE DRAIN GATE SOURCE GATE STYLE 13: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR GENERIC MARKING DIAGRAM* AYW XXXXXG G 1 A = Assembly Location Y = Year W = Work Week XXXXX = Specific Device Code G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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