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regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
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Self-Protected Low Side
Driver with In-Rush Current
Management
NCV8412, NCV8412D
•
Typical Applications
• Switch a Variety of Resistive, Inductive and Capacitive Loads
• Can Replace Electromechanical Relays and Discrete Circuits
• Automotive/Industrial
Drain
Gate
Input
ESD Protection
Current
Limit
42 V
145 mW @ 10 V
5.9 A
SOT−223 (TO−261)
CASE 318E
SOIC−8 NB
CASE 751
DRAIN 1
DRAIN 1
DRAIN 2
DRAIN 2
MARKING DIAGRAM
DRAIN
4
AYW
8412A G
G
2
3
1
8
1
8412AD
ALYWX
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
8412A or 8412AD
= Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
Overvoltage
Protection
Temperature
Limit
ID MAX
(Limited)
SOURCE 1
GATE 1
SOURCE 2
GATE 2
•
•
•
•
Short−Circuit Protection with In−Rush Current Management
Delta Thermal Shutdown
Thermal Shutdown with Automatic Restart
Overvoltage Protection
Integrated Clamp for Overvoltage Protection and Inductive
Switching
ESD Protection
dV/dt Robustness
Analog Drive Capability (Logic Level Input)
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101 Grade 1
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
RDS(ON) TYP
SOURCE
•
•
•
•
•
VDSS
(Clamped)
DRAIN
Features
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GATE
The NCV8412 is a three terminal protected Low−Side Smart
Discrete FET. The protection features include Delta Thermal
Shutdown, overcurrent, overtemperature, ESD and integrated
Drain−to−Gate clamping for overvoltage protection. The device also
offers fault indication via the gate pin. This device is suitable for harsh
automotive environments.
Current
Sense
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
Source
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2019
December, 2020 − Rev. 1
1
Publication Order Number:
NCV8412/D
NCV8412, NCV8412D
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Drain−to−Source Voltage Internally Clamped
VDSS
42
V
Drain−to−Gate Voltage Internally Clamped
VDG
42
V
Gate−to−Source Voltage
VGS
"14
V
Drain Current − Continuous
ID
Total Power Dissipation (SOT−223)
Internally Limited
@ TA = 25°C (Note 1)
@ TA = 25°C (Note 2)
PD
Power Dissipation per Channel (SOIC−8 Dual), both channels loaded equally
@ TA = 25°C (Note 1)
@ TA = 25°C (Note 2)
PD
Total Power Dissipation (SOIC−8 Dual), only one channel loaded
PD
0.93
1.20
W
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Junction−to−Case (Soldering Point)
RqJA
RqJA
RqJS
97.0
57.0
7.9
°C/W
Thermal Resistance (SOIC−8 Dual), both channels loaded equally Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Junction−to−Case (Soldering Point)
RqJA
RqJA
RqJS
107.8
79.4
29.0
°C/W
Thermal Resistance (SOIC−8 Dual), only one channel loaded
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Junction−to−Case (Soldering Point)
RqJA
RqJA
RqJS
133.6
103.8
29.1
°C/W
Single Pulse Inductive Load Switching Energy
(L = 50 mH, ILpeak = 2 A, VGS = 5 V, RG = 25 W, TJstart = 25°C)
EAS
100
mJ
Load Dump Voltage
US *
55
V
TJ
−40 to 150
°C
Tstorage
−55 to 150
°C
Thermal Resistance (SOT−223)
@ TA = 25°C (Note 1)
@ TA = 25°C (Note 2)
(VGS = 0 and 10 V, RL = 22 W) (Note 3)
Operating Junction Temperature
Storage Temperature
1.28
2.19
0.57
0.78
W
W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Mounted onto a 80 x 80 x 1.6 mm single layer FR4 board (100 sq mm, 1 oz. Cu, steady state)
2. Mounted onto a 80 x 80 x 1.6 mm single layer FR4 board (645 sq mm, 1 oz. Cu, steady state)
3. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class C according to ISO16750−1.
ESD ELECTRICAL CHARACTERISTICS (Notes 4, 5)
Parameter
Electro−Static Discharge Capability
Test Condition
Symbol
Min
Human Body Model (HBM)
ESD
4000
Charged Device Model (CDM)
Typ
Max
Unit
V
1000
4. Not tested in production.
5. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JS−001−2017)
Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes smaller than
2 x 2 mm due to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current
waveform characteristic defined in JEDEC JS−002−2018.
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2
NCV8412, NCV8412D
+
ID
DRAIN
IG
+
VDS
GATE
SOURCE
VGS
−
−
Figure 2. Voltage and Current Convention
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3
NCV8412, NCV8412D
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
VGS = 0 V, ID = 10 mA
V(BR)DSS
42
44
49
V
39
42
49
0.7
4.0
2.3
20
52
72
mA
1.6
2.2
V
OFF CHARACTERISTICS
Drain−to−Source Clamped Breakdown
Voltage
VGS = 0 V, ID = 10 mA, TJ = 150°C
(Note 6)
VGS = 0 V, VDS = 32 V
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V, VDS = 32 V, TJ = 150°C
(Note 6)
Gate Input Current
VGS = 5 V, VDS = 0 V
IGSS
VGS = VDS, ID = 150 mA
VGS(th)
VGS = VDS, ID = 150 mA (Note 6)
VGS(th)/TJ
3.1
VGS = 10 V, ID = 1.7 A
RDS(ON)
145
200
VGS = 10 V, ID = 1.7 A, TJ = 150°C
(Note 6)
255
400
mA
ON CHARACTERISTICS
Gate Threshold Voltage
Gate Threshold Temperature Coefficient
Static Drain−to−Source On Resistance
1.0
mV/°C
mW
VGS = 5.0 V, ID = 1.7 A
180
230
VGS = 5.0 V, ID = 1.7 A, TJ = 150°C
(Note 6)
310
460
VGS = 5.0 V, ID = 0.5 A
180
230
VGS = 5.0 V, ID = 0.5 A, TJ = 150°C
(Note 6)
305
460
VSD
0.95
1.2
V
tON
20
31
ms
Source−to−Drain Forward On Voltage
IS = 7 A, VGS = 0 V
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Time (10% VGS to 90% ID)
Turn−On Rise Time (10% ID to 90% ID)
Turn−Off Time (90% VGS to 10% ID)
VGS = 0 V to 10 V,
VDD = 12 V, ID = 1 A
Turn−Off Fall Time (90% ID to 10% ID)
trise
14
25
ms
tOFF
96
140
ms
tfall
37
50
ms
Slew Rate On (80% VDS to 50% VDS)
−dVDS/dtON
0.45
1.0
V/ms
Slew Rate Off (50% VDS to 80% VDS)
dVDS/dtOFF
0.3
0.4
V/ms
ILIM
SELF PROTECTION CHARACTERISTICS
VDS = 10 V, VGS = 5.0 V
Current Limit
3.3
4.4
5.6
VDS = 10 V, VGS = 5.0 V, TJ = 150°C
(Note 6)
3.3
4.0
4.9
VDS = 10 V, VGS = 10 V (Note 6)
2.6
3.9
5.9
VDS = 10 V, VGS = 10 V, TJ = 150°C
(Note 6)
2.3
3.5
5.0
150
175
190
Temperature Limit (Turn−Off)
Thermal Hysteresis
Temperature Limit (Turn−Off)
Thermal Hysteresis
VGS = 5.0 V (Note 6)
VGS = 10 V (Note 6)
TLIM(OFF)
°C
15
DTLIM(ON)
TLIM(OFF)
A
150
185
200
15
DTLIM(ON)
GATE INPUT CHARACTERISTICS (Note 6)
Device ON Gate Input Current
VGS = 5 V, VDS = 10 V, ID = 1 A
IGON
VGS = 10 V, VDS = 10 V, ID = 1 A
Current Limit Gate Input Current
VGS = 5 V, VDS = 10 V
IGCL
VGS = 10 V, VDS = 10 V
Thermal Limit Gate Input Current
VGS = 5 V, VDS = 10 V, ID = 0 A
VGS = 10 V, VDS = 10 V, ID = 0 A
IGTL
25
52
72
250
333
480
35
65
96
200
390
540
550
630
750
1350
1500
1650
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Not tested in production.
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4
NCV8412, NCV8412D
TYPICAL PERFORMANCE CURVES
10
Emax (mJ)
IL(max) (A)
1000
TJstart = 25°C
TJstart = 25°C
100
TJstart = 150°C
TJstart = 150°C
1
10
10
100
L (mH)
10
Figure 3. Single Pulse Maximum Switch−off
Current vs. Load Inductance
100
L (mH)
Figure 4. Single Pulse Maximum Switching
Energy vs. Load Inductance
10
1000
TJstart = 150°C
1
0.1
Emax (mJ)
IL(max) (A)
TJstart = 25°C
1
100
TJstart = 150°C
10
10
TIME IN CLAMP (ms)
TJstart = 25°C
1
Figure 5. Single Pulse Maximum Inductive
Switch−off Current vs. Time in Clamp
5
TA = 25°C
6V
10 V
4
4V
3
VDS = 10 V
25°C
4
5V
ID (A)
ID (A)
Figure 6. Single Pulse Maximum Inductive
Switching Energy vs. Time in Clamp
5
8V
10
TIME IN CLAMP (ms)
3.5 V
2
−40°C
150°C
3
105°C
2
3V
1
1
0
VGS = 2.5 V
0
1
2
3
4
0
5
VDS (V)
1
3
VGS (V)
Figure 7. On−state Output Characteristics
Figure 8. Transfer Characteristics
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5
2
4
5
NCV8412, NCV8412D
TYPICAL PERFORMANCE CURVES
400
350
150°C, ID = 1.7 A
150°C, ID = 0.5 A
150°C, VGS = 5 V
300
105°C, VGS = 10 V
200
RDS(on) (mW)
RDS(on) (mW)
300
105°C, ID = 1.7 A
105°C, ID = 0.5 A
25°C, ID = 1.7 A
25°C, ID = 0.5 A
100
−40°C, ID = 1.7 A
0
4
2
5
−40°C, ID = 0.5 A
150°C, VGS = 10 V
105°C, VGS = 5 V
200
25°C, VGS = 5 V
150
25°C, VGS = 10 V
−40°C, VGS = 5 V
100
−40°C, VGS = 10 V
6
7
8
9
50
10
VGS (V)
1
1.2
ID (A)
Figure 9. RDS(on) vs. Gate−Source Voltage
Figure 10. RDS(on) vs. Drain Current
0.2 0.4
0.8
1.4
1.6
1.8
2
VDS = 10 V
7
VGS = 5 V
6
VGS = 10 V
1
ILIM (A)
1.5
1.25
25°C
−40°C
5
150°C
4
0.75
105°C
3
0.5
−40
−20
0
20
40
60
TJ (°C)
80
100
120
2
140
5
6
5.5
7
8
9
10
VGS (V)
Figure 11. Normalized RDS(on) vs. Temperature
Figure 12. Current Limit vs. Gate−Source
Voltage
100
VDS = 10 V
VGS = 0 V
10
5
4.5
IDSS (mA)
ILIM (A)
0.6
8
ID = 1.7 A
1.75
RDS(on) (NORMIALZIZED)
250
VGS = 10 V
4
1
150°C
0.1
105°C
VGS = 5 V
3.5
3
−40
−20
0
20
40
60
80
100
120
0.01
0.001
140
25°C
−40°C
10
15
20
25
30
35
TJ (°C)
VDS (V)
Figure 13. Current Limit vs. Junction
Temperature
Figure 14. Drain−to−Source Leakage Current
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6
40
NCV8412, NCV8412D
TYPICAL PERFORMANCE CURVES
1.1
ID = 150 mA
VGS = VDS
1.1
1
VSD (V)
NORMALIZED VGS(th) (V)
1.2
0.9
1
−40°C
0.9
25°C
0.8
105°C
0.8
0.7
0.7
0.6
0.6
−40
0.5
−20
0
20
40
60
80
100
120
140
150°C
VGS = 0 V
1
TJ (°C)
tr
TIME (ms)
120
ID = 1 A
VDD = 12 V
RG = 0 W
tON
100
tOFF
80
60
40
tf
20
0
3
4
5
6
7
VGS (V)
8
9
10
1.5
TIME (ms)
tOFF, (VGS = 5 V)
60
tON, (VGS = 5 V)
tf, (VGS = 10 V)
40
tr, (VGS = 5 V)
tf, (VGS = 5 V)
20
0
DRAIN−SOURCE VOLTAGE SLOPE (V/ms)
ID = 1 A
VDD = 12 V
tON, (VGS = 10 V)
tr, (VGS = 10 V)
0
500
1000
RG (W)
1500
6
7
8
9
10
−dVDS/dtON
1.0
dVDS/dtOFF
0.5
0
3
4
5
6
7
VGS (V)
8
9
10
Figure 18. Resistive Load Switching
Drain−Source Voltage Slope vs. Gate−Source
Voltage
tOFF, (VGS = 10 V)
80
5
ID = 1 A
VDD = 12 V
RG = 0 W
Figure 17. Resistive Load Switching Time vs.
Gate−Source Voltage
100
4
Figure 16. Source−Drain Diode Forward
Characteristics
DRAIN−SOURCE VOLTAGE SLOPE (V/ms)
140
3
IS (A)
Figure 15. Normalized Threshold Voltage vs.
Temperature
160
2
2000
1.4
−dVDS/dtON, VGS = 10 V
1.2
ID = 1 A
VDD = 12 V
1
0.8
dVDS/dtOFF, VGS = 5 V
0.6
0.4
dVDS/dtOFF, VGS = 10 V
−dVDS/dtON, VGS = 5 V
0.2
0
0
Figure 19. Resistive Load Switching Time vs.
Gate Resistance
500
1000
RG (W)
1500
2000
Figure 20. Drain−Source Voltage Slope during
Turn On and Turn Off vs. Gate Resistance
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7
NCV8412, NCV8412D
TYPICAL PERFORMANCE CURVES
140
100
90
RqJA (°C/W)
RqJA (°C/W)
80
70
60
PCB Cu thickness, 2.0 oz
50
PCB Cu thickness, 2.0 oz,
only 1 channel loaded
120
PCB Cu thickness, 1.0 oz
40
PCB Cu thickness, 1.0 oz, only 1 channel loaded
130
110
100
90
80
PCB Cu thickness,
2.0 oz, both channels loaded equally
70
60
700
100 200 300
400
500
600
COPPER HEAT SPREADER AREA (mm2)
0
800
50
0
Figure 21. RqJA vs. Copper Area − SOT−223
PCB Cu thickness, 1.0 oz,
both channels loaded equally
100
200
300
400
500
600 700
COPPER HEAT SPREADER AREA (mm2)
800
Figure 22. RqJA vs. Copper Area − SOIC−8
Dual
100
RqJA(t) (°C/W)
50% Duty Cycle
20%
10 10%
5%
1
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
80 x 80 x 1.6 mm Single−Layer PCB, 645 mm2 1 oz. Copper
0.0001
0.001
0.01
0.1
1
PULSE WIDTH (sec)
Figure 23. Transient Thermal Resistance − SOT−223
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8
10
100
1000
NCV8412, NCV8412D
TYPICAL PERFORMANCE CURVES
1000
RqJA(t) (°C/W)
100
50% Duty Cycle
20%
10%
10 5%
2%
1
0.1
1%
80 x 80 x 1.6 mm Single−Layer PCB, 645 mm2 1 oz. Copper
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE WIDTH (sec)
Figure 24. Transient Thermal Resistance − SOIC−8 Dual, only 1 channel loaded
RqJA(t) (°C/W)
100
50% Duty Cycle
20%
10 10%
5%
2%
1
1%
0.1
80 x 80 x 1.6 mm Single−Layer PCB, 645 mm2 1 oz. Copper
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
PULSE WIDTH (sec)
Figure 25. Transient Thermal Resistance − SOIC−8 Dual, both channels loaded equally
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9
1000
NCV8412, NCV8412D
APPLICATION INFORMATION
Circuit Protection Features
junction temperature is exceeded. When activated at
typically 175°C, the NCV8412 turns off. This feature is
provided to prevent failures from accidental overheating.
The NCV8412 has three main protections. Current Limit,
Thermal Shutdown and Delta Thermal Shutdown. These
protections establish robustness of the NCV8412.
EMC Performance
Current Limit and Short Circuit Protection
If better EMC performance is needed, connect a small
ceramic capacitor to the drain pin as close to the device as
possible according to Figure 26.
The NCV8412 has current sense element. In the event that
the drain current reaches designed current limit level,
integrated Current Limit protection establishes its constant
level.
Delta Thermal Shutdown
Delta Thermal Shutdown (DTSD) Protection increases
higher reliability of the NCV8412. DTSD consist of two
independent temperature sensors – cold and hot sensors. The
NCV8412 establishes a slow junction temperature rise by
sensing the difference between the hot and cold sensors.
ON/OFF output cycling is designed with hysteresis that
results in a controlled saw tooth temperature profile
(Figure 27). The die temperature slowly rises (DTSD) until
the absolute temperature shutdown (TSD) is reached around
175°C.
Thermal Shutdown with Automatic Restart
Internal Thermal Shutdown (TSD) circuitry is provided to
protect the NCV8412 in the event that the maximum
Figure 26. EMC Capacitor Placement
TEST CIRCUITS AND WAVEFORMS
Thermal Transient Limitation Phase
Overtemperature
Cycling
VG
ILIM
ID
INOM
TSD
Delta TSD
activation
TJ
Time
Figure 27. Overload Protection Behavior
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10
Nominal
Load
NCV8412, NCV8412D
RL
VIN
D
RG
VDD
G DUT
S
IDS
Figure 28. Resistive Load Switching Test Circuit
Figure 29. Resistive Load Switching Waveforms
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11
+
−
NCV8412, NCV8412D
L
VDS
VIN
D
RG
+
VDD
G DUT
−
S
tp
IDS
Figure 30. Inductive Load Switching Test Circuit
5V
VIN
0V
tav
tp
V(BR)DSS
Ipk
VDD
VDS
IDS
VDS(on)
Time
Figure 31. Inductive Load Switching Waveforms
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12
0
NCV8412, NCV8412D
DEVICE ORDERING INFORMATION
Marking
Package
Shipping†
NCV8412ASTT1G
8412A
SOT−223
(Pb−Free)
1,000 / Tape & Reel
NCV8412ASTT3G
8412A
SOT−223
(Pb−Free)
1,000 / Tape & Reel
NCV8412ADDR2G
8412AD
SOIC−8
(Pb−Free)
2,500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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13
NCV8412, NCV8412D
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
q
q
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14
NCV8412, NCV8412D
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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