NCV8460ADR2G

DATA SHEET www.onsemi.com Self Protected High Side Driver with Temperature Shutdown and Current Limit NCV8460A The NCV8460A is a fully protected High−Side driver that can be used to switch a wide variety of loads, such as bulbs, solenoids and other acuators. The device is internally protected from an overload condition by an active current limit and thermal shutdown. A diagnostic output reports ON and OFF state open load conditions as well as thermal shutdown. Features • • • • • • • • • • • • PRODUCT SUMMARY Parameter Symbol Value Units Operating Voltage Range VS 6 to 36 V RDSon(max) TJ = 25°C RON 60 mW Output Current Limit (min) Ilim 6 A MARKING DIAGRAM 8 SO−8 D SUFFIX CASE 751 8 1 Short Circuit Protection Thermal Shutdown with Automatic Restart CMOS compatible control input Open Load Detection in On and Off State Diagnostic Output Undervoltage and Overvoltage Shutdown Loss of Ground Protection ESD protection Slew Rate Control for Low EMI Switching Very Low Standby Current NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant Typical Applications • Switch a Variety of Resistive, Inductive and Capacitive Loads • Can Replace Electromechanical Relays and Discrete Circuits • Automotive / Industrial V8460A ALYW G 1 V8460A = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package PIN CONNECTIONS GND 1 8 VD IN 2 7 OUT STAT 3 6 OUT 5 VD NC 4 (Top View) ORDERING INFORMATION Device Package Shipping† NCV8460ADR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 August, 2021 − Rev. 10 1 Publication Order Number: NCV8460/D NCV8460A VD Overvoltage Detection Undervoltage Detection Regulated Chargepump Output Clamping Input Buffer IN Pre Driver Control Logic í Current Limitation STAT Overtemperature Detection On−State Open Load Detection GND Off−State Open Load Detection Figure 1. Block Diagram PIN DESCRIPTION Pin # Symbol Description 1 GND 2 IN 3 STAT Status Output 4 N/C No Connection 5 VD Supply Voltage 6 OUT Output 7 OUT Output 8 VD Ground Logic Level Input Supply Voltage www.onsemi.com 2 OUT NCV8460A MAXIMUM RATINGS Value Rating DC Supply Voltage Peak Transient Input Voltage (Load Dump 42.5 V, VD = 13.5 V, RLOAD = 6.5 W, ISO7637−2 pulse 5) Symbol Min Max Unit VD −0.3 41 V 56 V Vpeak Input Voltage Vin −8 8 V Input Current Iin −5 5 mA Output Current (Note 1) Iout −6 Internally Limited A Negative Ground Current −Ignd −200 − mA Status Current Istatus −5 5 mA Power Dissipation, TA = 25°C Ptot Electrostatic Discharge (HBM Model 100 pF / 1500 W) Input Status Output VD 1.183 W DC Single Pulse Inductive Load Switching Energy (Note 2) (L = 1.8 mH, Vbat = 13.5 V; IL = 9 A, TJstart = 150°C) Operating Junction Temperature Storage Temperature 4 3.5 5 5 kV kV kV kV EAS 100 mJ TJ −40 +150 °C Tstorage −55 +150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Reverse Output current has to be limited by the load to stay within absolute maximum ratings and thermal performance. 2. Not subjected to production testing. THERMAL RESISTANCE RATINGS Parameter Thermal Resistance Junction−to−Lead Junction−to−Ambient (min. Pad) Junction−to−Ambient (1” square pad size, FR−4, 1 oz Cu) www.onsemi.com 3 Symbol Max Value Unit RqJL RqJA RqJA 30 110.8 105.6 °C/W °C/W °C/W NCV8460A ELECTRICAL CHARACTERISTICS (8 ≤ VD ≤ 36 V; −40°C < TJ < 150°C unless otherwise specified) Value Rating Typ Max Unit VD 6 − 36 V VUV 3 5 Symbol Operating Supply Voltage Undervoltage Shutdown Undervoltage Min Conditions VUV_Rst Overvoltage Shutdown VOV On Resistance RON Iout = 2 A; TJ = 25°C, VD > 8 V Iout = 2 A, VD > 8 V Standby Current ID Off State, Vin = Vout = 0 V, VD = 13.5 V On State; Vin = 5 V, VD = 13.5 V, Iout = 0 A Output Leakage Current IL Vin = Vout = 0 V Vin = 0 V, Vout = 3.5 V Vin = Vout = 0 V, VD = 13.5 V 6 V 6.5 V 60 120 mW 20 3.5 mA mA 50 10 3 mA 1.25 V 36 V 10 1.5 −20 INPUT CHARACTERISTICS Input Voltage − Low Vin_low Input Current − Low Iin_low Input Voltage − High Vin_high Input Current − High Iin_high Vin = 1.25 V 1 mA 3.25 V Vin = 3.25 V 10 0.25 mA Input Hysteresis Voltage Vhyst Input Clamp Voltage Vin_cl Iin = 1 mA Iin = −1 mA Turn−On Delay Time td_on to 10% Vout, VD = 13.5 V, RL = 6.5 W 40 ms Turn−Off Delay Time td_off to 90% Vout, VD = 13.5 V, RL = 6.5 W 30 ms Slew Rate On dVout / dton 10% to 80% Vout, VD = 13.5 V, RL = 6.5 W 0.9 V / ms Slew Rate Off dVout / dtoff 90% to 10% Vout, VD = 13.5 V, RL = 6.5 W 0.7 V / ms 11 −13 V 12 −12 13 −11 V SWITCHING CHARACTERISTICS OUTPUT DIODE CHARACTERISTICS (Note 3) Forward Voltage VF Iout = −1.3 A, TJ = 150°C 0.6 V STATUS PIN CHARACTERISTICS Status Output Voltage Low Status Leakage Current Vstat_low Istat = 1.6 mA 0.2 0.5 V Istat_leakage Vstat = 5 V 1 10 mA Cstat Vstat = 5 V (Note 3) Vstat_cl Istat =1 mA Istat = −1 mA Status Pin Input Capacitance Status Clamp Voltage 100 pF 10 −2.2 11 −1.2 12 −0.6 V 200 °C PROTECTION FUNCTIONS (Note 4) Temperature Shutdown (Note 3) TSD 150 175 Temperature Shutdown Hysteresis (Note 3) TSD_hyst 7 15 6 9 Output Current Limit Ilim 8 V < VD < 36 V 6 V < VD < 36 V Status Delay in Overload td_stat Switch Off Output Clamp Voltage Vclamp Iout = 2 A, Vin = 0 V, L = 6 mH VD − 41 VD − 45 °C 15 A 15 A 20 ms VD − 55 V 3. Not subjected to production testing 4. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper hardware/software strategy. If the devices operates under abnormal conditions this hardware/software solutions must limit the duration and number of activation cycles. www.onsemi.com 4 NCV8460A ELECTRICAL CHARACTERISTICS (8 ≤ VD ≤ 36 V; −40°C < TJ < 150°C unless otherwise specified) Value Rating Symbol Conditions Min 30 Typ Max Unit 500 mA 220 ms 3.5 V 1000 ms DIAGNOSTICS CHARACTERISTICS Openload On State Detection Threshold IOL Vin = 5 V Openload On State Detection Delay td_OL_on Iout = 0 A Openload Off State Detection Threshold VOL Vin = 0 V Openload Detection Delay at Turn Off td_OL_off 1.5 − 3. Not subjected to production testing 4. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper hardware/software strategy. If the devices operates under abnormal conditions this hardware/software solutions must limit the duration and number of activation cycles. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Iout < IOL VIN TJ > TJ_TSD VIN Vout > VOL VSTAT VSTAT Td_STAT Td_OL_off Td_OL_on Td_STAT Figure 2. Open Load Status Timing (with external pull−up) Figure 3. Overtemperature Status Timing Vout 90% 80% dVout / dt(on) dVout / dt(off) 10% t td(on) td(off) Vin t Figure 4. Switching Timing Diagram www.onsemi.com 5 NCV8460A STATUS PIN TRUTH TABLE Input Output Status Normal Operation Conditions L H L H H H Undervoltage L H L L X X Overvoltage L H L L H H Current Limitation L H H L X X H (TJ < TSD) H (TJ > TSD) L Overtemperature L H L L H L Output Voltage > VOL L H H H L H Output Current < IOL L H L H H L www.onsemi.com 6 NCV8460A TYPICAL CHARACTERISTICS CURVES 5.6 45 5.4 44 43 5.0 VOV (V) VUV (V) 5.2 4.8 42 41 40 4.6 39 4.4 38 4.2 −50 37 0 50 100 50 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 6. Overvoltage Shutdown vs. Temperature 148 140 128 120 150 100 Ioff (mA) 108 88 68 80 150°C 60 40 25°C 48 25°C −40°C 20 −40°C 28 0 0 5 10 15 20 25 30 35 40 VD (V) 30 VD (V) Figure 7. RDS(on) vs. VD Figure 8. OFF State Standby Current vs. VD 0 120 4 100 3.5 VIN HIGH (V) 150°C 80 IL (mA) 0 Figure 5. Undervoltage Shutdown vs. Temperature 150°C RDS(on) (mW) −50 150 60 40 25°C 10 20 40 50 3 2.5 2 1 −50 0 0 20 1.5 −40°C 20 10 30 40 0 50 100 150 VD (V) TEMPERATURE (°C) Figure 9. Output Leakage vs. VD Vout = 0 V Figure 10. Vin Threshold High vs. Temperature www.onsemi.com 7 NCV8460A TYPICAL CHARACTERISTICS CURVES 10 4 9 3.5 Iin @ 5 V 7 3 Iin (mA) Vin LOW (V) 8 2.5 6 5 Iin @ 3.25 V 4 2 3 Iin @ 1.25 V 1.5 2 1 −50 0 50 100 1 −50 150 150 Figure 12. Input Current vs. Temperature −10.5 13 −11 Vin_cl (neg) (V) 13.5 Vin_cl (pos) (V) 100 Figure 11. Vin Threshold Low vs. Temperature −10 12.5 12 11.5 −11.5 −12 −12.5 −13 11 −13.5 10.5 −14 10 −50 0 50 100 150 −50 0 50 150 TEMPERATURE (°C) Figure 13. Input Clamp Voltage (Positive) vs. Temperature Figure 14. Input Clamp Voltage (Negative) vs. Temperature 90 90 80 80 25°C 70 −40°C 60 60 Toff (ms) −40°C 50 150°C 40 100 TEMPERATURE (°C) 70 Ton (ms) 50 TEMPERATURE (°C) 14 25°C 50 40 30 30 20 20 10 10 0 0 TEMPERATURE (°C) 150°C 0 0 10 20 VD (V) 30 40 0 Figure 15. Turn On Time vs. VD 5 10 15 20 VD (V) 25 30 Figure 16. Turn Off Time vs. VD www.onsemi.com 8 35 40 NCV8460A TYPICAL CHARACTERISTICS CURVES 1.6 0.70 1.4 25°C 1.2 0.50 dVout / dt(off) (mS) dVout / dt(on) (mS) 0.60 0.40 0.30 −40°C 150°C 0.20 25°C 0.8 0.6 −40°C 0.4 0.10 0 1.0 150°C 0.2 0 5 10 15 20 25 30 35 0 40 0 5 10 15 20 25 30 VD (V) VD (V) Figure 17. Slew Rate ON vs. VD Figure 18. Slew Rate OFF vs. VD 35 40 300 0.9 0.85 Vstat_low (mV) 0.75 VF (V) 150°C 250 0.8 0.7 0.65 0.6 0.55 0.5 200 25°C 150 −40°C 100 50 0.45 0.4 −50 0 50 TEMPERATURE (°C) 100 150 0 0 10 Figure 19. Forward Voltage (@ −1.3 A) vs. Temperature 20 VD (V) 30 40 Figure 20. STAT Low Voltage vs. VD 5 13 4.5 12.5 3.5 12 3 V(pos) (V) Istat_Leakage (mA) 4 2.5 2 11.5 11 1.5 1 10.5 0.5 0 −50 0 50 TEMPERATURE (°C) 100 150 10 −50 Figure 21. Status Leakage Current vs. Temperature 0 50 100 TEMPERATURE (°C) 150 Figure 22. Status Clamp Voltage (Positive) vs. Temperature www.onsemi.com 9 NCV8460A TYPICAL CHARACTERISTICS CURVES 14 0 12 −1 11 Ilim (A) STATUS CLAMP (neg) (V) 13 −2 10 9 8 −3 7 6 −4 −50 0 50 100 5 −50 150 50 100 TEMPERATURE (°C) Figure 23. Status Clamp Voltage (Negative) vs. Temperature Figure 24. Current Limit vs. Temperature VD = 13.5 V 150 300 48 47.5 −40°C 250 47 25°C 46.5 200 150°C 46 IOL (mA) Vclamp (V) 0 TEMPERATURE (°C) 45.5 45 150 100 44.5 44 50 43.5 43 0 10 20 30 40 0 −50 −30 −10 10 50 30 50 70 90 110 130 150 VD (V) TEMPERATURE (°C) Figure 25. Turn Off Output Clamp Voltage vs. VD and Temperature Figure 26. ON State Open Load Detection vs. Temperature VD = 13.5 V 100 2.9 2.7 −40°C 25°C ILmax (A) Vol (V) 2.5 2.3 2.1 10 25°C 150°C 150°C 1.9 1.7 1 1.5 0 5 10 15 20 25 30 35 40 10 100 VD (V) L (mH) Figure 27. Off State OL Detection Threshold vs. VD and Temperature Figure 28. Single−Pulse Maximum Switch−off Current vs. Load Inductance www.onsemi.com 10 NCV8460A TYPICAL CHARACTERISTICS CURVES 1000 25°C Emax (mJ) 150°C 100 10 10 100 L (mH) Figure 29. Single−Pulse Maximum Switch−off Current vs. Load Inductance ISO 7637−2: 2004(E) PULSE TEST RESULTS ISO 7637−2:2004(E) Test Levels Delays and Test Pulse I II III IV Impedance 1 −25 V −50 V −75 V −100 V 2 ms, 10 W 2a +25 V +50 V +37 V +50 V 0.05 ms, 10 W 3a −25 V −50 V −112 V −150 V 0.1 ms, 50 W 3b +25 V +50 V +75 V +100 V 0.1 ms, 50 W 4 −4 V −5 V −6 V −7 V 5 s, .01 W 5 (Load Dump) +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2 W ISO 7637−2:2004(E) Class Test Results Test Pulse I II III IV 1 C C C C 2a C C C C 3a C C C C 3b C C C C 4 C C C C 5 (Load Dump) C E E E Functional Status A All functions of a device perform as designed during and after exposure to disturbance. B All functions of a device perform as designed during exposure. However,one or more of them can go beyond specified tolerance. All functions return automatically to within normal limits after exposure is removed. Memory functions shall remain class A. C One or more functions of a device do not perform as designed during exposure but return automatically to normal operation after exposure is removed. D One or more functions of a device do not perform as designed during exposure and do not return to normal operation until exposure is removed and the device is reset by simple E One or more functions of a device do not perform as designed during and after exposure and cannot be returned to proper operation without replacing the device. www.onsemi.com 11 NCV8460A Normal Operation Input Load Voltage Status Undervoltage VUV_HYS VD VUV Input Load Voltage Status Undefined Overvoltage VD > VOV VD < VOV VCC Input Load Voltage Status Open Load with External pull−up Input Load Voltage VOL Status Open Load without External pull−up Input Load Voltage Status Overtemperature TJ TR Input Load Voltage Status Figure 30. Waveforms www.onsemi.com 12 TTSD NCV8460A + 5V − VD STAT Vout Input GND Reverse Battery Protection Load DGND RGND Figure 31. Application Diagram Reverse Battery Protection This offset will be increased when more than one device shares the resistor. Power Dissipation during a reverse battery event is equal to: An external resistor RGND is required to adequately protect the device from a Reverse Battery event. The resistor value can be calculated using the following two formulas. 1. RGND ≤ 600 mV / (Id (on) max) 2. RGND ≥ (-VD) / (-Ignd) Maximum (-Ignd) current, which is the reverse GND pin current, can be found in the Maximum Ratings section. Several High Side Devices can share same the reverse battery protection resistor. Please note that the sum of (Id (on) max) of all devices should be used to calculate RGND value. If the microprocessor ground is not common with the device ground, RGND will produce a voltage offset ((Id (on) max) x RGND) with respect to the IN and STAT pins. 2 P D + ǒ* V DǓ ń R GND In the case of high power dissipation due to several devices sharing RGND, it is recommended to place a diode DGND in the ground path as an alternate reverse battery protection method. When driving an inductive load, a 1 kW resistor should be placed in parallel with the DGND diode. This method will also produce a voltage offset of ~600 mV with respect to the IN and STAT pins. This diode can also be shared amongst several High Side Devices. This voltage offset will vary if DGND is shared by multiple devices. www.onsemi.com 13 NCV8460A Vbat 5V V pull −up VD STAT OL R pull −up I V OUT Input GND RL Figure 32. Open Load Detection In Off State OFF State Open Load Detection when the load is connected, the Rpull-up must also not cause the OFF State OL to miss detecting an OL condition when the load is disconnected. A VOUT voltage below the VOL_max (Openload Off State Detection Threshold) maximum value with the load (RL) disconnected needs to be avoided. The following formula shows this relationship: Off State Open Load Detection requires an external pull-up resistor (Rpull-up) connected between VOUT pin and a positive supply voltage (Vpull-up). The external Rpull-up resistor value should be selected to ensure that a false OFF State OL condition is not detected when the load (RL) is connected. A VOUT voltage above the VOL_min (Openload Off State Detection Threshold) minimum value with the load (RL) connected needs to be avoided. The following formula shows this relationship: ǒ R pull*up t ǒV pull*up * V OL_maxǓńOL 1 OL 1 + I LǒOutput Leakage with V OUT + 3.5 VǓ Ǔ V OUT + V pull*upńǒR L ) R pull*upǓ R L t V OL_min Because Id (OFF) may significantly increase if VOUT is pulled high (up to several mA), Rpull-up resistor should be connected to a supply that is switched OFF when the module is in standby. In addition to ensuring the selected Rpull-up resistor value does not cause a false OFF State OL detection condition www.onsemi.com 14 NCV8460A 1000 10 1 Duty Cycle = 0.5 0.2 0.1 0.05 0.02 0.01 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 PULSE TIME (s) 1 Figure 33. Transient Thermal Impedance 180 160 140 qJA (°C/W) R(t), (°C/W) 100 1.0 oz 120 2.0 oz 100 80 60 0 200 400 600 COPPER HEAT SPREADER AREA 800 (mm2) Figure 34. RqJA vs Copper Area www.onsemi.com 15 1000 10 100 100 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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