NCV8503PWADJR2G

NCV8503 Series Micropower 400 mA LDO Linear Regulators with ENABLE, DELAY, Adjustable RESET, and General Use Comparator http://onsemi.com The NCV8503 is a family of precision micropower voltage regulators. Their output current capability is 400 mA. The family has output voltage options for Adjustable, 2.5 V, 3.3 V and 5.0 V. The output voltage is accurate within ± 2.0% with a maximum dropout voltage of 0.6 V at 400 mA. Low quiescent current is a feature drawing less than 1.0 mA with ENABLE = 0 V. With ENABLE = 5.0 V, the part only draws 200 mA with 100 mA load. This part is ideal for any and all battery operated microprocessor equipment. Microprocessor control logic includes an active RESET (with DELAY). The active RESET circuit operates correctly at an output voltage as low as 1.0 V. The RESET function is activated during the power up sequence or during normal operation if the output voltage drops below the regulation limits. The reset threshold voltage can be decreased by the connection of external resistor divider to RADJ lead. The general use comparator (FLAG/Monitor) is referenced to a temperature stable voltage and provides 1.0 mA of drive current at its open collector output. The regulator is protected against reverse battery, short circuit, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments. The device has also been optimized for EMC conditions. Features • • • • • • • • • • • • • • • Output Voltage Options: Adjustable, 2.5 V, 3.3 V, 5.0 V ± 2.0% Output Low < 1.0 mA Sleep Current Low 200 mA Quiescent Current Fixed or Adjustable Output Voltage Active RESET Adjustable Reset ENABLE 400 mA Output Current Capability Fault Protection ♦ +60 V Peak Transient Voltage ♦ −15 V Reverse Voltage ♦ Short Circuit ♦ Thermal Overload General Use Comparator NCV Prefix for Automotive and Other Applications Requiring Site and Change Control AEC Qualified PPAP Capable These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2010 May, 2010 − Rev. 25 1 MARKING DIAGRAM 16 1 SOIC 16 LEAD WIDE BODY EXPOSED PAD PDW SUFFIX CASE 751AG 16 NCV8503x AWLYYWWG 1 x = Voltage Ratings as Indicated Below: A = Adjustable 2 = 2.5 V 3 = 3.3 V 5 = 5.0 V A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Device ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. Publication Order Number: NCV8503/D NCV8503 Series PIN CONNECTIONS ADJUSTABLE OUTPUT 1 VADJ VOUT NC NC NC NC VIN MON IQ SENSE (Fixed Output Only) VIN VOUT SENSE VOUT NC NC NC NC VIN MON 1 16 FLAG RESET ENABLE GND NC NC DELAY RADJ Monitor (VO) VDD 33 mF 10 mF RADJ NCV8503 DELAY RFLG 5.1 k Microprocessor VBAT FIXED OUTPUT 16 FLAG RESET ENABLE GND NC NC DELAY RADJ RRST 5.1 k MON CDELAY ENABLE FLAG VADJ (Adjustable Output Only) RESET I/O GND Figure 1. Application Diagram http://onsemi.com 2 I/O NCV8503 Series MAXIMUM RATINGS*{ Rating VIN (DC) Value Unit −15 to 45 V 60 V Peak Transient Voltage (46 V Load Dump @ VIN = 14 V) Operating Voltage 45 V VOUT (DC) −0.3 to 16 V Voltage Range (RESET, FLAG, RADJ, DELAY) −0.3 to 10 V Input Voltage Range: −0.3 to 10 −0.3 to 16 V V −0.3 to 10** V 4.0 200 kV V Junction Temperature, TJ −40 to +150 °C Storage Temperature, TS −55 to 150 °C 16 57 °C/W °C/W 260 peak (Note 2) °C MON VADJ Input Voltage Range (ENABLE) ESD Susceptibility (Human Body Model) (Machine Model) Package Thermal Resistance, SOW−16 E PAD: Junction−to−Case, RθJC Junction−to−Ambient, RθJA Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) 1. 150 second maximum above 217°C. 2. −5°C/+0°C allowable conditions. *The maximum package power dissipation must be observed. †During the voltage range which exceeds the maximum tested voltage of VIN, operation is assured, but not specified. Wider limits may apply. Thermal dissipation must be observed closely. **Reference Figure 17 for switched−battery ENABLE application. ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, ENABLE = 5.0 V, −40°C ≤ TJ ≤ 150°C; VIN = dependent on voltage option (Note 3); unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Output Stage Output Voltage for 2.5 V Option (VO) 6.5 V < VIN < 16 V, 1.0 mA ≤ IOUT ≤ 400 mA 4.5 V < VIN < 26 V, 1.0 mA ≤ IOUT ≤ 400 mA 2.450 2.425 2.5 2.5 2.550 2.575 V V Output Voltage for 3.3 V Option (VO) 7.3 V < VIN < 16 V, 1.0 mA ≤ IOUT ≤ 400 mA 4.5 V < VIN < 26 V, 1.0 mA ≤ IOUT ≤ 400 mA 3.234 3.201 3.3 3.3 3.366 3.399 V V Output Voltage for 5.0 V Option (VO) 9.0 V < VIN < 16 V, 1.0 mA ≤ IOUT ≤ 400 mA 6.0 V < VIN < 26 V, 1.0 mA ≤ IOUT ≤ 400 mA 4.90 4.85 5.0 5.0 5.10 5.15 V V Output Voltage for Adjustable Option (VO) VOUT = VADJ (Unity Gain) 6.5 V < VIN < 16 V, 1.0 mA < IOUT < 400 mA 4.5 V < VIN < 26 V, 1.0 mA < IOUT < 400 mA 1.274 1.261 1.300 1.300 1.326 1.339 V V Dropout Voltage (VIN − VOUT) (5.0 V and Adj. > 5.0 V Options Only) IOUT = 400 mA IOUT = 1.0 mA − − 400 30 600 150 mV mV Load Regulation VIN = 14 V, 5.0 mA ≤ IOUT ≤ 400 mA −30 5.0 30 mV Line Regulation (2.5 V, 3.3 V, and Adjustable Options) 4.5 V < VIN < 26 V, IOUT = 1.0 mA − 5.0 25 mV Line Regulation (5.0 V Option) 6.0 V < VIN < 26 V, IOUT = 1.0 mA − 5.0 25 mV Quiescent Current, (IQ) Active Mode IOUT = 100 mA, VIN = 12 V, MON = 3.0 V IOUT = 75 mA, VIN = 14 V, MON = 3.0 V IOUT ≤ 400 mA, VIN = 14 V, MON = 3.0 V − − − 200 2.5 25 350 5.0 45 mA mA mA Quiescent Current, (IQ) Sleep Mode ENABLE = 0 V, VIN = 12 V, −40°C ≤ TJ ≤ 125°C Current Limit − − − 1.0 mA 425 800 − mA Short Circuit Output Current VOUT = 0 V 100 500 − mA Thermal Shutdown (Guaranteed by Design) 150 180 − °C 3. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type. http://onsemi.com 3 NCV8503 Series ELECTRICAL CHARACTERISTICS (continued) (IOUT = 1.0 mA, ENABLE = 5.0 V, −40°C ≤ TJ ≤ 150°C; VIN = dependent on voltage option (Note 4); unless otherwise specified.) Test Conditions Characteristic Min Typ Max Unit 2.35 2.30 25 − − − 1.0 × VO − − V V mV 3.10 3.00 35 − − − 1.0 × VO − − V V mV 4.70 4.60 50 − − − 1.0 × VO 4.85 − V V mV 1.22 1.19 10 − − − 1.0 × VO − − V V mV − 0.1 0.4 V Reset Function (RESET) RESET Threshold for 2.5 V Option HIGH (VRH) LOW (VRL) Hysteresis VIN = 4.5 V (Note 5) (Note 6) VOUT Increasing VOUT Decreasing RESET Threshold for 3.3 V Option HIGH (VRH) LOW (VRL) Hysteresis VIN = 4.5 V (Note 5) (Note 6) VOUT Increasing VOUT Decreasing RESET Threshold for 5.0 V Option HIGH (VRH) LOW (VRL) Hysteresis VIN = 6.0 V (Note 6) VOUT Increasing VOUT Decreasing RESET Threshold for Adjustable Option HIGH (VRH) LOW (VRL) Hysteresis VIN = 4.5 V (Note 5) (Note 6) VOUT Increasing VOUT Decreasing RESET Output Voltage Low (VRLO) VIN = Minimum (Note 6) (Note 7) 1.0 V ≤ VOUT ≤ VRL, RRESET = 5.1 k DELAY Switching Threshold (VDT) (2.5 V, 3.3 V, and 5.0 V Options) VIN = Minimum (Note 6) (Note 7) 1.4 1.8 2.2 V DELAY Switching Threshold (VDT) (Adjustable Option) VIN = Minimum (Note 6) (Note 7) 1.0 1.3 1.6 V DELAY Low Voltage VIN = Minimum (Note 6) (Note 7) VOUT < RESET Threshold Low(min) − − 0.2 V DELAY Charge Current VIN = Minimum (Note 6) (Note 7) DELAY = 1.0 V, VOUT > VRH 2.5 4.0 5.5 mA DELAY Discharge Current VIN = Minimum (Note 6) (Note 7) DELAY = 1.0 V, VOUT < VRL 5.0 − − mA Reset Adjust Switching Voltage (VR(ADJ)) Hysteresis VIN = Minimum (Note 6) (Note 7) Increasing and Decreasing 1.16 20 1.25 50 1.34 100 V mV Monitor Threshold VIN = Minimum (Note 6) (Note 7) Increasing and Decreasing 1.20 1.28 1.36 V Hysteresis VIN = Minimum (Note 6) (Note 7) 10 35 75 mV Input Current MON = 2.0 V −0.5 0.1 0.5 mA Output Saturation Voltage MON = 0 V, IFLAG = 1.0 mA, VIN = Minimum (Note 6) (Note 7) − 0.1 0.4 V VADJ = 1.25 V, VIN = Minimum (Note 6) (Note 7) −0.5 − 0.5 mA Input Threshold Low, VIN = 14 V (Note 6) High, VIN = 14 V (Note 6) − 2.0 − − 1.0 − V V Input Current ENABLE = 5.0 V, VIN = 14 V (Note 6) − 30 75 mA FLAG/Monitor Voltage Adjust (Adjustable Output only) Input Current ENABLE 4. 5. 6. 7. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type. For VIN ≤ 4.5 V, a RESET = Low may occur with the output in regulation. Part is guaranteed by design to meet specification over the entire VIN voltage range, but is production tested only at the specified VIN voltage. Minimum VIN = 4.5 V for 2.5 V, 3.3 V, and Adjustable options. Minimum VIN = 6.0 V for 5.0 V option. http://onsemi.com 4 NCV8503 Series PACKAGE PIN DESCRIPTION, ADJUSTABLE OUTPUT Pin Number Pin Symbol 1 VADJ Voltage Adjust. A resistor divider from VOUT to this lead sets the output voltage. 2 VOUT ±2.0%, 400 mA output. 3−6, 11, 12 NC No connection. 7 VIN Input Voltage. 8 MON Monitor. Input to comparator. If not needed connect to VOUT. 9 RADJ Reset adjust. If not needed connect to ground. 10 DELAY 13 GND 14 ENABLE 15 RESET Active reset (accurate to VOUT ≥ 1.0 V) 16 FLAG Open collector output from comparator. NOTE: Function Timing capacitor for RESET function. Ground. All GND leads must be connected to Ground. ENABLE control for the IC. A high powers the device up. Tentative pinout for SOW−16 E Pad. PACKAGE PIN DESCRIPTION, FIXED OUTPUT Pin Number Pin Symbol 1 SENSE 2 VOUT 3−6, 11, 12 NC No connection. 7 VIN Input Voltage. 8 MON Monitor. Input to comparator. If not needed connect to VOUT. 9 RADJ Reset adjust. If not needed connect to ground. 10 DELAY 13 GND 14 ENABLE 15 RESET Active reset (accurate to VOUT ≥ 1.0 V) 16 FLAG Open collector output from comparator. NOTE: Function Kelvin connection which allows remote sensing of output voltage for improved regulation. If remote sensing is not desired, connect to VOUT. ±2.0%, 400 mA output. Timing capacitor for RESET function. Ground. All GND leads must be connected to Ground. ENABLE control for the IC. A high powers the device up. Tentative pinout for SOW−16 E Pad. http://onsemi.com 5 NCV8503 Series VOUT VIN Current Source (Circuit Bias) + − ENABLE SENSE 1.5 V IBIAS RADJ + + − IBIAS 1.8 V (Fixed Versions) 1.3 V (Adjustable Version) VBG − 18 mV RESET Current Limit Sense Error Amplifier VBG + Fixed Versions only − Thermal Protection 4.0 mA DELAY + − IBIAS Bandgap Reference VBG VBG − Figure 2. Block Diagram http://onsemi.com 6 VADJ GND IBIAS + MON 15 k Adjustable Version only FLAG NCV8503 Series TYPICAL PERFORMANCE CHARACTERISTICS 3.35 VOUT = 5.0 V VIN = 14 V IOUT = 5.0 mA Vout, OUTPUT VOLTAGE (V) 5.08 5.06 5.04 5.02 5.00 4.98 4.96 4.94 Vout, OUTPUT VOLTAGE (V) 5.10 VOUT = 3.3 V VIN = 14 V IOUT = 5.0 mA 3.33 3.31 3.29 3.27 3.25 4.92 4.90 −40 −20 0 3.23 −40 −20 20 40 60 80 100 120 140 160 TEMPERATURE (°C) Figure 3. 5 V Output Voltage vs. Temperature 20 40 60 80 100 120 140 160 TEMPERATURE (°C) Figure 4. 3.3 V Output Voltage vs. Temperature 600 VOUT = 2.5 V VIN = 14 V IOUT = 5.0 mA 2.54 2.53 2.52 2.51 2.50 2.49 2.48 2.47 DROPOUT VOLTAGE (mV) 2.55 Vout, OUTPUT VOLTAGE (V) 0 500 125 °C 400 25 °C 300 200 −40 °C 100 2.46 5 V and Adj. > 5 V options only 2.45 −40 −20 0 0 20 40 60 80 100 120 140 160 TEMPERATURE (°C) Figure 5. 2.5 V Output Voltage vs. Temperature 100 150 200 250 300 Iout, OUTPUT CURRENT (mA) 350 400 3.0 4.5 2.5 4.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 50 Figure 6. Dropout Voltage vs. Output Current 5.0 3.5 3.0 2.5 2.0 1.5 125 °C 1.0 25 °C 0.5 0.0 0 4 8 1.5 −40 °C 25 °C 125 °C 1.0 0.5 IOUT = 1 mA −40 °C 0 2.0 12 16 20 0.0 1.4 24 IOUT = 1 mA 1.6 1.8 2.0 2.2 2.4 2.6 2.8 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 7. Output Voltage vs. Input Voltage Figure 8. Output Voltage vs. Input Voltage http://onsemi.com 7 3.0 NCV8503 Series TYPICAL PERFORMANCE CHARACTERISTICS 100 Unstable Region CVOUT = 33 mF* Unstable Region 3.3 V 10 2.5 V 10 ESR (W) ESR (W) 100 5.0 V 1.0 Unstable Region VIN = 14 V CVOUT = 10 mF 0.01 300 100 150 200 250 Iout, OUTPUT CURRENT (mA) 50 0 350 0.1 400 Figure 9. Output Stability with Output Voltage Change +25°C −40°C 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 5 10 40 15 20 25 30 35 IOUT, OUTPUT CURRENT (mA) 45 +125°C +25°C −40°C 30 20 10 6 Iout = 100 mA Iout = 50 mA Iout = 10 mA 0 6 8 10 12 14 16 18 20 VIN, INPUT VOLTAGE (V) 22 24 50 0 100 150 200 250 300 350 400 450 500 IOUT, OUTPUT CURRENT (mA) 210 T = 25°C 8 2 400 Figure 12. Quiescent Current vs. Output Current 10 4 350 40 0 50 IQ, QUIESCENT CURRENT (mA) IQ, QUIESCENT CURRENT (mA) Iout = 200 mA 5 V version 300 100 150 200 250 Iout, OUTPUT CURRENT (mA) 50 50 Figure 11. Quiescent Current vs. Output Current 12 0 60 +125°C 1.6 *There is no unstable lower region for the 33 mF capacitor Figure 10. Output Stability with Output Capacitor Change IQ, QUIESCENT CURRENT (mA) IQ, QUIESCENT CURRENT (mA) 2.0 1.8 CVOUT = 0.1 mF 1.0 Stable Region 0.1 Stable Region 205 200 190 185 180 175 26 Iout = 100 mA 195 T = 25°C 8 6 10 12 14 16 18 20 VIN, INPUT VOLTAGE (V) 22 24 26 Figure 14. Quiescent Current vs. Input Voltage Figure 13. Quiescent Current vs. Input Voltage http://onsemi.com 8 NCV8503 Series CIRCUIT DESCRIPTION REGULATOR CONTROL FUNCTIONS The NCV8503 contains the microprocessor compatible control function RESET (Figure 15). ENABLE Function The part stays in a low IQ sleep mode when the ENABLE pin is held low. The part has an internal pull down if the pin is left floating. The integrity of the ENABLE pin allows it to be tied to the battery line through an external resistor. It will withstand load dump potentials in this configuration. VIN RESET Threshold VOUT VBAT Up to 45 V DELAY Threshold (VDT) DELAY RESET VOUT VIN NCV8503 10 k ENABLE GND Td Td Figure 15. Reset and Delay Circuit Wave Forms Figure 17. ENABLE Function RESET Function A RESET signal (low voltage) is generated as the IC powers up until VOUT is within 1.5% of the regulated output voltage, or when VOUT drops out of regulation,and is lower than 4.0% below the regulated output voltage. Hysteresis is included in the function to minimize oscillations. The RESET output is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC thereby guaranteeing that the RESET signal is valid for VOUT as low as 1.0 V. DELAY Function The reset delay circuit provides a programmable (by external capacitor) delay on the RESET output lead. The DELAY lead provides source current (typically 4.0 mA) to the external DELAY capacitor during the following proceedings: 1. During Power Up (once the regulation threshold has been verified). 2. After a reset event has occurred and the device is back in regulation. The DELAY capacitor is discharged when the regulation (RESET threshold) has been violated. This is a latched incident. The capacitor will fully discharge and wait for the device to regulate before going through the delay time event again. Adjustable Reset Function The reset threshold can be made lower by connecting an external resistor divider to the RADJ lead from the VOUT lead, as displayed in Figure 16. This lead is grounded to select the default value of 4.6 V (on the 5.0 V option). VR(ADJ) VOUT RADJ NCV8503 DELAY FLAG/Monitor Comparator to mP and System Power RRST RESET A general use comparator is included whose positive input terminal is tied to the on−chip band gap voltage reference. This provides a very temperature stable referenced comparator with versatile uses in any system. The trip point can be programmed externally using a resistor divider to the input monitor (MON) (Figure 18). The typical threshold is 1.28 V on the MON pin. COUT to mP and RESET Port VMON CDELAY VBAT VOUT VIN NCV8503 Figure 16. Adjustable RESET MON FLAG RADJ RESET DELAY GND VCC Figure 18. Flag/Monitor Function http://onsemi.com 9 mP COUT I/O RESET NCV8503 Series Voltage Adjust ≈5.0 V VOUT Figure 19 shows the device setup for a user configurable output voltage. The feedback to the VADJ pin is taken from a voltage divider referenced to the output voltage. The loop is balanced around the Unity Gain threshold (1.30 V typical). JEDEC standard JESD78 requires −100 mA trigger test conditions. VADJ conforms to −75 mA test conditions. COUT 15 k NCV8503 VADJ 1.28 V 5.1 k Figure 19. Adjustable Output Voltage APPLICATION NOTES FLAG MONITOR Figure 20 shows the FLAG Monitor waveforms as a result of the circuit depicted in Figure 18. As the input voltage falls (VMON), the Monitor threshold is crossed. This causes the voltage on the FLAG output to go low. STABILITY CONSIDERATIONS The output or compensation capacitor helps determine three main characteristics of a linear regulator: start−up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 21 should work for most applications, however it is not necessarily the optimized solution. VMON MON Flag Monitor Ref. Voltage FLAG VIN Figure 20. FLAG Monitor Circuit Waveform Delay Charge Current 4.2 mA COUT** 33 mF Figure 21. Test and Application Circuit Showing Output Compensation Example: Using CDELAY = 33 nF. Assume reset Delay Low Voltage = 0. Use the typical value for Vdt = 1.8 V (2.5 V, 3.3 V, and 5.0 V options). Use the typical value for Delay Charge Current = 4.2 mA. ƪ33 nF(1.8 * 0)ƫ RRST *CIN required if regulator is located far from the power supply filter **COUT required for stability. Capacitor must operate at minimum temperature expected ƪCDELAY(Vdt * Reset Delay Low Voltage)ƫ tDELAY + NCV8503 RESET SETTING THE DELAY TIME The delay time is controlled by the Reset Delay Low Voltage, Delay Switching Threshold, and the Delay Charge Current. The delay follows the equation: tDELAY + VOUT CIN* 0.1 mF + 14 ms http://onsemi.com 10 NCV8503 Series Thermal Resistance, Junction to Ambient, RqJA, (°C/W) 100 The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. 90 80 70 60 VIN 50 40 IOUT IIN 0 200 400 600 Copper Area (mm2) IQ Figure 23. Single Output Regulator with Key Performance Parameters Labeled HEAT SINKS A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA: CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR The maximum power dissipation for a single output regulator (Figure 23) is: (1) ) VIN(max)IQ where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: o T RqJA + 150 C * A PD VOUT } Control Features 800 Figure 22. 16 Lead SOW (Exposed Pad), qJA as a Function of the Pad Copper Area (2 oz. Cu Thickness), Board Material = 0.0625, G−10/R−4 PD(max) + [VIN(max) * VOUT(min)] IOUT(max) SMART REGULATOR® RqJA + RqJC ) RqCS ) RqSA (3) where: RqJC = the junction−to−case thermal resistance, RqCS = the case−to−heatsink thermal resistance, and RqSA = the heatsink−to−ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. (2) http://onsemi.com 11 NCV8503 Series ORDERING INFORMATION Device Output Voltage NCV8503PWADJG NCV8503PWADJR2G Adjustable NCV8503PW25G NCV8503PW25R2G 2.5 V NCV8503PW33G NCV8503PW33R2G 3.3 V NCV8503PW50G NCV8503PW50R2G 5.0 V Package Shipping† SOW−16 Exposed Pad (Pb−Free) 47 Units/Rail SOW−16 Exposed Pad (Pb−Free) 1000 Tape & Reel SOW−16 Exposed Pad (Pb−Free) 47 Units/Rail SOW−16 Exposed Pad (Pb−Free) 1000 Tape & Reel SOW−16 Exposed Pad (Pb−Free) 47 Units/Rail SOW−16 Exposed Pad (Pb−Free) 1000 Tape & Reel SOW−16 Exposed Pad (Pb−Free) 47 Units/Rail SOW−16 Exposed Pad (Pb−Free) 1000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLIC). http://onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC 16 LEAD WIDE BODY, EXPOSED PAD CASE 751AG ISSUE B SCALE 1:1 −U− A 0.25 (0.010) M W 9 B 1 M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751R-01 OBSOLETE, NEW STANDARD 751R-02. M 16 P R x 45_ 8 −W− G 14 TOP VIEW PIN 1 I.D. PL DETAIL E C F −T− 0.10 (0.004) T K D 16 PL 0.25 (0.010) T U M SEATING PLANE W S S J SIDE VIEW DETAIL E 1 DIM A B C D F G H J K L M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 3.45 3.66 0.25 0.32 0.00 0.10 4.72 4.93 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.136 0.144 0.010 0.012 0.000 0.004 0.186 0.194 0_ 7_ 0.395 0.415 0.010 0.029 GENERIC MARKING DIAGRAM* H EXPOSED PAD DATE 31 MAY 2016 8 XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX AWLYYWWG L 16 9 BOTTOM VIEW XXXXX A WL YY WW G SOLDERING FOOTPRINT* 0.350 Exposed Pad 0.175 0.050 CL 0.200 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 0.188 CL = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package 0.376 0.074 0.150 0.024 DIMENSIONS: INCHES *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON21237D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. SOIC−16, WB EXPOSED PAD PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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