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NCV86604BD33R2G

NCV86604BD33R2G

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    SOIC8_150MIL

  • 描述:

    IC REG LINEAR 3.3V 150MA 8SOIC

  • 数据手册
  • 价格&库存
NCV86604BD33R2G 数据手册
NCV8660B Very Low Iq LD0 150 mA Regulator with RESET and Delay Time Select The NCV8660B is a precision very low Iq low dropout voltage regulator. Quiescent currents as low as 28 mA typical make it ideal for automotive applications requiring low quiescent current with or without a load. Integrated control features such as Reset and Delay Time Select make it ideal for powering microprocessors. It is available with a fixed output voltage of 5.0 V and 3.3 V and regulates within ±2.0%. Features http://onsemi.com MARKING DIAGRAMS 8 8 1 SOIC−8 FUSED CASE 751 1 x y 660yBx ALYWW G • • • • • • • • • • Fixed Output Voltage of 5 V and 3.3 V ±2.0% Output Voltage up to VBAT = 40 V Output Current up to 150 mA Microprocessor Compatible Control Functions: ♦ Delay Time Select ♦ RESET Output NCV Prefix for Automotive ♦ Site and Change Control ♦ AEC−Q100 Qualified Low Dropout Voltage Low Quiescent Current of 28 mA Typical Stable Under No Load Conditions Protection Features: ♦ Thermal Shutdown ♦ Short Circuit These are Pb−Free Devices A L Y WW G = 5 for 5 V Output, 3 for 3.3 V Output = 1 for 8 ms, 128 ms Reset Delay, = 2 for 8 ms, 32 ms Reset Delay = 3 for 16 ms, 64 ms Reset Delay = 4 for 32 ms, 128 ms Reset Delay = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the dimensions section on page 11 of this data sheet. Applications ♦ ♦ • Automotive: • Body Control Module Instrument and Clusters ♦ Occupant Protection and Comfort ♦ Powertrain Battery Powered Consumer Electronics IN NCV8660B OUT COUT 2.2 mF OUT VBAT 13.2 V CIN 0.1 mF DT DT RO GND RO Figure 1. Application Diagram © Semiconductor Components Industries, LLC, 2010 May, 2010 − Rev. 2 1 Publication Order Number: NCV8660B/D NCV8660B PIN DESCRIPTIONS Pin 1 2 5−8 3 4 Symbol IN RO GND DT OUT Function Input Supply Voltage. 0.1 mF bypass capacitor to GND at the IC. Reset Output. CMOS compatible output. Goes low when VOUT drops by more than 7% from nominal. Ground Reset Delay Time Select. Short to GND or connect to OUT to select time. Regulated Voltage Output. 2.2 mF to ground for typical applications. IN OUT Current Limit and Thermal Shutdown + − Vref1 GND DT − + Timing Circuit RO Vref2 Figure 2. Block Diagram http://onsemi.com 2 NCV8660B ABSOLUTE MAXIMUM RATINGS Rating Input Voltage (IN) Input Current Output Voltage (OUT) DC Transient, t < 10 s (Note 1) Output Current (OUT) Storage Temperature Range DT (Reset Delay Time Select) Voltage (Note 2) DT (Reset Delay Time Select) Current (Note 2) RO (Reset Output) Voltage DC Transient, t < 10 s RO (Reset Output) Current ESD CAPABILITY ESD Capability, Human Body Model (Note 3) ESD Capability, Machine Model (Note 3) ESD Capability, Charged Device Model (Note 3) THERMAL RESISTANCE Junction−to−Ambient (Note 4) Junction−to−Lead (pin 6) (Note 4) LEAD SOLDERING TEMPERATURE AND MSL Moisture Sensitivity Level Lead Temperature Soldering: SMD style only, Reflow (Note 5) Pb−Free Part 60 − 150 sec above 217°C, 40 sec max at peak MSL SLD − 3 265 peak − °C RqJA RqJT 104 33 °C/W °C/W ESDHB ESDMM ESDCDM −2.0 −200 −1.0 2.0 200 1.0 kV V kV Symbol VIN IIN VOUT Min −0.3 −1.0 −0.3 −0.3 −1.0 −55 −0.3 −1.0 −0.3 −0.3 −1.0 Max 40 − 5.5 16 Current Limited 150 16 1.0 5.5 16 1.0 Unit V mA V IOUT TSTG VDT IDT VRO mA °C V mA V IRO mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The output voltage must not exceed the input voltage. 2. External resistor required to minimize current to less than 1 mA when the control voltage is above 16 V. 3. This device series incorporates ESD protection and is tested by the following methods: ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A114) ESD MM tested per AEC−Q100−003 (EIA/JESD22−A115) ESD CDM tested per EIA/JESD22/C101, Field Induced Charge Model 4. Values represented typical steady−state thermal performance on 1 oz. copper FR4 PCB with 1 in2 copper area. 5. Per IPC / JEDEC J−STD−020C. OPERATING RANGE Pin Symbol, Parameter VIN, Input Voltage Operating Range Junction Temperature Range Symbol VIN TJ Min 4.5 −40 Max 40 150 Unit V °C http://onsemi.com 3 NCV8660B ELECTRICAL CHARACTERISTICS 5.5 V < VIN < 40 V, −40°C ≤ TJ ≤ +150°C, unless otherwise specified Characteristic GENERAL Quiescent Current Thermal Shutdown (Note 6) Thermal Hysteresis (Note 6) OUT Output Voltage VOUT 6 V ≤ VIN ≤ 16 V, 0.1 mA ≤ IOUT ≤ 150 mA 6 V ≤ VIN ≤ 40 V, 0.1 mA ≤ IOUT ≤ 100 mA 5.6 V ≤ VIN ≤ 16 V, 0 mA ≤ IOUT ≤ 150 mA, −40°C ≤ TJ ≤ +125°C Output Voltage VOUT 5.5 V ≤ VIN ≤ 16 V, 0.1 mA ≤ IOUT ≤ 150 mA 5.5 V ≤ VIN ≤ 40 V, 0.1 mA ≤ IOUT ≤ 100 mA Output Current Limit Output Current Limit, Short Circuit Load Regulation Line Regulation Dropout Voltage − 5.0 V Only ICL ISCKT DVOUT DVOUT VDR OUT = 96% x VOUT nominal OUT = 0 V VIN = 13.2 V, IOUT = 0.1 mA to 150 mA IOUT = 5 mA, VIN = 6 V to 28 V IOUT = 100 mA, (Note 7) VDR = VIN – VOUT, (DVOUT = −100 mV) IOUT = 150 mA, (Note 7) VDR = VIN – VOUT, (DVOUT = −100 mV) Output Load Capacitance Power Supply Ripple Rejection DT (Reset Delay Time Select) Threshold Voltage Input Current RO, Reset Output RESET Threshold RESET Threshold Hysteresis RO Output Low RO Output High (OUT−RO) Reset Reaction Time Input Voltage Reset Threshold RESET Delay with DT Selection Delay Time Out of RESET − 8 ms version − 16 ms version − 32 ms version − 64 ms version − 128 ms version tdRx VOUT into regulation to RO High 5.0 10 20 40 80 8.0 16 32 64 128 11.5 23 46 92 184 msec VRf VRhys VRL VRH tRR VIN_RT 10 kW RESET to OUT, VOUT = 4.5 V 10 kW RESET to GND VOUT into UV to RESET Low VIN Decreasing, VOUT > VRT VOUT decreasing 90 − − VOUT −0.4 16 − 93 2.0 0.2 VOUT −0.2 25 3.8 96 − 0.4 VOUT 38 4.25 %VOUT %VOUT V V msec V High Low DT = 5 V 2 − − − − − − 0.8 1.0 V V mA CO PSRR Output capacitance for stability VIN = 13.2 V, 0.5 VPP, 100 Hz 4.9 4.9 4.9 3.234 3.234 205 205 −40 −20 − − 2.2 − 5.0 5.0 5.0 3.3 3.3 − − 10 0 0.225 0.30 − 60 5.1 5.1 5.1 3.366 3.366 525 525 40 20 0.45 0.60 − − mF dB mA mA mV mV V V V Iq TSD THYS 100mA < IOUT < 150mA, VIN = 13.2V, TJ = 25°C 100mA < IOUT < 150mA, VIN = 13.2V, TJ ≤ 85°C − − 150 − 25 − 175 25 30 40 195 − °C °C mA Symbol Conditions Min Typ Max Unit 6. Not production tested, guaranteed by design. 7. Dropout at a given current level is defined as the voltage difference of VIN to VOUT with VIN decreasing until the output drops by 100 mV. http://onsemi.com 4 NCV8660B TYPICAL OPERATING CHARACTERISTICS 5.0 4.995 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 60 80 100 120 140 160 4.99 4.985 4.98 4.975 4.97 4.965 Iout = 0 mA, 150 mA 4.96 0 20 40 −40 −20 3.315 3.310 3.305 3.300 3.295 3.290 3.285 3.280 3.275 3.270 3.265 Iout = 0 mA, 150 mA 3.260 0 20 40 −40 −20 60 80 100 120 140 160 TEMPERATURE (°C) TEMPERATURE (°C) Figure 3. Output Voltage vs. Temperature (OUT = 5 V) 5.0 4.995 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 4.99 4.985 4.98 4.975 4.97 4.965 4.96 4.955 0 20 40 60 150°C 80 100 120 140 160 −40°C 25°C 3.310 3.305 3.300 3.295 3.290 3.285 3.280 3.275 3.270 3.265 3.260 3.255 Figure 4. Output Voltage vs. Temperature (OUT = 3.3 V) 25°C −40°C 150°C 0 20 40 60 80 100 120 140 160 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) Figure 5. Output Voltage vs. Output Current (OUT = 5 V) 6 5 4 3 2 25°C 1 0 150°C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 −40°C 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 Figure 6. Output Voltage vs. Output Current (OUT = 3.3 V) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 150°C 25°C −40°C 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 7. Output Voltage vs. Input Voltage (RLOAD = 51 k, Iout = 100 mA, OUT = 5 V) Figure 8. Output Voltage vs. Input Voltage (RLOAD = 51 k, Iout = 100 mA, OUT = 3.3 V) http://onsemi.com 5 NCV8660B TYPICAL OPERATING CHARACTERISTICS 380 370 360 350 340 330 320 310 −40 −20 Vin = 13.2 V 0 20 40 60 80 100 120 140 160 TEMPERATURE (°C) DROPOUT VOLTAGE (mV) CURRENT LIMIT (mA) 600 500 400 300 200 100 0 150°C 25°C −40°C 0 25 50 75 100 125 150 OUTPUT CURRENT (mA) Figure 9. Current Limit vs. Temperature Figure 10. Dropout Voltage vs. Output Current 600 500 1 mA 400 300 200 100 0 −40 −20 150 mA 125 mA 100 mA 75 mA 50 mA 25 mA 10 mA 0 20 40 60 80 100 120 140 160 QUIESCENT CURRENT (mA) 40 35 30 25 20 15 10 5 0 0 2 4 6 8 10 Iout = 0 mA 12 14 16 DROPOUT VOLTAGE (mV) TEMPERATURE (°C) INPUT VOLTAGE (V) Figure 11. Dropout Voltage vs. Temperature Figure 12. Quiescent Current vs. Input Voltage 29 28.5 QUIESCENT CURRENT (mA) 28 27 26 25 24 0 20 40 60 80 100 120 140 160 QUIESCENT CURRENT (mA) 27.5 26.5 25.5 24.5 23.5 −40 −20 35 30 25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 150°C 25°C −40°C TEMPERATURE (°C) OUTPUT CURRENT (mA) Figure 13. Quiescent Current vs. Temperature Figure 14. Quiescent Current vs. Output Current http://onsemi.com 6 NCV8660B TYPICAL OPERATING CHARACTERISTICS Figure 15. Load Transient (VIN = 13.2 V, OUT = 5 V) Figure 17. Load Transient (VIN = 13.2 V, OUT = 3.3 V) IN OUT Cout = 2.2 mF Iout = 150 mA Figure 16. Line Transient (OUT = 5 V) Figure 18. Line Transient (OUT = 3.3 V) http://onsemi.com 7 NCV8660B TYPICAL OPERATING CHARACTERISTICS 80 70 60 MAG (dB) 50 40 30 20 10 0 10 VIN = 13.2 V COUT = 4.7 mF IOUT = 100 mA 100 1k 10 k FREQUENCY 100 k 1M 10 M MAG (dB) 80 70 60 50 40 30 20 10 0 10 VIN = 13.2 V COUT = 4.7 mF IOUT = 150 mA 100 1k 10 k 100 k 1M 10 M FREQUENCY Figure 19. Ripple Rejection vs. Frequency (VIN = 13.2 V, IOUT = 100 mA) 10000 1000 100 ESR (W) 10 1 0.1 0.01 Vin = 13.2 V CLOAD = 2.2 mF 0 20 40 60 80 100 120 140 160 10000 1000 100 ESR (W) Stable Region 10 1 0.1 0.01 Figure 20. Ripple Rejection vs. Frequency (VIN = 13.2 V, IOUT = 150 mA) Unstable Region 25°C −40°C 125°C 25°C −40°C Unstable Region 125°C Stable Region Vin = 13.2 V CLOAD = 2.2 mF 0 20 40 60 80 100 120 140 160 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) Figure 21. Output Capacitor ESR vs. Output Current (OUT = 5 V) 5.5 5.0 4.5 OUTPUT VOLTAGE (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 25 50 75 100 Figure 22. Output Capacitor ESR vs. Output Current (OUT = 3.3 V) Temperature Increasing Temperature Decreasing 125 150 175 TEMPERATURE (°C) Figure 23. Thermal Shutdown vs. Temperature http://onsemi.com 8 NCV8660B DETAILED OPERATING DESCRIPTION General Current Limit The NCV8660B is a 5 V and 3.3 V linear regulator providing low drop−out voltage for 150 mA at low quiescent current levels. Also featured in this part is a reset output with selectable delay times. Delay times are selectable via part selection and control through the Delay Time Select (DT) pin. No pull−up resistor is needed on the reset output (RO). Pull−up and pull−down capability are included. Only a small bypass capacitor on the input (IN) supply pin and output (OUT) voltage pin are required for normal operation. Thermal shutdown functionality protects the IC from damage caused from excessively high temperatures appearing on the IC. Output Voltage Current limit is provided on OUT to protect the IC. The minimum specification is 205 mA. Current limit is specified under two conditions (OUT = 96% x OUT nominal) and (OUT = 0 V). No fold−back circuitry exists. Any measured differences can be attributed to change in die temperature. The part may be operated up to 205 mA provided thermal die temperature is considered and is kept below 150°C. Degradation of electrical parameters at this current is expected at these elevated levels. A reset (RO) will not occur with a load less than 205 mA. Reset Output Output stability is determined by the capacitor selected from OUT to GND. The NCV8660B has been designed to work with low ESR (equivalent series resistance) ceramic capacitors. The device is extremely stable using virtually any capacitor 2.2 mF and above. Reference the Output Capacitor Stability graph in Figure 21. The output capacitor value will affect overshoot during power−up. A lower value capacitor will cause higher overshoot on the output. System evaluation should be performed with minimum loading for evaluation of overshoot. Selection of process technology for the NCV8660B allows for low quiescent current independent of loading. Quiescent current will remain flat across the entire range of loads providing a low quiescent current condition in standby and under heavy loads. This is highly beneficial to systems requiring microprocessor interrupts during standby mode as duty cycle and load changes have no impact on the standby current. Reference Figure 14 for Quiescent Current vs Output Current. A reset signal is provided on the Reset Output (RO) pin to provide feedback to the microprocessor of an out of regulation condition. This is in the form of a logic signal on RO. Output (OUT) voltage conditions below the RESET threshold cause RO to go low. The RO integrity is maintained down to OUT = 1.0 V. The Reset Output (RO) circuitry includes an active internal pullup to the output (OUT) as shown in Figure 24. No external pullup is neccessary. OUT RO Reset Control Signal Figure 24. Reset Output Circuitry http://onsemi.com 9 NCV8660B IN t OUT Reset Delay Time t < Reset Reaction Time OUT Reset Threshold plus Hysteresis OUT Reset Threshold t RO t Reset Threshold Plus Hysteresis Thermal Shutdown Voltage Dip at Input Reset Delay Time Secondary Spike Overload at Output Reset Delay Time Reset Reaction Time Thermal Shutdown minus Thermal Hysteresis Figure 25. Reset Timing During power−up (or restoring OUT voltage from a reset event), the OUT voltage must be maintained above the Reset threshold for the Reset Delay time before RO goes high. The time for Reset Delay is determined by the choice of IC and the state of the DT pin. Reset Delay Time Select The Delay Time select (DT) pin is logic level controlled and provides Reset Delay time per the chart. Note the DT pin is sampled only when RO is low, and changes to the DT pin when RO is high will not effect the reset delay time. Thermal Shutdown Selection of the NCV8660B device and the state of the DT pin determines the available Reset Delay times. The part is designed for use with DT tied to ground or OUT, but may be controlled by any logic signal which provides a threshold between 0.8 V and 2 V. The default condition for an open DT pin is the slower Reset time (DT = GND condition). Times are in pairs and are highlighted in the chart below. Consult factory for availability. DT=GND Reset Time NCV86601B NCV86602B NCV86603B NCV86604B 8 ms 8 ms 16 ms 32 ms DT=OUT Reset Time 128 ms 32 ms 64 ms 128 ms When the die temperature exceeds the Thermal Shutdown threshold, a Thermal Shutdown event is detected OUT is turned off, and RO goes low. The IC will remain in this state until the die temperature moves below the shutdown threshold (175°C typical) minus the hysteresis factor (25°C typical). The output will then turn back on and RO will go high after the RESET Delay time. http://onsemi.com 10 NCV8660B 180 170 160 ThetaJA (°C/W) 150 140 130 110 90 80 120 100 Theta JA curve Power curve with PCB 1 oz cu MAX POWER (W) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 700 0 100 200 300 400 500 600 COPPER HEAT SPREADER AREA (mm2) Figure 26. RqJA vs. PCB Copper Area 100 0.5 0.2 10 0.1 0.05 0.02 1 0.1 0.01 0.001 0.000001 Psi L−A 0.00001 0.0001 0.001 0.01 0.1 PULSE TIME (sec) 1 10 100 1000 0.01 Single Pulse R(t), (°C/W) Figure 27. Transient Thermal Response Cu Area = 645 mm2 ORDERING INFORMATION Device NCV86601BD50R2G NCV86602BD50R2G NCV86603BD50R2G NCV86604BD50R2G NCV86601BD33R2G NCV86602BD33R2G NCV86603BD33R2G NCV86604BD33R2G 3.3 V 5.0 V Output Voltage Reset Delay Time, DT to GND 8 ms 8 ms 16 ms 32 ms 8 ms 8 ms 16 ms 32 ms Reset Delay Time, DT to OUT 128 ms 32 ms 64 ms 128 ms 128 ms 32 ms 64 ms 128 ms SOIC−8 FUSED (Pb−Free) 2500 / Tape & Reel Package Shipping† †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. http://onsemi.com 11 NCV8660B PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AJ A 8 5 −X− B 1 S 4 0.25 (0.010) M Y M −Y− G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 12 NCV8660B/D
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