NCV8664CST33T3G

NCV8664C Linear Regulator, Low Dropout, Very Low Iq The NCV8664C is a precision 3.3 V and 5.0 V fixed output, low dropout integrated voltage regulator with an output current capability of 150 mA. Careful management of light load current consumption, combined with a low leakage process, achieve a typical quiescent current of 22 mA. NCV8664C is pin and functionally compatible with NCV4264−2C and could replace this part when lower quiescent current is required. The output voltage is accurate within ±2.0%, and maximum dropout voltage is 600 mV at full rated load current. It is internally protected against input supply reversal, output overcurrent faults, and excess die temperature. No external components are required to enable these features. www.onsemi.com MARKING DIAGRAMS TAB 1 2 3 1 Features • • • • • • • • • 3.3 V, 5.0 V Fixed Output ±2.0 % Output Accuracy, Over Full Temperature Range 22 mA Typical Quiescent Current 600 mV Maximum Dropout Voltage at 150 mA Load Current Wide Input Voltage Operating Range of 4.5 V to 45 V Internal Fault Protection ♦ −42 V Reverse Voltage ♦ Short Circuit/Overcurrent ♦ Thermal Overload NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable EMC Compliant These are Pb−Free Devices 4 1 2 AYW 664CxG G SOT−223 ST SUFFIX CASE 318E 3 DPAK DT SUFFIX CASE 369C 664CxxG ALYWW 1 xx x A L Y WW G or G = Voltage Rating DPAK (50 = 5.0 V Version) (33 = 3.3 V Version) = Voltage Rating SOT223 (5 = 5.0 V Version) (3 = 3.3 V Version) = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS (SOT−223/DPAK) PIN FUNCTION 1 VIN 2,4,TAB GND 3 VOUT ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. © Semiconductor Components Industries, LLC, 2015 November, 2018 − Rev. 3 1 Publication Order Number: NCV8664C/D NCV8664C VIN VOUT Bias Current Generators 1.3 V Reference + Error Amp - Thermal Shutdown GND Figure 1. Block Diagram PIN FUNCTION DESCRIPTION Pin No. DPAK/SOT−223 Symbol 1 VIN 2 GND Ground; Must be connected to GND potential. 3 VOUT Regulated output voltage. 4, TAB GND Ground; substrate and best thermal connection to the die. Function Unregulated input voltage; 4.5 V to 45 V. OPERATING RANGE Pin Symbol, Parameter Symbol Min Max Unit VIN, DC Input Operating Voltage VIN 4.5 +45 V Junction Temperature Operating Range TJ −40 +150 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. MAXIMUM RATINGS Rating Symbol Min Max Unit VIN −42 +45 V VOUT −0.3 +32 V Tstg −55 +150 °C ESD Capability, Human Body Model (Note 1) VESDHBM 4 − kV ESD Capability, Machine Model (Note 1) VESDMIM 200 − V VIN, DC Voltage VOUT, DC Voltage Storage Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device series incorporates ESD protection and is tested by the following methods: ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A 114C) ESD MM tested per AEC−Q100−003 (EIA/JESD22−A 115C) www.onsemi.com 2 NCV8664C THERMAL RESISTANCE Parameter Symbol Condition Min Max Unit Junction−to−Ambient DPAK SOT−223 RqJA − − 87.4 (Note 2) 109 (Note 2) °C/W Junction−to−Tab DPAK SOT−223 RyJT − − 3.5 10.9 °C/W 2. 1 oz copper, 100 mm2 copper area, FR4. LEAD SOLDERING TEMPERATURE AND MSL Rating Symbol Lead Temperature Soldering Reflow (SMD Styles Only), Lead Free (Note 3) Min Max − 265 pk 3 1 − − Unit Tsld Moisture Sensitivity Level SOT223 DPAK MSL °C − 3. Lead Free, 60 sec – 150 sec above 217°C, 40 sec max at peak. ELECTRICAL CHARACTERISTICS (VIN = 13.5 V, Tj = −40°C to +150°C, unless otherwise noted.) Characteristic Symbol Test Conditions Min Typ Max Unit Output Voltage 5.0 V Version VOUT 0.1 mA  IOUT  150 mA (Note 4) 6.0 V  VIN  28 V 4.900 5.0 5.100 V Output Voltage 5.0 V Version VOUT 0 mA  IOUT  150 mA 5.5 V  VIN  28 V −40°C  TJ  125°C 4.900 5.0 5.100 V Output Voltage 3.3 V Version VOUT 0.1 mA  IOUT  150 mA (Note 4) 4.5 V  VIN  28 V 3.234 3.3 3.366 V Line Regulation 5.0 V Version DVOUT vs. VIN IOUT = 5.0 mA 6.0 V  VIN  28 V −25 0.7 +25 mV Line Regulation 3.3 V Version DVOUT vs. VIN IOUT = 5.0 mA 4.5 V  VIN  28 V −25 0.6 +25 mV Load Regulation DVOUT vs. IOUT 1.0 mA  IOUT  150 mA (Note 4) −35 0.5 +35 mV Dropout Voltage 5.0 V Version VIN−VOUT IQ = 100 mA (Notes 4 & 5) IQ = 150 mA (Notes 4 & 5) − − 230 270 500 600 mV Iq IOUT = 100 mA TJ = 25°C TJ = −40°C to +85°C − − 21 22 29 30 Active Ground Current IG(ON) IOUT = 50 mA (Note 4) IOUT = 150 mA (Note 4) − − 0.5 3.1 3 15 mA Power Supply Rejection PSRR VRIPPLE = 0.5 VP−P, F = 100 Hz − 67 − dB Current Limit IOUT(LIM) VOUT = 4.5 V (5.0 V Version) (Note 4) VOUT = 3.0 V (3.3 V Version) (Note 4) 150 150 − − 500 500 mA Short Circuit Current Limit IOUT(SC) VOUT = 0 V (Note 4) 100 − 500 mA TTSD (Note 6) 150 − 200 °C Quiescent Current mA PROTECTION Thermal Shutdown Threshold Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Use pulse loading to limit power dissipation. 5. Dropout voltage = (VIN – VOUT), measured when the output voltage has dropped 100 mV relative to the nominal value obtained with VIN = 13.5 V. 6. Not tested in production. Limits are guaranteed by design. www.onsemi.com 3 NCV8664C 4.5−45 V Input II CIN 1.0 mF Vin 1 100 nF 8664C 3 IQ Vout Output COUT 10 mF, 5.0 V Version 22 mF, 3.3 V Version 2 GND Figure 2. Measurement Circuit 4.5−45 V Input Vin CIN 100 nF 1 8664C 3 Vout 2 Output COUT 10 mF, 5.0 V Version 22 mF, 3.3 V Version GND Figure 3. Applications Circuit www.onsemi.com 4 RL NCV8664C Typical Characteristic Curves − 5 V Version 100 5.10 VQ, OUTPUT VOLTAGE (V) Unstable Region ESR (W) 10 1 Stable Region 0.1 CQ = 10 mF 0.01 0 25 50 75 100 125 40 80 160 120 Figure 4. Output Stability with Output Capacitor ESR Figure 5. Output Voltage vs. Junction Temperature 450 VDR, DROPOUT VOLTAGE (mV) VQ, OUTPUT VOLTAGE (V) 0 TJ, JUNCTION TEMPERATURE (°C) 4 3 2 RL = 33 W TJ = 25°C 1 0 1 2 3 5 4 6 7 8 9 400 350 TJ = 125°C 300 250 200 TJ = 25°C 150 100 50 0 10 0 25 50 75 100 125 150 VI, INPUT VOLTAGE (V) IQ, OUTPUT CURRENT (mA) Figure 6. Output Voltage vs. Input Voltage Figure 7. Dropout Voltage vs. Output Current 3.0 Iq, QUIESCENT CURRENT (mA) 350 IQ, OUTPUT CURRENT (mA) VI = 13.5 V RL = 1 kW 4.95 IQ, OUTPUT CURRENT (mA) 5 300 250 200 150 VQ = 0 V TJ = 25°C 100 50 0 5.00 4.90 −40 150 6 0 5.05 0 5 10 15 20 25 30 35 40 TJ = 25°C 2.5 2.0 1.5 1.0 RL = 100 W 0.5 0 45 RL = 50 W 0 5 10 15 20 25 30 35 40 VI, INPUT VOLTAGE (V) VI, INPUT VOLTAGE (V) Figure 8. Maximum Output Current vs. Input Voltage Figure 9. Quiescent Current vs. Input Voltage www.onsemi.com 5 45 NCV8664C Typical Characteristic Curves − 5 V Version 0.25 Iq, QUIESCENT CURRENT (mA) VI = 13.5 V TJ = 25°C 3.0 2.5 2.0 1.5 1.0 0.5 0 0 25 50 100 75 125 VI = 13.5 V TJ = 25°C 0.20 0.15 0.10 0.05 0 150 0 2 4 6 8 10 12 14 16 18 IQ, OUTPUT CURRENT (mA) IQ, OUTPUT CURRENT (mA) Figure 10. Quiescent Current vs. Output Current, (High Load) Figure 11. Quiescent Current vs. Output Current, (Low Load) 50 Iq, QUIESCENT CURRENT (mA) Iq, QUIESCENT CURRENT (mA) 3.5 VI = 13.5 V IOUT = 100 mA 40 30 20 10 0 −40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Quiescent Current vs. Temperature www.onsemi.com 6 20 NCV8664C Typical Characteristic Curves − 3.3 V Version 100 3.36 VQ, OUTPUT VOLTAGE (V) Unstable Region ESR (W) 10 1 Stable Region 0.1 CQ = 10 mF 0.01 0 25 50 75 100 125 VI = 13.5 V RL = 660 W 3.26 0 40 80 120 160 Figure 13. Output Stability with Output Capacitor ESR Figure 14. Output Voltage vs. Junction Temperature 350 IQ, OUTPUT CURRENT (mA) VQ, OUTPUT VOLTAGE (V) 3.28 TJ, JUNCTION TEMPERATURE (°C) 2 RL = 22 W TJ = 25°C 1 0 1 2 3 4 5 6 7 8 9 300 250 200 150 VQ = 0 V TJ = 25°C 100 50 0 10 0 5 10 15 20 25 30 35 45 40 VI, INPUT VOLTAGE (V) VI, INPUT VOLTAGE (V) Figure 15. Output Voltage vs. Input Voltage Figure 16. Maximum Output Current vs. Input Voltage 1.50 50 TJ = 25°C Iq, QUIESCENT CURRENT (mA) Iq, QUIESCENT CURRENT (mA) 3.30 IQ, OUTPUT CURRENT (mA) 3 1.25 1.00 RL = 50 W 0.75 0.50 RL = 100 W 0.25 0 3.32 3.24 −40 150 4 0 3.34 0 5 10 15 20 25 30 35 40 40 30 20 VI = 13.5 V IOUT = 100 mA 10 0 −40 45 0 40 80 120 160 VI, INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C) Figure 17. Quiescent Current vs. Input Voltage Figure 18. Quiescent Current vs. Temperature www.onsemi.com 7 NCV8664C Typical Characteristic Curves − 3.3 V Version 0.25 VI = 13.5 V TJ = 25°C 3.0 Iq, QUIESCENT CURRENT (mA) Iq, QUIESCENT CURRENT (mA) 3.5 2.5 2.0 1.5 1.0 0.5 0 0 25 50 75 100 125 0.15 0.10 0.05 0 150 VI = 13.5 V TJ = 25°C 0.20 0 2 4 6 8 10 12 14 16 18 IQ, OUTPUT CURRENT (mA) IQ, OUTPUT CURRENT (mA) Figure 19. Quiescent Current vs. Output Current, (High Load) Figure 20. Quiescent Current vs. Output Current, (Low Load) www.onsemi.com 8 20 NCV8664C Circuit Description Calculating Power Dissipation in a Single Output Linear Regulator The NCV8664C is a precision trimmed 3.3 V and 5.0 V fixed output regulator. Careful management of light load consumption combined with a low leakage process results in a typical quiescent current of 22 mA. The device has current capability of 150 mA, with 600 mV of dropout voltage at full rated load current. The regulation is provided by a PNP pass transistor controlled by an error amplifier with a bandgap reference. The regulator is protected by both current limit and short circuit protection. Thermal shutdown occurs above 150°C to protect the IC during overloads and extreme ambient temperatures. The maximum power dissipation for a single output regulator (Figure 3) is: PD(max)  [VIN(max)  VOUT(min)]  IQ(max)  VI(max)  Iq (eq. 1) Where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IQ(max) is the maximum output current for the application, and Iq is the quiescent current the regulator consumes at IQ(max). Once the value of PD(Max) is known, the maximum permissible value of RqJA can be calculated: Regulator The error amplifier compares the reference voltage to a sample of the output voltage (Vout) and drives the base of a PNP series pass transistor by a buffer. The reference is a bandgap design to give it a temperature−stable output. Saturation control of the PNP is a function of the load current and input voltage. Over saturation of the output power device is prevented, and quiescent current in the ground pin is minimized. The NCV8664C is equipped with foldback current protection. This protection is designed to reduce the current limit during an overcurrent situation. PqJA  150 oC  TA PD (eq. 2) The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA’s less than the calculated value in Equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heat sink will be required. The current flow and voltages are shown in the Measurement Circuit Diagram. Regulator Stability Considerations The input capacitor CIN in Figure 2 is necessary for compensating input line reactance. Possible oscillations caused by input inductance and input capacitance can be damped by using a resistor of approximately 1 W in series with CIN. The output or compensation capacitor, COUT helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. Tantalum, aluminum electrolytic, film, or ceramic capacitors are all acceptable solutions, however, attention must be paid to ESR constraints. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 2 should work for most applications; however, it is not necessarily the optimized solution. Actual Stability Regions are shown in the graphs in the Typical Performance Characteristics section. Heat Sinks A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA: RqJA  RqJC  RqCS  RqSA (eq. 3) Where: RqJC = the junction−to−case thermal resistance, RqCS = the case−to−heat sink thermal resistance, and RqSA = the heat sink−to−ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in data sheets of heatsink manufacturers. Thermal, mounting, and heat sinking are discussed in the ON Semiconductor application note AN1040/D, available on the ON Semiconductor Website. www.onsemi.com 9 180 RqJA, THERMAL RESISTANCE (°C/W) RqJA, THERMAL RESISTANCE (°C/W) NCV8664C 160 140 120 1 oz 100 80 2 oz 60 40 0 100 200 300 400 500 600 700 120 110 100 90 80 1 oz 70 60 2 oz 50 40 0 COPPER SPREADER AREA (mm2) 200 400 600 800 1000 COPPER SPREADER AREA (mm2) Figure 21. RqJA vs. Copper Spreader Area, SOT−223 Figure 22. RqJA vs. Copper Spreader Area, DPAK 1000 Cu Area 100 mm2, 1 oz R(t) (°C/W) 100 10 1 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (sec) Figure 23. Single−Pulse Heating Curve, SOT−223 100 R(t) (°C/W) Cu Area 100 mm2, 1 oz 10 1 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 PULSE TIME (sec) Figure 24. Single−Pulse Heating Curve, DPAK www.onsemi.com 10 10 100 1000 NCV8664C ORDERING INFORMATION Device* Marking Package Shipping† NCV8664CDT50RKG 664C50G DPAK (Pb−Free) 2500 / Tape & Reel NCV8664CDT33RKG 664C33G DPAK (Pb−Free) 2500 / Tape & Reel NCV8664CST50T3G 664C5 SOT−223 (Pb−Free) 4000 / Tape & Reel NCV8664CST33T3G 664C3 SOT−223 (Pb−Free) 4000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−223 (TO−261) CASE 318E−04 ISSUE R DATE 02 OCT 2018 SCALE 1:1 q q DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com SOT−223 (TO−261) CASE 318E−04 ISSUE R STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. ANODE CATHODE NC CATHODE STYLE 6: PIN 1. 2. 3. 4. RETURN INPUT OUTPUT INPUT STYLE 7: PIN 1. 2. 3. 4. ANODE 1 CATHODE ANODE 2 CATHODE STYLE 11: PIN 1. MT 1 2. MT 2 3. GATE 4. MT 2 STYLE 3: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 8: STYLE 12: PIN 1. INPUT 2. OUTPUT 3. NC 4. OUTPUT CANCELLED DATE 02 OCT 2018 STYLE 4: PIN 1. 2. 3. 4. SOURCE DRAIN GATE DRAIN STYLE 5: PIN 1. 2. 3. 4. STYLE 9: PIN 1. 2. 3. 4. INPUT GROUND LOGIC GROUND STYLE 10: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE DRAIN GATE SOURCE GATE STYLE 13: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR GENERIC MARKING DIAGRAM* AYW XXXXXG G 1 A = Assembly Location Y = Year W = Work Week XXXXX = Specific Device Code G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE G 4 1 2 DATE 31 MAY 2023 3 SCALE 1:1 GENERIC MARKING DIAGRAM* STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR DOCUMENT NUMBER: DESCRIPTION: STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE 98AON10527D DPAK (SINGLE GAUGE) XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete XXXXXX A L Y WW G = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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