NCV8668

NCV8668

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    ONSEMI(安森美)

  • 封装:

  • 描述:

    NCV8668 - Very Low I 150 mA LDO Regulator with Window Watchdog, Enable and Reset - ON Semiconductor

  • 数据手册
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NCV8668 数据手册
NCV8668 Very Low Iq 150 mA LDO Regulator with Window Watchdog, Enable and Reset The NCV8668 is 150 mA LDO regulator with integrated window watchdog and reset functions dedicated for microprocessor applications. Its robustness allows NCV8668 to be used in severe automotive environments. Very low quiescent current as low as 38 mA typical makes it suitable for applications permanently connected to battery requiring very low quiescent current with or without load. The Enable function can be used for further decrease of quiescent current down to 1 mA. The NCV8668 contains protection functions as current limit and thermal shutdown. Features http://onsemi.com MARKING DIAGRAMS 14 1 SOIC−14 CASE 751A 1 14 V8668ZZXXG AWLYWW 8 1 SOIC−8 D SUFFIX CASE 751A 8 668ZZX ALYW G • • • • • • • • • • • • • • Output Voltage Options: 3.3 V and 5 V Output Voltage Accuracy: $1.5% (TJ = 25°C to 125°C) Output Current up to 150 mA Very Low Quiescent Current: Typ 38 mA (max 43 mA) Very Low Dropout Voltage Enable Function Microprocessor Compatible Control Functions: ♦ Reset with Adjustable Power−on Delay ♦ Window Watchdog Wide Input Voltage Operation Range: up to 40 V Protection Features: ♦ Current Limitation ♦ Reverse Output Current ♦ Thermal Shutdown These are Pb−Free Devices Body Control Module Instruments and Clusters Occupant Protection and Comfort Powertrain VBAT V in C in 0.1 mF V out Vout C out 2.2 mF VDD 1 8 8 1 SOIC−8 EP CASE 751AC ZZ 1 668ZZX AYWWG G Typical Applications = Timing, Reset Threshold, Watchdog Control Options* XX,X = Voltage Options = 5 V (XX = 50, X = 5) = 3.3 V (XX = 33, X = 3) A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package *See APPLICATION INFORMATION Section. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. NCV8668 RO WDI Microprocessor RESET I/O I/O I/O OFF ON EN GND WM1 WM2 Figure 1. Application Schematic © Semiconductor Components Industries, LLC, 2010 October, 2010 − Rev. 2 1 Publication Order Number: NCV8668/D NCV8668 Vin Vout * Driver with Current Limit Thermal Shutdown Vref RESET GENERATOR and WINDOW WATCHDOG RO WDI WM1 WM2 EN GND Enable * 5 V OPTION ONLY Figure 2. Simplified Block Diagram RO GND GND GND GND WM 2 WM 1 1 14 EN Vin GND GND GND Vout WDI 1 RO GND WM 2 WM 1 SOIC−8 8 EN Vin Vout WDI 1 RO GND WM 2 WM 1 SOIC−8 EP 8 EN Vin Vout WDI SOIC−14 Figure 3. Pin Connections (Top View) PIN FUNCTION DESCRIPTION Pin No. SOIC−14 1 Pin No. SOIC−8 1 Pin No. SOIC−8 EP 1 Pin Name RO Description Reset Output. 30 kW internal Pull−Up resistor connected to Vout. (Open Drain output for 2.5 V, 2.6 V, and 3.3 V voltage options) RO goes Low when Vout drops by more than 7% from nominal. Power Supply Ground. For SOIC−14 − connect pin 2 and 3 to GND − connect pin 4−5 and 10−12 to heatsink area with GND potential Watchdog Mode Bit 2; Watchdog and Reset mode selection. Connect to Vout or GND. Watchdog Mode Bit 1; Watchdog and Reset mode selection. Connect to Vout or GND. Watchdog Input; Trigger Input for Watchdog pulses. When not used, connect to Vout or GND. Regulated Output Voltage. Connect 2.2 mF capacitor with ESR < 100 W to ground. Positive Power Supply Input. Connect 0.1 mF capacitor to ground. Enable Input; low level disables the IC. Exposed Pad is Connected to Ground 2, 3, 4, 5, 10, 11, 12 2 2 GND 6 7 8 9 13 14 3 4 5 6 7 8 3 4 5 6 7 8 EPAD WM2 WM1 WDI Vout Vin EN GND http://onsemi.com 2 NCV8668 ABSOLUTE MAXIMUM RATINGS Rating Input Voltage (Note 1) DC Transient, t < 100 ms Input Current Output Voltage (Note 2) Output Current Enable Input Voltage Range DC Transient, t < 100 ms Enable Input Current Range Reset Output Voltage (Note 3) Reset Output Current Watchdog Input Voltage Watchdog Mode 1 Voltage Watchdog Mode 1 Current Watchdog Mode 2 Voltage Watchdog Mode 2 Current Junction Temperature Storage Temperature Symbol Vin Min −0.3 − −5 −0.3 −3 −0.3 − −1 −0.3 −3 −0.3 −0.3 −5 −0.3 −5 −40 −55 Max 40 45 − 5.5 Current Limited 40 45 1 5.5 3 5.5 5.5 5 5.5 5 150 150 Unit V Iin Vout Iout VEN mA V mA V IEN VRO IRO VWDI VWM1 IWM1 VWM2 IWM2 TJ TSTG mA V mA V V mA V mA °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. The Output voltage must not exceed the Input voltage. 3. The Reset Output voltage must not exceed the Output voltage. ESD CAPABILITY (Note 4) Rating ESD Capability, Human Body Model ESD Capability, Machine Model Symbol ESDHBM ESDMM Min −2 −200 Max 2 200 Unit kV V 4. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) LEAD SOLDERING TEMPERATURE AND MSL (Note 5) Rating Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free Versions (Note 5) Moisture Sensitivity Level (SOIC−14, SOIC−8) (SOIC−8EP) Symbol TSLD MSL Min − 1 2 Max 265 peak Unit °C − 5. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D http://onsemi.com 3 NCV8668 THERMAL CHARACTERISTICS (Note 6) Rating Thermal Characteristics, SOIC−14 (Note 6) Thermal Resistance, Junction−to−Air (Note 7) Thermal Reference, Junction−to−Lead4 (Note 7) Thermal Characteristics, SOIC−8 (Note 6) Thermal Resistance, Junction−to−Air (Note 7) Thermal Reference, Junction−to−Lead4 (Note 7) Thermal Characteristics, SOIC−8 EP (Note 6) Thermal Resistance, Junction−to−Air (Note 7) Thermal Reference, Junction−to−Lead4 (Note 7) Thermal Reference, Junction−to−Pad (Note 7) Symbol RqJA RYJL RqJA RYJL RqJA RYJL4 RYJPad Value 95 18.2 132 49.2 80 28.5 14.8 Unit °C/W °C/W °C/W 6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 7. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. RECOMMENDED OPERATING RANGES (Note 8) Rating Input Voltage (Note 9) Junction Temperature Symbol Vin TJ Min 4.5 −40 Max 40 150 Unit V °C 8. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 9. Minimum Vin = 4.5 V or (Vout + VDO), whichever is higher. ELECTRICAL CHARACTERISTICS Vin = 13.2 V, Cin = 0.1 mF, Cout = 2.2 mF, for typical values TJ = 25°C, for min/max values TJ = −40°C to 150°C; unless otherwise noted. (Notes 10 and 11) Parameter REGULATOR OUTPUT Output Voltage (Accuracy %) 3.3 V 5.0 V Output Voltage (Accuracy %) 3.3 V 5.0 V TJ = 25°C to 125°C Vin = 4.5 V to 16 V, Iout = 0.1 mA to 100 mA Vin = 5.5 V to 16 V, Iout = 0.1 mA to 100 mA Vout 3.2505 4.925 (−1.5%) 3.234 3.234 4.9 4.9 (−2%) 3.234 4.9 (−2%) −20 3.3 5.0 3.3495 5.075 (+1.5%) 3.366 3.366 5.1 5.1 (+2%) 3.366 5.1 (+2%) 20 V Test Conditions Symbol Min Typ Max Unit Vin = 4.5 V to 40 V, Iout = 0.1 mA to 100 mA Vin = 4.5 V to 16 V, Iout = 0.1 mA to 150 mA Vin = 5.55 V to 40 V, Iout = 0.1 mA to 100 mA Vin = 5.7 V to 16 V, Iout = 0.1 mA to 150 mA TJ = −40°C to 125°C Vin = 4.5 V to 28 V, Iout = 0 mA Vin = 5.5 V to 28 V, Iout = 0 mA Vout 3.3 3.3 5.0 5.0 V Output Voltage (Accuracy %) 3.3 V 5.0 V Line Regulation 5.0 V 3.3 V Load Regulation Dropout Voltage (Note 12) 5.0 V Output Capacitor for Stability (Note 13) Vout 3.3 5.0 0 V Vin = 5.5 V to 28 V, Iout = 5 mA Vin = 4.5 V to 28 V, Iout = 5 mA Iout = 0.1 mA to 150 mA Iout = 100 mA Iout = 150 mA Iout = 5 mA to 150 mA Iout = 0 mA to 5 mA Regline mV Regload VDO −40 − − 2.2 − 1 10 225 300 − − − 40 450 600 − 100 100 mV mV Cout ESR mF W W 10. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area. 11. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [TJ. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 12. Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.2 V. If Vout < 5 V, then VDO = Vin – Vout. Maximum dropout voltage value is limited by minimum input voltage Vin = 4.5 V recommended for guaranteed operation at maximum output current. 13. Values based on design and/or characterization. 14. Recommended for typical trigger time. TWD = tCW + 1/2 * tOW http://onsemi.com 4 NCV8668 ELECTRICAL CHARACTERISTICS Vin = 13.2 V, Cin = 0.1 mF, Cout = 2.2 mF, for typical values TJ = 25°C, for min/max values TJ = −40°C to 150°C; unless otherwise noted. (Notes 10 and 11) Parameter Disable and Quiescent Current Disable Current Quiescent Current (Iq = Iin – Iout) VEN = 0 V,TJ < 85°C Iout = 100 mA, TJ = 25°C Iout = 100 mA, TJ v 125°C Vout = 0.96 x Vout_nom Vout = 0 V VEN = 0 V, Iout = −1 mA IDIS Iq − − − − 38 − 1 43 44 mA mA Test Conditions Symbol Min Typ Max Unit Current Limit Protection Current Limit Short Circuit Current Limit Reverse Output Current Protection Reverse Output Current Protection PSRR Power Supply Ripple Rejection (Note 13) f = 100 Hz, 0.5Vpp Enable Thresholds Enable Input Threshold Voltage Logic High Logic Low Enable Input Current Logic High Logic Low Window Watchdog Watchdog Mode Bit 1 Threshold Voltage Voltage Increasing, Logic High 3.3 V 5.0 V Voltage Decreasing, Logic Low Watchdog Mode Bit 2 Threshold Voltage Voltage Increasing, Logic High 3.3 V 5.0 V Voltage Decreasing, Logic Low Watchdog Input WDI Threshold Voltage Voltage Increasing, Logic High 3.3 V 5.0 V Voltage Decreasing, Logic Low Watchdog Input WDI Current Logic High Logic Low Watchdog Sampling Time Ignore Window Time Open Window Time Closed Window Time VWDI,H = 5 V VWDI,L = 0 V, TJ < 85 °C Fast: Slow: Fast: Slow: Fast: Slow: Fast: Slow: WM2 = L WM1 = L AND WM2 = H WM2 = L WM1 = L AND WM2 = H WM2 = L WM1 = L AND WM2 = H WM2 = L WM1 = L AND WM2 = H VWM1,H VWM1,L VWM2,H VWM2,L VWDI,H VWDI,L IWDI,H IWDI,L tsam tIW tOW tCW V − − 0.8 − − − 2.65 4.0 − V − − 0.8 − − − 2.65 4.0 − V − − 0.8 − − 0.4 0.8 25.6 51.2 25.6 51.2 25.6 51.2 − − − 3 0.5 0.5 1.0 32.0 64.0 32.0 64.0 32.0 64.0 2.65 4.0 − 4 1 0.6 1.2 38.4 76.8 38.4 76.8 38.4 76.8 mA VEN = 5 V VEN = 0 V, TJ < 85°C Vth(EN) 3 − − − − − 3 0.5 − 0.8 5 1 V PSRR − 60 − dB Vout_rev − 2 5.5 V ILIM ISC 205 205 − − 525 525 mA mA IEN_ON IEN_OFF mA ms ms ms ms 10. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area. 11. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [TJ. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 12. Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.2 V. If Vout < 5 V, then VDO = Vin – Vout. Maximum dropout voltage value is limited by minimum input voltage Vin = 4.5 V recommended for guaranteed operation at maximum output current. 13. Values based on design and/or characterization. 14. Recommended for typical trigger time. TWD = tCW + 1/2 * tOW http://onsemi.com 5 NCV8668 ELECTRICAL CHARACTERISTICS Vin = 13.2 V, Cin = 0.1 mF, Cout = 2.2 mF, for typical values TJ = 25°C, for min/max values TJ = −40°C to 150°C; unless otherwise noted. (Notes 10 and 11) Parameter Window Watchdog Window Watchdog Trigger Time (Note 14) Watchdog Deactivation Current Threshold 3.3 V 5.0 V Watchdog Activating Current Threshold 3.3 V 5.0 V Reset Output RO Input Voltage Reset Threshold 3.3 V Output Voltage Reset Threshold 3.3 V 5.0 V Reset Hysteresis Maximum Reset Sink Current 3.3 V 5.0 V Reset Output Low Voltage Reset Output High Voltage 5.0 V Reset High Level Leakage Current 3.3 V Integrated Reset Pull Up Resistor 5.0 V Reset Delay Time Reset Reaction Time (See Figure 24) THERMAL SHUTDOWN Thermal Shutdown Temperature (Note 13) Thermal Shutdown Hysteresis (Note 13) TSD TSH 150 − 175 25 195 − °C °C Fast: WM1 = L AND WM2 = L Slow:WM1 = H OR (WM1 = L AND WM2 = H) Vout = 3 V, VRO = 0.25 V Vout = 4.5 V, VRO = 0.25 V Vout > 1 V, IRO < 200 mA Vin decreasing, Vout > VRT Vout decreasing Vin > 4.5 V Vin > 5.5 V Vin_RT VRT − 90 90 − 1.3 1.75 − 4.5 − 15 12.8 25.6 16 3.8 93 93 2.0 − − 0.15 − − 30 16 32 25 4.2 96 96 − − − 0.25 − 1 50 19.2 38.4 38 V %Vout Fast: Slow: WM2 = L WM1 = L AND WM2 = H tWD Iout_WD_OFF 0.5 0.5 Iout_WD_ON − − − − 2 2 − − 5 5 mA − − 48 96 − − ms mA Test Conditions Symbol Min Typ Max Unit Iout decreasing Vin > 4.5 V Vin > 5.5 V Iout increasing Vin > 4.5 V Vin > 5.5 V VRH IRomax %Vout mA VROL VROH IROLK RRO tRD tRR V V mA kW ms ms 10. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area. 11. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [TJ. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 12. Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.2 V. If Vout < 5 V, then VDO = Vin – Vout. Maximum dropout voltage value is limited by minimum input voltage Vin = 4.5 V recommended for guaranteed operation at maximum output current. 13. Values based on design and/or characterization. 14. Recommended for typical trigger time. TWD = tCW + 1/2 * tOW http://onsemi.com 6 NCV8668 TYPICAL CHARACTERISTICS 40 Iq, QUIESCENT CURRENT (mA) 38 37 36 35 34 33 32 31 30 −40 −20 0 20 40 60 80 100 120 140 160 Iq, QUIESCENT CURRENT (mA) 39 Vin = 13.2 V Iout = 100 mA 200 Iout = 0 mA TJ = 25°C 150 100 50 0 0 5 10 15 20 25 30 35 40 TJ, JUNCTION TEMPERATURE (°C) Vin, INPUT VOLTAGE (V) Figure 4. Quiescent Current vs Temperature Figure 5. Quiescent Current vs Input Voltage (5 V option) 5.10 40 Iq, QUIESCENT CURRENT (mA) 39 38 37 36 35 34 33 32 31 30 0 25 50 75 100 125 150 25°C −40°C 150°C Vin = 13.2 V Vout, OUTPUT VOLTAGE (V) Vin = 13.2 V Iout = 100 mA 5.05 5.00 4.95 4.90 −40 −20 0 20 40 60 80 100 120 140 160 Iout, OUTPUT CURRENT (mA) TJ, JUNCTION TEMPERATURE (°C) Figure 6. Quiescent Current vs Output Current Figure 7. Output Voltage vs Temperature (5 V option) 600 VDO, DROPOUT VOLTAGE (mV) 6 Iout = 1 mA Vout, OUTPUT VOLTAGE (V) 5 TJ = 25°C 4 3 2 1 0 500 400 300 200 100 0 150°C 25°C −40°C 0 25 50 75 100 125 150 0 1 2 3 4 5 6 7 8 Vin, INPUT VOLTAGE (V) Iout, OUTPUT CURRENT (mA) Figure 8. Output Voltage vs Input Voltage (5 V option) Figure 9. Dropout Voltage vs Output Current (5 V option) http://onsemi.com 7 NCV8668 TYPICAL CHARACTERISTICS 800 VDO, DROPOUT VOLTAGE (mV) ILIM, ISC, CURRENT LIMIT (mA) 700 600 500 400 300 200 100 0 −40 −20 0 20 40 60 80 100 120 140 160 100 mA 150 mA 400 ISC @ Vout = 0 V 300 TJ = 25°C 200 ILIM @ Vout = 4.8 V (5 V option) 100 0 0 5 10 15 20 25 30 35 40 TJ, JUNCTION TEMPERATURE (°C) Vin, INPUT VOLTAGE (V) Figure 10. Dropout vs Temperature (5 V option) 400 ILIM, ISC, CURRENT LIMIT (mA) ESR, STABILITY REGION (W) Vin = 13.2 V 350 ISC @ Vout = 0 V ILIM @ Vout = 4.8 V (5 V option) 250 100 Figure 11. Current Limit vs. Input Voltage 10 Vin = 13.2 V TJ = −40°C to 150°C CLOAD = 2.2 mF − 100 mF 300 1 Stable Region 0.1 Unstable Region 1 10 100 1000 Iout, OUTPUT CURRENT (mA) 200 −40 −20 0 20 40 60 80 100 120 140 160 0.01 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Current Limit vs. Temperature 14.2 V Vin (1 V/div) TJ = 25°C Iout = 1 mA Cout = 10 mF trise/fall = 1 ms (Vin) 12.2 V Figure 13. Cout ESR Stability Region vs Output Current Iout (100 mA/div) 150 mA TJ = 25°C Vin = 13.2 V Cout = 10 mF trise/fall = 1 ms (Iout) 0.1 mA 5.14 V Vout (100 mV/div) 5V 5.1 V Vout (50 mV/div) 4.97 V TIME (100 ms/div) 4.82 V TIME (20 ms/div) Figure 14. Line Transients (5 V option) Figure 15. Load Transients (5 V option) http://onsemi.com 8 NCV8668 TYPICAL CHARACTERISTICS TJ = 25°C VEN = Vin Rout = 5 kW Vin (5 V/div) 100 90 80 70 PSRR (dB) 60 50 40 30 20 10 0 10 100 1000 f, FREQUENCY (Hz) 10000 100000 TJ = 25°C Vin = 13.2 V ±0.5 Vpp Cout = 2.2 mF Iout = 0.1 mA Vout (5 V/div) VRO (5 V/div) TIME (100 ms/div) Figure 16. Power Up/Down Response (5 V option) 6000 5000 4000 3000 2000 1000 0 10 IDIS, DISABLE CURRENT (mA) TJ = 25°C Vin = 13.2 V Cout = 2.2 mF Iout = 150 mA 4 Figure 17. PSRR vs. Frequency (5 V option) NOISE DENSITY (nV/√Hz) Vin = 13.2 V VEN = 0 V 3 2 1 100 1000 f, FREQUENCY (Hz) 10000 100000 0 −40 −20 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (°C) Figure 18. Noise vs. Frequency (5 V option) 4 VEN = 0 V IDIS, DISABLE CURRENT (mA) IEN, ENABLE CURRENT (mA) 3 150°C 2 125°C 85°C 0 0 5 10 15 20 25 30 35 40 40 50 Figure 19. Disable Current vs Temperature Vin = 13.2 V 150°C 25°C 30 20 −40°C 1 10 0 0 5 10 15 20 25 30 35 40 Vin, INPUT VOLTAGE (V) VEN, ENABLE VOLTAGE (V) Figure 20. Disable Current vs. Input Voltage Figure 21. Enable Current vs. Enable Voltage http://onsemi.com 9 NCV8668 TYPICAL CHARACTERISTICS 4.80 tRD, RESET DELAY TIME (ms) VRT, RESET THRESHOLD (V) Vin = 13.2 V 4.75 18 Vin = 13.2 V Reset Mode = FAST 17 4.70 16 4.65 15 4.60 −40 −20 0 20 40 60 80 100 120 140 160 14 −40 −20 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 22. Reset Threshold vs Temperature (5 V option) Figure 23. Reset Delay Time vs Temperature http://onsemi.com 10 NCV8668 TYPICAL CHARACTERISTICS Vin Vout < tRR VRT+ VRhys VRT VRO t t tRD tRR VROH VROL t Figure 24. Reset Function and Timing Diagram Trigger Reset & Disabled Watchdog Reset Trigger WD_ON No Trigger WD_ON Ignore Window WD_ON or Iout > Iout_WD_ON WD_OFF or Iout < Iout_WD_OFF Long Open Window WD_OFF or Iout < Iout_WD_OFF No Trigger WD_OFF or Iout < Iout_WD_OFF Trigger Disabled Watchdog WD_OFF or Iout < Iout_WD_OFF Open Window WD_OFF or Iout < Iout_WD_OFF No Trigger Trigger Closed Window WM1 WM2 Window Watchdog Mode Reset Mode L L FAST FAST L H SLOW SLOW H L FAST SLOW H H OFF SLOW Figure 25. Window Watchdog State Diagram, Watchdog and Reset Modes http://onsemi.com 11 NCV8668 TYPICAL CHARACTERISTICS Vin t VRT+V Rhys VRT Vout t Iout Iout_WD_OFF VRO VROH VROL t IW tmax=4xt OW t CW IW 1st LONG OW CW OW t OW OW IW 1st LONG OW CW IW 1st LONG OW CW IW 1st LONG OW t WD CW OW IW t RD t RD t RD Iout_WD_ON t RD t t RR t WINDOW VWDI Don‘t Care during IW Missing Pulse during OW Pulse during CW Current Controled WD − Turn off Normal Operation t t Figure 26. Window Watchdog Signal Diagram Closed window Open window Watchdog trigger signal Open window Closed window WDI Valid WDI WDI Not valid WDI t ECW t EOW Watchdog decoder sample point Figure 27. Valid WDI trigger signal http://onsemi.com 12 NCV8668 DEFINITIONS General Current Limit and Short Circuit Current Limit All measurements are performed using short pulse low duty cycle techniques to maintain junction temperature as close as possible to ambient temperature. Output Voltage Current Limit is value of output current by which output voltage drops below 96% of its nominal value. Short Circuit Current Limit is output current value measured with output of the regulator shorted to ground. PSRR The output voltage parameter is defined for specific temperature, input voltage and output current values or specified over Line, Load and Temperature ranges. Line Regulation Power Supply Rejection Ratio is defined as ratio of output voltage and input voltage ripple. It is measured in decibels (dB). Line Transient Response The change in output voltage for a change in input voltage measured for specific output current over operating ambient temperature range. Load Regulation Typical output voltage overshoot and undershoot response when the input voltage is excited with a given slope. Load Transient Response The change in output voltage for a change in output current measured for specific input voltage over operating ambient temperature range. Dropout Voltage Typical output voltage overshoot and undershoot response when the output current is excited with a given slope between low−load and high−load conditions. Thermal Protection The input to output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. It is measured when the output drops 100 mV below its nominal value. The junction temperature, load current, and minimum input supply requirements affect the dropout level. Quiescent Currents Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated at typically 175°C, the regulator turns off. This feature is provided to prevent failures from accidental overheating. Maximum Package Power Dissipation Quiescent Current (Iq) is the difference between the input current (measured through the LDO input pin) and the output current. The power dissipation level is maximum allowed power dissipation for particular package or power dissipation at which the junction temperature reaches its maximum operating value, whichever is lower. APPLICATIONS INFORMATION The NCV8668 regulator is self−protected with internal thermal shutdown and internal current limit. Typical characteristics are shown in Figures 4 to 27. A ceramic or tantalum 0.1 mF capacitor is recommended and should be connected close to the NCV8668 package. Higher capacitance and lower ESR will improve the overall line and load transient response. If extremely fast input voltage transients are expected then appropriate input filter must be used in order to decrease rising and/or falling edges below 50 V/ms for proper operation. The filter can be composed of several capacitors in parallel. Output Decoupling (Cout) Input Decoupling (Cin) decoupling value is 2.2 mF and can be augmented to fulfill stringent load transient requirements. The regulator works with ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response. Enable Operation The Enable pin will turn the regulator on or off. The threshold limits are covered in the electrical characteristics table in this data sheet. Reset Operation The NCV8668 is a stable component and does not require a minimum Equivalent Series Resistance (ESR) for the output capacitor. Stability region of ESR versus Output Current is shown in Figure 13. The minimum output A reset signal is provided on the Reset Output (RO) pin to provide feedback to the microprocessor of an out of regulation condition. The timing diagram of reset function is shown in Figure 24. This is in the form of a logic signal on RO. Output voltage conditions below the RESET threshold cause RO to go low. The RO integrity is maintained down to VOUT = 1.0 V. The Reset Output (RO) circuitry includes http://onsemi.com 13 NCV8668 a pull−up resistor (30 kW) internally connected to the output (VOUT). No external pull−up is necessary. For voltage option 3.3 V RO is open drain output and external pull−up resistor is required. Reset signal is also generated in case when input voltage decreases below its minimum operating limit (4.5 V). The Input Voltage Reset Threshold is typically 3.8 V. This applies only to voltage options with nominal value below minimum operating input voltage (3.3 V). Window Watchdog Operation affect the rate of junction temperature rise for the part. When the NCV8668 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power applications. The maximum dissipation the NCV8668 can handle is given by: P D(MAX) + T J(MAX) * T A R qJA (eq. 1) The watchdog slow, fast or off state is set by pins WM1 and WM2 (see table in Figure 25). The timing values used in this description refer to typ. Values when WM1 and WM2 are connected to GND (fast watchdog and reset timing). The state diagram of the window watchdog (WWD) and the watchdog and reset mode selection table is shown in Figure 25. The WWD timing is shown in Figure 26. After power−on, the reset output signal at the RO pin (microprocessor reset) is kept LOW for the reset delay time tRD (16 ms). RO signal transition from LOW to HIGH triggers the ignore window (IW) with duration of tIW (32 ms). During this window the signal at the WDI pin is ignored. When IW ends a long open window with maximum duration of (128 ms, tmax = 4xtOW) is started. When a valid trigger signal is detected during long open window, a closed window (CW) with duration of tCW (32 ms) is initialized immediately. WDI signal transition from HIGH to LOW is taken as a trigger. As valid trigger two HIGH samples followed by two LOW samples (with sampling time tsam = 0.5 ms) have to be present before end of the long window. Valid WDI trigger signal is shown in Figure 27. When CW ends a standard open window (OW) with maximum duration of tOW (32 ms) is initiated immediately. The OW ends immediately when valid trigger appears at WDI input. For normal operation the microprocessor timing of WDI pulses must be stable and correspond to tWD. A reset signal is generated (RO goes LOW) if there is no valid trigger (missing pulse at WDI pin) during OW or if a pre−trigger occurs during the CW (unexpected pulse at WDI pin). Thermal Considerations Since TJ is not recommended to exceed 150°C, then the NCV8668 soldered on 645 mm2, 1 oz copper area, FR4 can dissipate up to 1.3 W for SOIC−14 package when the ambient temperature (TA) is 25°C. See Figure 28 for RqJA versus PCB area. The power dissipated by the NCV8668 can be calculated from the following equations: P D + V in I q@I out ) I out V in * V out (eq. 2) or V in(MAX) + 140 SOIC−14 130 120 110 PCB 1 oz Cu PCB 2 oz Cu 0 100 200 300 400 500 600 700 P D(MAX) ) V out I out ) I q I out (eq. 3) RqJA, THERMAL RESISTANCE (°C/W) 100 90 80 COPPER HEAT SPREADER AREA (mm2) Figure 28. Thermal Resistance vs PCB Copper Area Hints As power in the NCV8668 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature Vin and GND printed circuit board traces should be as wide as possible. When the impedance of these traces is high, there is a chance to pick up noise or cause the regulator to malfunction. Place external components, especially the output capacitor, as close as possible to the NCV8668, and make traces as short as possible. http://onsemi.com 14 NCV8668 ORDERING INFORMATION tRD Fast/ Slow 16 / 32 ms 16 / 32 ms 16 / 32 ms 16 / 32 ms 16 / 32 ms IW/OW/CW Time Fast/ Slow 32 / 64 ms 1st LOW Time Fast/ Slow 128 / 256 ms 128 / 256 ms 128 / 256 ms 128 / 256 ms 128 / 256 ms Output Current WW ON/ OFF Yes Device NCV8668ABD250R2G Vout 5.0 V VRT 93% Marking V8668AB50G Package SOIC−14 (Pb−Free) SOIC−8 (Pb−Free) SOIC−8 EPAD (Pb−Free) SOIC−8 EPAD (Pb−Free) SOIC−8 (Pb−Free) Shipping† 2500 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel NCV8668ABD150R2G 5.0 V 32 / 64 ms 93% Yes 668AB5 NCV8668ABPD50R2G 5.0 V 32 / 64 ms 93% Yes 668AB5 NCV8668ABPD33R2G 3.3 V 32 / 64 ms 93% Yes 668AB3 NCV8668ABD133R2G 3.3 V 32 / 64 ms 93% Yes 668AB3 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NOTE: Contact factory for other package, output voltage, timing and reset threshold options http://onsemi.com 15 NCV8668 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 A 8 5 B 1 S 4 0.25 (0.010) M Y M −Y− G K C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 16 NCV8668 PACKAGE DIMENSIONS SOIC−8 EP CASE 751AC−01 ISSUE B 2X NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS (ANGLES IN DEGREES). 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 MM TOTAL IN EXCESS OF THE “b” DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DATUMS A AND B TO BE DETERMINED AT DATUM PLANE H. DIM A A1 A2 b b1 c c1 D E E1 e L L1 F G h q MILLIMETERS MIN MAX 1.35 1.75 0.00 0.10 1.35 1.65 0.31 0.51 0.28 0.48 0.17 0.25 0.17 0.23 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.40 1.27 1.04 REF 2.24 3.20 1.55 2.51 0.25 0.50 0_ 8_ D A 8 5 0.10 C A-B D DETAIL A EXPOSED PAD 5 F 8 2X 0.10 C D PIN ONE LOCATION 0.10 C 8X A2 A GAUGE PLANE 0.10 C SEATING PLANE b1 L (L1) DETAIL A q C SIDE VIEW A1 0.25 c1 SECTION A−A SOLDERING FOOTPRINT* 2.72 0.107 1.52 0.060 7.0 0.275 2.03 0.08 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 17 ÉÉ ÇÇ ÉÉ ÇÇ ÉÉ ÇÇ ÉÉ ÉÉÉ ÉÉÉ 1 E1 E 2X 4 G h 4 1 0.20 C 8X b 0.25 C A-B D e BOTTOM VIEW B TOP VIEW A A END VIEW H c (b) Exposed Pad mm inches NCV8668 PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE J −A− 14 8 −B− P 7 PL 0.25 (0.010) M B M 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C −T− SEATING PLANE R X 45 _ F D 14 PL 0.25 (0.010) K M M S J TB A S SOLDERING FOOTPRINT* 7X DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 7.04 1 0.58 14X 14X 1.52 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 18 NCV8668/D
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