NCV8772

NCV8772 Ultra Low Iq 350 mA LDO Regulator with Enable and Reset The NCV8772 is 350 mA LDO regulator with integrated reset functions dedicated for microprocessor applications. Its robustness allows NCV8772 to be used in severe automotive environments. Ultra low quiescent current as low as 24 mA typical makes it suitable for applications permanently connected to battery requiring ultra low quiescent current with or without load. This feature is especially critical when modules remain in active mode when ignition is off. The Enable function can be used for further decrease of quiescent current in shutdown mode to 1 mA. The NCV8772 contains protection functions as current limit, thermal shutdown and reverse output current protection. Features http://onsemi.com MARKING DIAGRAMS D2PAK−5 D5S SUFFIX CASE 936A NC V8772yxx AWLYWWG • • • • • • • • • • • • • • Output Voltage Options: 5 V Output Voltage Accuracy: ±1.5% (TJ = 25°C to 125°C) Output Current up to 350 mA Ultra Low Quiescent Current: typ 24 mA (max 30 mA) Very Wide Range of Cout and ESR Values for Stability Enable Function − 1 mA Max Quiescent Current when disabled Microprocessor Compatible Control Functions: − Reset with Adjustable Power−On Delay Wide Input Voltage Operation Range: up to 40 V Protection Features − Current Limitation − Thermal Shutdown − Reverse Output Current Protection These are Pb−Free Devices Body Control Module Instruments and Clusters Occupant Protection and Comfort Powertrain VBAT Cin 0.1 mF Vin Vout Vout Cout 1 mF VDD Microprocessor 1 D2PAK−7 D7S SUFFIX CASE 936AB NC V8772yxx AWLYWWG 1 y x, xx A WL Y WW G = Timing and Reset Threshold Option = Voltage Option = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Typical Applications ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. NCV8772 DT* OFF ON EN GND RO RESET * D2PAK−7 ONLY Figure 1. Typical Application Schematic © Semiconductor Components Industries, LLC, 2011 March, 2011 − Rev. 2 1 Publication Order Number: NCV8772/D NCV8772 Vin Vout Thermal Shutdown Driver With Current Limit EN Enable Erorr Amplifier Reset Comparator Reset Driver RO Reference Timing Circuit DT* ** GND Timer * D2PAK−7 ONLY ** Pull−Down Resistor (typ 150 kW) active only in Reset State Figure 2. Simplified Block Diagram PIN CONNECTIONS PIN Tab, 1. Vin 2. RO 3. GND 4. EN 5. Vout PIN Tab, 1. Vin 2. RO 3. NC 4. GND 5. EN 6. DT 7. Vout 1 D2PAK−5 1 D2PAK−7 Figure 3. Pin Connections PIN FUNCTION DESCRIPTION Pin No. D2PAK−5 1 2 Pin No. D2PAK−7 1 2 Pin Name Vin RO Description Positive Power Supply Input. Connect 0.1 mF capacitor to ground. Reset Output. 30 kW internal Pull−up resistor connected to Vout. RO goes Low when Vout drops by more than 7% (typ) from its nominal value (for NCV8772y devices with y = 1,2,3,...) or more than 10% (typ) from its nominal value (for NCV8772y devices with y = A, B, C,...). Not Connected Power Supply Ground. Enable Input; low level disables the IC. Reset Delay Time Select. Short to GND or connected to Vout to select time. Regulated Output Voltage. Connect 1 mF capacitor with ESR < 100 W to ground. − 3, TAB 4 − 5 3 4, TAB 5 6 7 NC GND EN DT Vout http://onsemi.com 2 NCV8772 ABSOLUTE MAXIMUM RATINGS Rating Input Voltage (Note 1) Input Current Output Voltage (Note 2) Output Current Enable Input Voltage Enable Input Current DT (Reset Delay Time Select) Voltage DT (Reset Delay Time Select) Current Reset Output Voltage Reset Output Current Junction Temperature Storage Temperature DC Transient, t < 100 ms DC Transient, t < 100 ms Symbol Vin Iin Vout Iout VEN IEN VDT IDT VRO IRO TJ TSTG Min −0.3 − −5 −0.3 −3 −0.3 − −1 −0.3 −1 −0.3 −3 −40 −55 Max 40 45 − 5.5 Current Limited 40 45 1 5.5 1 5.5 3 150 150 Unit V mA V mA V mA V mA V mA °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. 5.5 V or (Vin + 0.3 V) (whichever is lower). ESD CAPABILITY (Note 3) Rating ESD Capability, Human Body Model ESD Capability, Machine Model ESD Capability, Charged Device Model Symbol ESDHBM ESDMM ESDCDM Min −2 −200 −1 Max 2 200 1 Unit kV V kV 3. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) ESD Charge Device Model tested per AEC−Q100−011 (EIA/JESD22−C101) LEAD SOLDERING TEMPERATURE AND MSL (Note 4) Rating Moisture Sensitivity Level D2PAK−5 D2PAK−7 Symbol MSL TSLD Min 1 3 − 265 peak Max Unit − °C Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free Versions 4. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. THERMAL CHARACTERISTICS (Note 5) Rating Thermal Characteristics, D2PAK−5 Thermal Resistance, Junction−to−Air (Note 6) Thermal Reference, Junction−to−Case (Note 6) Thermal Characteristics, D2PAK−7 Thermal Resistance, Junction−to−Air (Note 6) Thermal Reference, Junction−to−Case (Note 6) Symbol RqJA RYJC RqJA RYJC Value 53 8.4 51 8.4 Unit °C/W °C/W 5. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 6. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. http://onsemi.com 3 NCV8772 RECOMMENDED OPERATING RANGE (Note 7) Rating Input Voltage (Note 8) Junction Temperature Symbol Vin TJ Min 5.5 −40 Max 40 150 Unit V °C 7. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 8. Minimum Vin = 5.5 V or (Vout + VDO), whichever is higher. ELECTRICAL CHARACTERISTICS Vin = 13.2 V, VEN = 3 V, Cin = 0.1 mF, Cout = 1 mF, for typical values TJ = 25°C, for min/max values TJ = −40°C to 150°C; unless otherwise noted. (Notes 9 and 10) Parameter REGULATOR OUTPUT Output Voltage (Accuracy %) TJ = 25 °C to 125 °C Vin = 5.575 V to 16 V, Iout = 0.1 mA to 200 mA Vout 4.925 (−1.5 %) 4.9 4.9 (−2 %) 4.9 (−2 %) −20 −35 − − 1 0.01 5.0 5.075 (+1.5%) 5.1 5.1 (+2%) 5.1 (+2%) 20 35 500 875 100 100 V Test Conditions Symbol Min Typ Max Unit Output Voltage (Accuracy %) Vin = 5.6 V to 40 V, Iout = 0.1 mA to 200 mA Vin = 5.975 V to 16 V, Iout = 0.1 mA to 350 mA TJ = −40°C to 125°C Vin = 5.975 V to 28 V, Iout = 0 mA to 350 mA Vin = 6 V to 28 V, Iout = 5 mA Iout = 0.1 mA to 350 mA Iout = 200 mA Iout = 350 mA Iout = 0 mA to 350 mA Vout 5.0 5.0 V Output Voltage (Accuracy %) Vout 5.0 0 10 250 440 − − V Line Regulation Load Regulation Dropout Voltage (Note 11) Regline Regload VDO mV mV mV Output Capacitor for Stability (Note 12) Cout ESR mF W DISABLE AND QUIESCENT CURRENTS Disable Current Quiescent Current (Iq = Iin − Iout) VEN = 0 V, TJ < 85°C Iout = 0.1 mA, TJ = 25°C Iout = 0.1 mA to 350 mA, TJ ≤ 125°C IDIS Iq − − − − 24 − 1 29 30 mA mA CURRENT LIMIT PROTECTION Current Limit Short Circuit Current Limit Vout = 0.96 x Vout_nom Vout = 0 V VEN = 0 V, Iout = −1 mA ILIM ISC Vout_rev PSRR 400 400 − − 1100 1100 mA mA REVERSE OUTPUT CURRENT PROTECTION Reverse Output Current Protection PSRR Power Supply Ripple Rejection (Note 12) f = 100 Hz, 0.5 Vpp ENABLE THRESHOLDS Enable Input Threshold Voltage Logic Low Logic High Enable Input Current Logic High Logic Low VEN = 5 V VEN = 0 V, TJ < 85°C Vth(EN) − 2.5 − − − − 3 0.5 0.8 − 5 1 V − 60 − dB − 2 5.5 V IEN_ON IEN_OFF mA 9. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area. 10. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [ TJ. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 11. Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.2 V. 12. Values based on design and/or characterization. 13. See APPLICATION INFORMATION section for Reset Thresholds and Reset Delay Time Options http://onsemi.com 4 NCV8772 ELECTRICAL CHARACTERISTICS Vin = 13.2 V, VEN = 3 V, Cin = 0.1 mF, Cout = 1 mF, for typical values TJ = 25°C, for min/max values TJ = −40°C to 150°C; unless otherwise noted. (Notes 9 and 10) Parameter DT (RESET DELAY TIME SELECT) − D2PAK−7 ONLY DT Threshold Voltage Logic Low Logic High DT Input Current RESET OUTPUT RO Output Voltage Reset Threshold (Note 13) (NCV8772y) where y = 1,2,3,... (NCV8772y) where y = A,B,C,... Reset Hysteresis Maximum Reset Sink Current Reset Output Low Voltage Reset Output High Voltage Integrated Reset Pull−up Resistor Reset Delay Time (D2PAK−5) (Note 13) Reset Delay Time (D2PAK−7) (Note 13) Reset Reaction Time (see Figure 24) THERMAL SHUTDOWN Thermal Shutdown Temperature (Note 12) Thermal Shutdown Hysteresis (Note 12) TSD TSH 150 − 175 25 195 − °C °C Min Available Time, DT connected to GND Max Available Time, DT connected to Vout Vout = 4.5 V, VRO = 0.25 V Vout > 1 V, IRO < 200 mA Vout decreasing, Vin > 5.5 V 5.0 V 5.0 V VRH IROmax VROL VROH RRO tRD tRD VRT 90 87 − 1.75 − 4.5 15 6.4 (−20%) 3.2 102.4 (−20%) 16 93 90 2.0 − 0.15 − 30 8 4 128 25 96 93 − − 0.25 − 50 9.6 (+20%) 4.8 153.6 (+20%) 38 %Vout mA V V kW ms ms %Vout VDT = 5 V Vth(DT) − 2.0 − − − − 0.8 − 1.0 V Test Conditions Symbol Min Typ Max Unit IDT mA tRR ms 9. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area. 10. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [ TJ. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 11. Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.2 V. 12. Values based on design and/or characterization. 13. See APPLICATION INFORMATION section for Reset Thresholds and Reset Delay Time Options http://onsemi.com 5 NCV8772 TYPICAL CHARACTERISTICS 30 Iq, QUIESCENT CURRENT (mA) 29 28 27 26 25 24 23 22 21 20 −40 −20 0 20 40 60 80 100 120 140 160 300 Iq, QUIESCENT CURRENT (mA) 250 200 150 100 50 0 Vin = 13.2 V Iout = 100 mA Iout = 0 mA TJ = 25°C 0 5 10 15 20 25 30 35 40 TJ, JUNCTION TEMPERATURE (°C) Vin, INPUT VOLTAGE (V) Figure 4. Quiescent Current vs. Temperature Figure 5. Quiescent Current vs. Input Voltage 30 Iq, QUIESCENT CURRENT (mA) 29 28 27 26 25 24 23 22 21 20 0 50 100 150 200 Vin = 13.2 V Vout, OUTPUT VOLTAGE (V) 5.10 Vin = 13.2 V Iout = 100 mA 5.05 TJ = 150°C TJ = −40°C TJ = 25°C 5.00 4.95 250 300 350 4.90 −40 −20 0 20 40 60 80 100 120 140 160 IOUT, OUTPUT CURRENT (mA) TJ, JUNCTION TEMPERATURE (°C) Figure 6. Quiescent Current vs. Output Current Figure 7. Output Voltage vs. Temperature 6 Vout, OUTPUT VOLTAGE (V) 5 4 3 2 TJ = 150°C 1 0 TJ = −40°C 0 1 2 3 4 5 6 7 8 TJ = 25°C VDO, DROPOUT VOLTAGE (mV) Iout = 1 mA 800 700 600 500 400 300 200 100 0 0 50 100 150 200 250 300 350 TJ = −40°C TJ = 150°C TJ = 25°C Vin, INPUT VOLTAGE (V) Iout, OUTPUT CURRENT (mA) Figure 8. Output Voltage vs. Input Voltage Figure 9. Dropout vs. Output Current http://onsemi.com 6 NCV8772 TYPICAL CHARACTERISTICS 800 VDO, DROPOUT VOLTAGE (mV) ILIM, ISC, CURRENT LIMIT (mA) 700 600 500 400 300 200 100 0 −40 −20 Iout = 350 mA Iout = 200 mA 800 700 600 500 400 300 200 100 0 0 5 10 15 20 25 30 Vin, INPUT VOLTAGE (V) 35 40 TJ = 25°C ISC @ Vout = 0 V ILIM @ Vout = 4.8 V Figure 10. Dropout vs. Temperature 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (°C) Figure 11. Output Current Limit vs. Input Voltage 100 800 ILIM, ISC, CURRENT LIMIT (mA) 750 700 650 600 550 500 450 400 −40 −20 0 20 40 60 80 ISC @ Vout = 0 V Vin = 13.2 V ESR, STABILITY REGION (W) 10 Vin = 13.2 V TJ = −40°C to 150°C Cout = 1 mF − 100 mF 1 STABLE REGION ILIM @ Vout = 4.8 V 0.1 100 120 140 160 0.01 0 50 100 150 200 250 300 350 TJ, JUNCTION TEMPERATURE (°C) Iout, OUTPUT CURRENT (mA) Figure 12. Output Current Limit vs. Temperature Figure 13. Cout ESR Stability Region vs. Output Current TJ = 25°C Vin = 13.2 V Cout = 10 mF trise/fall = 1 ms (Iout) 0.1 mA 5.3 V 5V 14.2 V Vin (1 V/div) 13 V TJ = 25°C Iout = 1 mA Cout = 10 mF trise/fall = 1 ms (Vin) 12.2 V 350 mA Iout (200 mA/div) Vout (50 mV/div) Vout (100 mV/div) 5V 4.98 V TIME (100 ms/div) 4.54 V TIME (20 ms/div) Figure 14. Line Transients Figure 15. Load Transients http://onsemi.com 7 NCV8772 TYPICAL CHARACTERISTICS TJ = 25°C VEN = Vin Rout = 5 kW Vin (5 V/div) 100 90 80 70 PSRR (dB) 60 50 40 30 20 10 0 10 100 1000 TJ = 25°C Vin = 13.2 V $ 0.5 Vpp Cout = 1 mF Iout = 1.0 mA Vout (5 V/div) VRO (5 V/div) 10000 100000 TIME (100 ms/div) f, FREQUENCY (Hz) Figure 16. Power Up/Down Response Figure 17. PSRR vs. Frequency 4500 4000 NOISE DENSITY (nV/√Hz) 3500 3000 2500 2000 1500 1000 500 0 10 100 1000 f, FREQUENCY (Hz) IDIS, DISABLE CURRENT (mA) TJ = 25°C Vin = 13.2 V Cout = 1 mF Iout = 350 mA 5 4 3 2 1 0 −40 −20 Vin = 13.2 V VEN = 0 V 10000 100000 0 20 40 60 80 100 120 140 160 Figure 18. Noise vs. Frequency Figure 19. Disable Current vs. Temperature TJ, JUNCTION TEMPERATURE (°C) 12 VEN = 0 V IDIS, DISABLE CURRENT (mA) IEN, ENABLE CURRENT (mA) 10 8 6 4 2 0 TJ = 125°C TJ = 85°C 0 5 10 15 20 25 30 35 40 TJ = 150°C 50 40 Vin = 13.2 V TJ = 150°C 30 20 10 0 TJ = 25°C TJ = −40°C 0 5 10 15 20 25 30 35 40 Vin, INPUT VOLTAGE (V) VEN, ENABLE VOLTAGE (V) Figure 20. Disable Current vs. Input Voltage Figure 21. Enable Current vs. Enable Voltage http://onsemi.com 8 NCV8772 TYPICAL CHARACTERISTICS 4.80 VRT, RESET THRESHOLD (V) 10 tRD, RESET DELAY TIME (ms) Vin = 13.2 V Vin = 13.2 V 4.75 9 4.70 8 4.65 7 4.60 −40 −20 0 20 40 60 80 100 120 140 160 6 −40 −20 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 22. Reset Threshold vs. Temperature Figure 23. Reset Delay Time vs. Temperature Vin Vout < tRR VRT + VRH VRT VRO VROH VROL t t tRD tRR t Figure 24. Reset Function and Timing Diagram http://onsemi.com 9 NCV8772 DEFINITIONS General Current Limit and Short Circuit Current Limit All measurements are performed using short pulse low duty cycle techniques to maintain junction temperature as close as possible to ambient temperature. Output voltage Current Limit is value of output current by which output voltage drops below 96% of its nominal value. Short Circuit Current Limit is output current value measured with output of the regulator shorted to ground. PSRR The output voltage parameter is defined for specific temperature, input voltage and output current values or specified over Line, Load and Temperature ranges. Line Regulation Power Supply Rejection Ratio is defined as ratio of output voltage and input voltage ripple. It is measured in decibels (dB). Line Transient Response The change in output voltage for a change in input voltage measured for specific output current over operating ambient temperature range. Load Regulation Typical output voltage overshoot and undershoot response when the input voltage is excited with a given slope. Load Transient Response The change in output voltage for a change in output current measured for specific input voltage over operating ambient temperature range. Dropout Voltage Typical output voltage overshoot and undershoot response when the output current is excited with a given slope between low−load and high−load conditions. Thermal Protection The input to output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. It is measured when the output drops 100 mV below its nominal value. The junction temperature, load current, and minimum input supply requirements affect the dropout level. Quiescent and Disable Currents Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated at typically 175°C, the regulator turns off. This feature is provided to prevent failures from accidental overheating. Maximum Package Power Dissipation Quiescent Current (Iq) is the difference between the input current (measured through the LDO input pin) and the output load current. If Enable pin is set to LOW the regulator reduces its internal bias and shuts off the output, this term is called the disable current (IDIS). The power dissipation level is maximum allowed power dissipation for particular package or power dissipation at which the junction temperature reaches its maximum operating value, whichever is lower. http://onsemi.com 10 NCV8772 APPLICATIONS INFORMATION The NCV8772 regulator is self−protected with internal thermal shutdown and internal current limit. Typical characteristics are shown in Figure 4 to Figure 24. A ceramic or tantalum 0.1 mF capacitor is recommended and should be connected close to the NCV8772 package. Higher capacitance and lower ESR will improve the overall line and load transient response. If extremely fast input voltage transients are expected then appropriate input filter must be used in order to decrease rising and/or falling edges below 50 V/ms for proper operation. The filter can be composed of several capacitors in parallel. Output Decoupling (Cout) Input Decoupling (Cin) RESET DELAY AND RESET THRESHOLD OPTIONS (D2PAK−5) Reset Delay Time NCV87721D5S NCV87722D5S NCV87723D5S NCV87724D5S NCV87725D5S NCV8772AD5S NCV8772BD5S NCV8772CD5S NCV8772DD5S NCV8772ED5S NOTE: 8 ms 16 ms 32 ms 64 ms 128 ms 8 ms 16 ms 32 ms 64 ms 128 ms Reset Threshold 93% 93% 93% 93% 93% 90% 90% 90% 90% 90% The NCV8772 is a stable component and does not require a minimum Equivalent Series Resistance (ESR) for the output capacitor. Stability region of ESR vs Output Current is shown in Figure 13. The minimum output decoupling value is 1 mF and can be augmented to fulfill stringent load transient requirements. The regulator works with ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response. The Enable pin will turn the regulator on or off. The threshold limits are covered in the electrical characteristics table in this datasheet. The timing values can be selected from the following list: 8, 16, 32, 64, 128 ms. Contact factory for options not included in ORDERING INFORMATION table on page 12. Reset Delay Time Select (D2PAK−7 only) Enable Operation Reset Operation A reset signal is provided on the Reset Output (RO) pin to provide feedback to the microprocessor of an out of regulation condition. The timing diagram of reset function is shown in Figure 24. This is in the form of a logic signal on RO. Output voltage conditions below the RESET threshold cause RO to go low. The RO integrity is maintained down to Vout = 1.0 V. For 5 V voltage option, the Reset Output (RO) circuitry includes internal pull−up (30 kW) connected to the output (Vout) No external pull−up is necessary. Selection of the NCV8772yD7S devices and the state of the DT pin determines the available Reset Delay times. The part is designed for use with DT tied to ground or Vout, but may be controlled by any logic signal which provides a threshold between 0.8 V and 2 V. The default condition for an open DT pin is the slower Reset time (DT = GND condition). Times are in pairs and are highlighted in the chart below. Consult factory for availability. The Delay Time select (DT) pin is logic level controlled and provides Reset Delay time per the chart. Note the DT pin is sampled only when RO is low, and changes to the DT pin when RO is high will not effect the reset delay time. http://onsemi.com 11 NCV8772 RESET DELAY AND RESET THRESHOLD OPTIONS (D2PAK−7) DT = GND Reset Time NCV87721D7S NCV87722D7S NCV87723D7S NCV87724D7S NCV87725D7S NCV8772AD7S NCV8772BD7S NCV8772CD7S NCV8772DD7S NCV8772ED7S NOTE: 8 ms 8 ms 16 ms 32 ms 4 ms 8 ms 8 ms 16 ms 32 ms 4 ms DT = Vout Reset Time 128 ms 32 ms 64 ms 128 ms 8 ms 128 ms 32 ms 64 ms 128 ms 8 ms Reset Threshold 93% 93% 93% 93% 93% 90% 90% 90% 90% 90% NOTE: 100 90 80 70 60 50 40 0 PCB 1 oz Cu dissipate up to 2.35 W (for D2PAK−5) when the ambient temperature (TA) is 25°C. See Figure 25 for RqJA versus PCB area. The power dissipated by the NCV8772 can be calculated from the following equations: P D + V in I q@I out ) I out V in * V out (eq. 2) or V in(max) + P D(max) ) V out I out ) I q I out (eq. 3) Items containing Iq can be neglected if Iout >> Iq. The timing values can be selected from the following list: 4, 8, 16, 32, 64, 128 ms. Contact factory for other timing combinations not included in this table or in ORDERING INFORMATION table on page 12. Thermal Considerations RqJA, THERMAL RESISTANCE (°C/W) As power in the NCV8772 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. When the NCV8772 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power applications. The maximum dissipation the NCV8772 can handle is given by: P D(max) + T J(max) * T A R qJA (eq. 1) PCB 2 oz Cu 100 200 300 400 500 600 COPPER HEAT SPREADER (mm2) 700 Figure 25. Thermal Resistance vs. PCB Copper Area (D2PAK−5) Hints Since TJ is not recommended to exceed 150°C, then the NCV8772 soldered on 645 mm2, 1 oz copper area, FR4 can Vin and GND printed circuit board traces should be as wide as possible. When the impedance of these traces is high, there is a chance to pick up noise or cause the regulator to malfunction. Place external components, especially the output capacitor, as close as possible to the NCV8772 and make traces as short as possible. ORDERING INFORMATION Reset Delay Time (DT = GND/Vout for D2PAK−7) 8 ms 4/8 ms Device NCV87721D5S50R4G NCV87725D7S50R4G Output Voltage 5.0 V 5.0 V Reset Threshold 93% 93% Marking NC V8772150 NC V8772550 Package D2PAK−5 (Pb−Free) D2PAK−7 (Pb−Free) Shipping† 800 / Tape & Reel 750 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 12 NCV8772 PACKAGE DIMENSIONS D2PAK 5 CASE 936A−02 ISSUE C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A AND K. 4. DIMENSIONS U AND V ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 6. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAXIMUM. INCHES MIN MAX 0.386 0.403 0.356 0.368 0.170 0.180 0.026 0.036 0.045 0.055 0.067 BSC 0.539 0.579 0.050 REF 0.000 0.010 0.088 0.102 0.018 0.026 0.058 0.078 5 _ REF 0.116 REF 0.200 MIN 0.250 MIN MILLIMETERS MIN MAX 9.804 10.236 9.042 9.347 4.318 4.572 0.660 0.914 1.143 1.397 1.702 BSC 13.691 14.707 1.270 REF 0.000 0.254 2.235 2.591 0.457 0.660 1.473 1.981 5 _ REF 2.946 REF 5.080 MIN 6.350 MIN −T− A K B 12345 OPTIONAL CHAMFER TERMINAL 6 E V U S H M L D 0.010 (0.254) M T N G R P C SOLDERING FOOTPRINT* 8.38 0.33 1.702 0.067 10.66 0.42 DIM A B C D E G H K L M N P R S U V 16.02 0.63 3.05 0.12 1.016 0.04 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 13 NCV8772 PACKAGE DIMENSIONS D2PAK−7 (SHORT LEAD) CASE 936AB−01 ISSUE B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A AND K. 4. DIMENSIONS U AND V ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 6. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAXIMUM. INCHES MIN MAX 0.386 0.403 0.356 0.368 0.170 0.180 0.026 0.036 0.045 0.055 0.067 BSC 0.539 0.579 0.050 REF 0.000 0.010 0.088 0.102 0.018 0.026 0.058 0.078 5 _ REF 0.116 REF 0.200 MIN 0.250 MIN MILLIMETERS MIN MAX 9.804 10.236 9.042 9.347 4.318 4.572 0.660 0.914 1.143 1.397 1.702 BSC 13.691 14.707 1.270 REF 0.000 0.254 2.235 2.591 0.457 0.660 1.473 1.981 5 _ REF 2.946 REF 5.080 MIN 6.350 MIN −T− A K B 12345 OPTIONAL CHAMFER TERMINAL 6 E V U S H M L D 0.010 (0.254) M T N G R P C RECOMMENDED SOLDERING FOOTPRINT* 0.424 DIM A B C D E G H K L M N P R S U V 0.310 0.584 0.136 7X 0.040 0.050 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 14 NCV8772/D