NCV8775C
Ultra Low Iq 350 mA LDO
Regulator with Reset
The NCV8775C is 350 mA LDO regulator with integrated reset
functions dedicated for microprocessor applications. Its robustness allows
NCV8775C to be used in severe automotive environments. Ultra low
quiescent current as low as 19 mA typical makes it suitable for
applications permanently connected to battery requiring ultra low
quiescent current with or without load. This feature is especially critical
when modules remain in active mode when ignition is off. The
NCV8775C contains protection functions as current limit, thermal
shutdown.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
•
•
Output Voltage Options: 3.3 V and 5 V
Output Voltage Accuracy: ±2%
Output Current up to 350 mA
Ultra Low Quiescent Current: typ 19 mA (max 28 mA)
Very Wide Range of Cout and ESR Values for Stability
Microprocessor Compatible Control Functions:
− Reset with Adjustable Delay
Wide Input Voltage Operation Range: up to 40 V
Protection Features
− Current Limitation
− Thermal Shutdown
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100 Grade 1
Qualified and PPAP Capable
EMC Compliant
These are Pb−Free Devices
xx
A
WL, L
Y
WW
G or G
DPAK−5
DT SUFFIX
CASE 175AA
775CxxG
ALYWW
D2PAK−5
D5S SUFFIX
CASE 936A
NC
V8775Cxx
AWLYWWG
= 50 (5.0 V Version)
= 33 (3.3 V Version)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Typical Applications
•
•
•
•
Body Control Module
Instruments and Clusters
Occupant Protection and Comfort
Powertrain
VBAT
Cin
0.1 mF
CD
47 nF
Vin
Vout
NCV8775C
D
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
Vout
VDD
Cout
10 mF
RO
RRO
5 kW
Microprocessor
RESET
GND
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2017
December, 2019 − Rev. 1
1
Publication Order Number:
NCV8775C/D
NCV8775C
Vout
Vin
Thermal
Shutdown
RO
Driver
With
Current
Limit
Error Amplifier
Reset Driver
Reset Comparator
Reference
Delay
Timer
GND
Figure 2. Simplified Block Diagram
PIN CONNECTIONS
PIN
Tab,
1. Vin
2. RO
3. GND
4. D
5. Vout
PIN
Tab,
1
1
D2PAK−5
DPAK−5
Figure 3. Pin Connections
PIN FUNCTION DESCRIPTION
Pin No.
DPAK−5
D2PAK−5
Pin Name
1
Vin
Positive Power Supply Input. Connect 0.1 mF capacitor to ground.
2
RO
Reset (Open Collector) Output. External Pull−up resistor connected to Vout.
3, TAB
GND
4
D
5
Vout
Description
Power Supply Ground. Pin 3 internally connected to tab.
Reset Delay. Timing capacitor to GND for Reset Delay function.
Regulated Output Voltage. Connect 10 mF capacitor with ESR < 5 W to ground.
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2
1. Vin
2. RO
3. GND
4. D
5. Vout
D
NCV8775C
ABSOLUTE MAXIMUM RATINGS
Symbol
Min
Max
Unit
Input Voltage (Note 1)
Rating
DC
Vin
−0.3
40
V
Input Voltage (Note 2)
Load Dump − Suppressed
Us *
−
45
V
Output Voltage
Vout
−0.3
7
V
Reset Delay Voltage
VD
−0.3
7
V
Reset Output Voltage
VRO
−0.3
7
V
Junction Temperature
TJ
−40
150
°C
Storage Temperature
TSTG
−55
150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class A according to ISO16750−1.
ESD CAPABILITY (Note 3)
Rating
Symbol
Min
Max
Unit
ESD Capability, Human Body Model
ESDHBM
−4
4
kV
ESD Capability, Charged Device Model
ESDCDM
−1
1
kV
3. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (JS−001−2017)
Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes 2 x 2 mm due to
the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current waveform
characteristic defined in JEDEC JS−002−2018.
LEAD SOLDERING TEMPERATURE AND MSL (Note 4)
Rating
Moisture Sensitivity Level
Symbol
DPAK−5
D2PAK−5
Min
MSL
Max
1
1
Unit
−
4. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
THERMAL CHARACTERISTICS (Note 5)
Rating
Symbol
Value
Thermal Characteristics, DPAK−5
Thermal Resistance, Junction−to−Air (Note 6)
Thermal Reference, Junction−to−Lead (Note 6)
Thermal Resistance, Junction−to−Air (Note 7)
Thermal Reference, Junction−to−Lead (Note 7)
RθJA
RψJL1
RθJA
RψJL1
53.5
8.2
23.9
7.4
Thermal Characteristics, D2PAK−5
Thermal Resistance, Junction−to−Air (Note 6)
Thermal Reference, Junction−to−Lead (Note 6)
Thermal Resistance, Junction−to−Air (Note 7)
Thermal Reference, Junction−to−Lead (Note 7)
RθJA
RψJL1
RθJA
RψJL1
53.3
7.6
23.7
6.9
Unit
°C/W
°C/W
5. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
6. Values based on 1s0p board with copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. Single layer − according
to JEDEC51.3.
7. Values based on 2s2p board with copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness for inner layers, 2 oz copper thickness for signal
layers and FR4 PCB substrate. 4 layers − according to JEDEC51.7.
RECOMMENDED OPERATING RANGE (Note 8)
Rating
Symbol
Min
Max
Unit
Input Voltage (Note 9)
Vin
4.5
40
V
Junction Temperature
TJ
−40
150
°C
8. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
9. Minimum Vin = 4.5 V or (Vout + VDO), whichever is higher.
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3
NCV8775C
ELECTRICAL CHARACTERISTICS Vin = 13.5 V, Cin = 0.1 mF, Cout = 10 mF, Min and Max values are valid for temperature range
−40°C ≤ TJ ≤ 150°C unless noted otherwise and are guaranteed by test, design or statistical correlation. Typical values are referenced to
TJ = 25°C (Notes 10 and 11)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
3.234
3.234
4.9
4.9
3.3
3.3
5.0
5.0
3.366
3.366
5.1
5.1
Regline
−20
0
20
mV
Regload
−35
10
35
mV
−
−
200
350
350
600
−
−
19
−
27
28
REGULATOR OUTPUT
Output Voltage (Accuracy %)
Vout
3.3 V Vin = 4.5 V to 40 V, Iout = 0.1 mA to 200 mA
Vin = 4.5 V to 16 V, Iout = 0.1 mA to 350 mA
5.0 V Vin = 5.6 V to 40 V, Iout = 0.1 mA to 200 mA
Vin = 5.975 V to 16 V, Iout = 0.1 mA to 350 mA
Line Regulation
V
3.3 V Vin = 4.5 V to 28 V, Iout = 5 mA
5.0 V Vin = 6 V to 28 V, Iout = 5 mA
Load Regulation
Iout = 0.1 mA to 350 mA
Dropout Voltage (Note 12)
VDO
5.0 V Iout = 200 mA
Iout = 350 mA
mV
QUIESCENT CURRENT
Quiescent Current (Iq = Iin − Iout)
mA
Iq
Iout = 0.1 mA, TJ = 25°C
Iout = 0.1 mA, TJ ≤ 125°C
CURRENT LIMIT PROTECTION
Current Limit
Vout = 0.96 x Vout_nom
ILIM
500
−
1100
mA
Short Circuit Current Limit
Vout = 0 V
ISC
500
−
1100
mA
PSRR
−
80
−
dB
ID
2.0
4.0
6.5
mA
VDU
1.2
1.3
1.4
V
tRD
10
16
22
ms
PSRR
Power Supply Ripple Rejection (Note 13) f = 100 Hz, 0.5 Vpp
D (RESET DELAY)
Reset Charging Current
VD = 1.0 V
Upper Timing Threshold
Reset Delay Time
CD = 47 nF
Reset Reaction Time
tRR
ms
6.0
RESET OUTPUT RO
Input Voltage Reset Threshold
Vin decreasing, Vout > VRT
Vin_RT
3.3 V
V
−
3.8
4.2
VRT
90
93
96
%Vout
VRH
−
2.0
−
%Vout
VROL
−
0.2
0.4
V
IROLK
−
−
5
mA
Thermal Shutdown Temperature
(Note 13)
TSD
150
175
195
°C
Thermal Shutdown Hysteresis
(Note 13)
TSH
−
10
−
°C
Output Voltage Reset Threshold
Vout decreasing
Reset Hysteresis
Reset Output Low Voltage
Vout > 1 V, RRO > 5 kW
Reset High Level Leakage Current
THERMAL SHUTDOWN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
11. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [ TJ. Low duty
cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
12. Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.5 V.
13. Values based on design and/or characterization.
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4
NCV8775C
TYPICAL CHARACTERISTICS
30
Vin = 13.5 V
Iout = 100 mA
Vout(nom) = 5.0 V
28
26
Iq, QUIESCENT CURRENT (mA)
Iq, QUIESCENT CURRENT (mA)
30
24
22
20
18
16
14
12
0
20
40
60
80
26
24
22
20
18
16
14
12
10
−40 −20
10
−40 −20
Vin = 13.5 V
Iout = 100 mA
Vout(nom) = 3.3 V
28
100 120 140 160
TJ, JUNCTION TEMPERATURE (°C)
20
40
60
80
100 120 140 160
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. Quiescent Current vs. Junction
Temperature
Figure 5. Quiescent Current vs. Junction
Temperature
800
800
Iq, QUIESCENT CURRENT (mA)
600
Iq, QUIESCENT CURRENT (mA)
Iout = 100 mA
TJ = 25°C
Vout(nom) = 5.0 V
700
500
400
300
200
100
0
Iout = 100 mA
TJ = 25°C
Vout(nom) = 3.3 V
700
600
500
400
300
200
100
0
0
4
8
12
16
20
24
28
32
36
40
0
4
8
Vin, INPUT VOLTAGE (V)
20
24
28
32
36
40
Iq, QUIESCENT CURRENT (mA)
1200
Vin = 13.5 V
Vout(nom) = 5.0 V
TJ = −40°C
TJ = 25°C
800
TJ = 150°C
600
400
200
0
0
16
Figure 7. Quiescent Current vs. Input Voltage
1200
1000
12
Vin, INPUT VOLTAGE (V)
Figure 6. Quiescent Current vs. Input Voltage
Iq, QUIESCENT CURRENT (mA)
0
Vin = 13.5 V
Vout(nom) = 3.3 V
1000
TJ = −40°C
TJ = 25°C
800
600
TJ = 150°C
400
200
0
50
100
150
200
250
300
IOUT, OUTPUT CURRENT (mA)
0
350
Figure 8. Quiescent Current vs. Output Current
50
100
150
200
250
Iout, OUTPUT CURRENT (mA)
300
350
Figure 9. Quiescent Current vs. Output Current
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5
NCV8775C
TYPICAL CHARACTERISTICS
3.38
5.10
Vin = 13.5 V
Iout = 100 mA
Vout(nom) = 5.0 V
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
−40 −20
0
20
Vin = 13.5 V
Iout = 100 mA
Vout(nom) = 3.3 V
3.36
Vout, OUTPUT VOLTAGE (V)
Vout, OUTPUT VOLTAGE (V)
5.08
40
60
80
3.34
3.32
3.30
3.28
3.26
3.24
3.22
−40 −20
100 120 140 160
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Output Voltage vs. Junction
Temperature
Figure 11. Output Voltage vs. Junction
Temperature
4
Iout = 100 mA
Vout(nom) = 5.0 V
5
Vout, OUTPUT VOLTAGE (V)
Vout, OUTPUT VOLTAGE (V)
6
4
3
TJ = 25°C
2
TJ = −40°C
1
TJ = 150°C
Iout = 100 mA
Vout(nom) = 3.3 V
3.5
3
2.5
2
TJ = 25°C
1.5
TJ = −40°C
1
TJ = 150°C
0.5
0
0
0
1
2
3
4
5
6
Vin, INPUT VOLTAGE (V)
7
0
8
1
2
3
4
5
6
7
8
Vin, INPUT VOLTAGE (V)
Figure 12. Output Voltage vs. Input Voltage
Figure 13. Output Voltage vs. Input Voltage
700
700
Vin = 13.5 V
Vout(nom) = 5.0 V
600
VDO, DROPOUT VOLTAGE (mV)
VDO, DROPOUT VOLTAGE (mV)
0
20 40 60 80 100 120 140 160
TJ, JUNCTION TEMPERATURE (°C)
500
400
TJ = 25°C
300
TJ = 150°C
200
TJ = −40°C
100
0
0
50
100
150
200
250
Iout, OUTPUT CURRENT (mA)
300
600
Vin = 13.5 V
Vout(nom) = 5.0 V
500
Iout = 350 mA
400
300
Iout = 200 mA
200
100
0
−40 −20
350
Figure 14. Dropout Voltage vs. Output Current
0
20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. Dropout Voltage vs. Junction
Temperature
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6
160
NCV8775C
TYPICAL CHARACTERISTICS
ILIM ISC, CURRENT LIMIT (mA)
ILIM ISC, CURRENT LIMIT (mA)
1000
ISC @ Vout = 0 V
800
600
ILIM @ Vout = 4.8 V
400
200
TJ = 25°C
Vout(nom) = 5.0 V
0
0
5
10
15
20
25
30
35
600
400
200
TJ = 25°C
Vout(nom) = 3.3 V
5
10
15
20
25
30
35
Vin, INPUT VOLTAGE (V)
Vin, INPUT VOLTAGE (V)
Figure 17. Output Current Limit vs. Input
Voltage
40
1100
Vin = 13.5 V
Vout(nom) = 5.0 V
ILIM ISC, CURRENT LIMIT (mA)
ILIM ISC, CURRENT LIMIT (mA)
ILIM @ Vout = 3.168 V
Figure 16. Output Current Limit vs. Input
Voltage
900
800
ISC @ Vout = 0 V
700
ILIM @ Vout = 4.8 V
600
500
400
−40 −20
Vin = 13.5 V
Vout(nom) = 3.3 V
1000
900
ISC @ Vout = 0 V
800
ILIM @ Vout = 3.168 V
700
600
500
400
0
20
40
60
80
−40 −20
100 120 140 160
0
20
40
60
80
100 120 140 160
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 18. Output Current Limit vs. Junction
Temperature
Figure 19. Output Current Limit vs. Junction
Temperature
100
100
Unstable Region
10
Unstable Region
10
Stable Region
ESR (W)
ESR (W)
ISC @ Vout = 0 V
800
0
0
40
1100
1000
1000
1
0.1
0.1
Vin = 13.5 V
Vout(nom) = 5.0 V
Cout = 1.0 mF − 100 mF
0.01
0
50
100
150
200
250
300
Stable Region
1
Vin = 13.5 V
Vout(nom) = 3.3 V
Cout = 1.0 mF − 100 mF
0.01
0
350
50
100
150
200
250
300
Iout, OUTPUT CURRENT (mA)
Iout, OUTPUT CURRENT (mA)
Figure 20. Output Stability with Output
Capacitor ESR
Figure 21. Output Stability with Output
Capacitor ESR
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7
350
NCV8775C
TYPICAL CHARACTERISTICS
Vin = 13.5 V
Vout(nom) = 5.0 V
4.75
4.7
4.65
4.6
4.55
3.17
VRT, RESET THRESHOLD (V)
VRT, RESET THRESHOLD (V)
4.8
4.5
Vin = 13.5 V
Vout(nom) = 3.3 V
3.13
3.09
3.05
3.01
2.97
−40 −20
−40 −20
0
20
40
60 80 100 120 140 160
TJ, JUNCTION TEMPERATURE (°C)
0
20
40
60
80
100 120 140 160
TJ, JUNCTION TEMPERATURE (°C)
Figure 22. Reset Threshold vs. Junction
Temperature
Figure 23. Reset Threshold vs. Junction
Temperature
Vin_RT, INPUT VOLTAGE RESET
THRESHOLD (V)
4.2
Vin = 13.5 V
Vout(nom) = 3.3 V
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
−40 −20
0
20 40 60 80 100 120 140 160
TJ, JUNCTION TEMPERATURE (°C)
Figure 24. Input Voltage Reset Threshold vs.
Junction Temperature
22
Vin = 13.5 V
CD = 47 nF
Vout(nom) = 5.0 V
20
tRD, RESET DELAY TIME (ms)
tRD, RESET DELAY TIME (ms)
22
18
16
14
12
10
−40 −20
0
20
40
60
80
Vin = 13.5 V
CD = 47 nF
Vout(nom) = 3.3 V
20
18
16
14
12
10
−40 −20
100 120 140 160
0
20
40
60
80
100 120 140 160
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. Reset Delay Time vs. Junction
Temperature
Figure 26. Reset Delay Time vs. Junction
Temperature
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NCV8775C
TYPICAL CHARACTERISTICS
120
Iout = 100 mA
80
PSRR (dB)
NOISE DENSITY (nV/√Hz)
100
60
40
Iout = 100 mA
20
0
Vin = 13.5 V ± 0.5 VPP
Cout = 1 mF
Vout(nom) = 5.0 V
10
100
1000
10000
100000
f, FREQUENCY (Hz)
1000000
6000
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
0
f = 10 Hz − 100 kHz
Vn = 268 mV
Vin = 13.5 V
Cout = 1 mF
Iout = 100 mA
Vout(nom) = 5.0 V
10
Figure 27. PSRR vs. Frequency
28 V
Vin
(10 V/div)
1000
10000
f, FREQUENCY (Hz)
350 mA
Iout
(200 mA/div)
TJ = 25°C
Vin = 13.5 V
Cout = 10 mF
trise/fall = 1 ms (Iout)
0.1 mA
5.17 V
Vout
(200 mV/div)
5.012 V
Vout
(20 mV/div)
4.995 V
TIME (400 ms/div)
TIME (100 ms/div)
Figure 29. Line Transients
Vin
(5 V/div)
13.5 V
Figure 30. Load Transients
TJ = 25°C
Iout = 100 mA
Cout = 10 mF
CD = 47 nF
trise/fall = 1 s (Vin)
0V
Vout
(5 V/div)
VRO
(5 V/div)
5V
4.78 V
5V
100000
Figure 28. Noise vs. Frequency
TJ = 25°C
Iout = 100 mA
Cout = 10 mF
trise/fall = 1 ms (Vin)
6V
100
0V
0V
TIME (400 ms/div)
Figure 31. Power Up/Down Response
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9
NCV8775C
V in
t
V out
< t RR
> t RR
V RT + V RH
V RT
t
V RO
tRR
tRR
V ROL
VD
t
tRD
tRD
VDU
Figure 32. Reset Function and Timing Diagram
t
DEFINITIONS
General
Current Limit and Short Circuit Current Limit
All measurements are performed using short pulse low
duty cycle techniques to maintain junction temperature as
close as possible to ambient temperature.
Current Limit is value of output current by which output
voltage drops below 96% of its nominal value. Short Circuit
Current Limit is output current value measured with output
of the regulator shorted to ground.
Output voltage
The output voltage parameter is defined for specific
temperature, input voltage and output current values or
specified over Line, Load and Temperature ranges.
PSRR
Power Supply Rejection Ratio is defined as ratio of output
voltage and input voltage ripple. It is measured in decibels
(dB).
Line Regulation
The change in output voltage for a change in input voltage
measured for specific output current over operating ambient
temperature range.
Line Transient Response
Typical output voltage overshoot and undershoot
response when the input voltage is excited with a given
slope.
Load Regulation
The change in output voltage for a change in output
current measured for specific input voltage over operating
ambient temperature range.
Load Transient Response
Typical output voltage overshoot and undershoot
response when the output current is excited with a given
slope between low−load and high−load conditions.
Dropout Voltage
The input to output differential at which the regulator
output no longer maintains regulation against further
reductions in input voltage. It is measured when the output
drops 100 mV below its nominal value. The junction
temperature, load current, and minimum input supply
requirements affect the dropout level.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 175°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.
Quiescent Current
Maximum Package Power Dissipation
Quiescent Current (Iq) is the difference between the input
current (measured through the LDO input pin) and the
output load current.
The power dissipation level is maximum allowed power
dissipation for particular package or power dissipation at
which the junction temperature reaches its maximum
operating value, whichever is lower.
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10
NCV8775C
APPLICATIONS INFORMATION
The NCV8775C regulator is self−protected with internal
thermal shutdown and internal current limit. Typical
characteristics are shown in Figure 4 to Figure 34.
V DU
t RD + C D
ID
t RD + 47 nF
Input Decoupling (Cin)
A ceramic or tantalum 0.1 mF capacitor is recommended
and should be connected close to the NCV8775C package.
Higher capacitance and lower ESR will improve the overall
line and load transient response.
Input Capacitor is required if regulator is located far from
power supply filter. If extremely fast input voltage transients
are expected with slew rate in excess of 4 V/ms then
appropriate input filter must be used. The filter can be
composed of several capacitors in parallel.
(eq. 1)
1.3 V
4 mA
+ 15.3 ms
Other time delays can be obtained by changing the CD
capacitor value. The Delay Time can be reduced by
decreasing the capacitance of CD. Using the formula above,
Delay can be reduced as desired. For minimum reset delay
time Delay pin must be left open with no PCB trace
connected to the pin.
Thermal Considerations
As power in the NCV8775C increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the NCV8775C has good thermal conductivity through the
PCB, the junction temperature will be relatively low with
high power applications. The maximum dissipation the
NCV8775C can handle is given by:
Output Decoupling (Cout)
The NCV8775C is a stable component and does not
require a minimum Equivalent Series Resistance (ESR) for
the output capacitor. Stability region of ESR vs Output
Current is shown in Figures 20 and 21. The minimum output
decoupling value is 1 mF and can be augmented to fulfill
stringent load transient requirements. The regulator works
with ceramic chip capacitors as well as tantalum devices.
Larger values improve noise rejection and load regulation
transient response.
P D(max) +
Reset Operation
A reset signal is provided on the Reset Output (RO) pin to
provide feedback to the microprocessor of an out of
regulation condition. The timing diagram of reset function
is shown in Figure 32. This is in the form of a logic signal on
RO. Output voltage conditions below the Reset threshold
cause RO to go low. RO is pulled up to Vout by an external
resistor, typically 5.0 kW in value. Output voltage regulation
must be maintained for the delay time before the reset output
signals a valid condition. The delay for the reset output is
defined as the amount of time it takes the timing capacitor
on the delay pin to charge from a residual voltage of 0 V to
the upper timing threshold voltage VDU of 1.3 V. The
charging current for this is ID of 4 mA and D pin voltage in
steady state is typically 0 V. By using typical IC parameters
with a 47 nF capacitor on the D Pin, the following time delay
is derived:
ƪTJ(max) * TAƫ
(eq. 2)
R qJA
Since TJ is not recommended to exceed 150°C, then the
NCV8775C soldered on 645 mm2, 1 oz copper area, FR4
can dissipate up to 2.35 W (for D2PAK−5) when the ambient
temperature (TA) is 25°C. See Figures 33 and 34 for RqJA
versus PCB area. The power dissipated by the NCV8775C
can be calculated from the following equations:
P D + V inǒI q@I outǓ ) I outǒV in * V outǓ
(eq. 3)
or
V in(max) +
NOTE:
www.onsemi.com
11
P D(max) ) ǒV out
I outǓ
I out ) I q
Items containing Iq can be neglected if Iout >> Iq.
(eq. 4)
NCV8775C
100
RqJA, THERMAL RESISTANCE
(°C/W)
110
100
RqJA, THERMAL RESISTANCE
(°C/W)
110
90
80
70
1 oz, Single Layer
60
50
2 oz, Single Layer
40
30
20
1 oz, 4 Layer
10
0
90
80
70
1 oz, Single Layer
60
50
2 oz, Single Layer
40
30
20
1 oz, 4 Layer
10
0
0
200
400
600
800
1000
COPPER HEAT SPREADER AREA (mm2)
200
400
600
800
COPPER HEAT SPREADER AREA (mm2)
Figure 33. Thermal Resistance vs. PCB Copper
Area (DPAK−5)
Figure 34. Thermal Resistance vs. PCB Copper
Area (D2PAK−5)
Hints
0
1000
The NCV8775C is not developed in compliance with
ISO26262 standard. If application is safety critical then the
above application example diagram shown in Figure 35 can
be used.
Vin and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator
to malfunction. Place external filter components, especially
the output capacitor, as near as possible to the device to
increase EMC performance.
Vout
VBAT
Vin
Vout
VDD
Cout
Cin
VCC
RESET
Voltage
Supervisor
NCV8775C
I/O
Microprocessor
(e.g. NCV30X, NCV809)
GND
D
CD
I/O
RO
GND
Figure 35. NCV8775C Application Diagram
ORDERING INFORMATION
Output Voltage
Package
Shipping†
NCV8775CDT33RKG
3.3 V
DPAK−5
(Pb−Free)
2500 / Tape & Reel
NCV8775CDT50RKG
5.0 V
DPAK−5
(Pb−Free)
2500 / Tape & Reel
NCV8775CDS33R4G
3.3 V
D2PAK−5
(Pb−Free)
800 / Tape & Reel
NCV8775CDS50R4G
5.0 V
D2PAK−5
(Pb−Free)
800 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK−5, CENTER LEAD CROP
CASE 175AA
ISSUE B
DATE 15 MAY 2014
SCALE 1:1
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
R1
Z
A
S
12 3 4 5
U
K
F
J
L
H
D
G
5 PL
0.13 (0.005)
M
T
2.2
0.086
0.34 5.36
0.013 0.217
5.8
0.228
10.6
0.417
0.8
0.031
SCALE 4:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12855D
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.020 0.028
0.018 0.023
0.024 0.032
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.045 BSC
0.170 0.190
0.185 0.210
0.025 0.040
0.020
−−−
0.035 0.050
0.155 0.170
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.51
0.71
0.46
0.58
0.61
0.81
4.56 BSC
0.87
1.01
0.46
0.58
2.60
2.89
1.14 BSC
4.32
4.83
4.70
5.33
0.63
1.01
0.51
−−−
0.89
1.27
3.93
4.32
GENERIC
MARKING DIAGRAMS*
RECOMMENDED
SOLDERING FOOTPRINT*
6.4
0.252
DIM
A
B
C
D
E
F
G
H
J
K
L
R
R1
S
U
V
Z
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DPAK−5 CENTER LEAD CROP
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK 5−LEAD
CASE 936A−02
ISSUE E
DATE 28 JUL 2021
SCALE 1:1
GENERIC
MARKING DIAGRAM*
xx
xxxxxxxxx
AWLYWWG
xxxxxx
A
WL
Y
WW
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH01006A
D2PAK 5−LEAD
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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