NCV8842DR2G

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The device uses the V2t control architecture to provide unmatched transient response, the best overall regulation and the simplest loop compensation for today’s high−speed logic. The NCV8842 accommodates input voltages from 4.0 V to 40 V and contains synchronization circuitry. The on−chip NPN transistor is capable of providing a minimum of 1.5 A of output current, and is biased by an external “boost” capacitor to ensure saturation, thus minimizing on−chip power dissipation. Protection circuitry includes thermal shutdown, cycle−by−cycle current limiting and frequency foldback. http://onsemi.com MARKING DIAGRAMS 16 SO−16W EP PW SUFFIX CASE 751AG 16 1 Features • • • • • • • • • • • • • NCV8842 AWLYYWWG 1 V2 Architecture Provides Ultra−Fast Transient Response, Improved Regulation and Simplified Design Wide Operating Range: 4 V to 40 V 2.0% Error Amp Reference Voltage Tolerance Switch Frequency Decrease of 4:1 in Short Circuit Conditions Reduces Short Circuit Power Dissipation BOOST Lead Allows “Bootstrapped” Operation to Maximize Efficiency Sync Function for Parallel Supply Operation or Noise Minimization Shutdown Lead Provides Power−Down Option 1.0 mA Quiescent Current During Power−Down Thermal Shutdown Soft−Start Exposed Pad Packages for Enhanced Thermal Characteristics NCV Prefix for Automotive and Other Applications Requiring Site and Change Controls These are Pb−Free Devices 1 18 1 18−LEAD DFN MN SUFFIX CASE 505 18 NCV8842 AWLYYWW G G 8 8 1 SOIC−8 D SUFFIX CASE 751 1 V8842 ALYWE G A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week E = Automotive Grade G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. © Semiconductor Components Industries, LLC, 2011 July, 2011 − Rev. 10 1 Publication Order Number: NCV8842/D NCV8842 R6 100k D1 Vout (3.3 V) C3 100 mF R3 162 + C1 0.1 mF U1 Vsw SHDNB NC NC NC NC SYNC GND D2 EPAD L1 27 mH Vin (7 V to 16 V) Vin BOOST NC NC NC NC Vc Vfb C5 0.1 mF + C2 NCV8842 330 mF C4 0.1 mF R2 100 SHDNB SYNC Figure 1. Application Diagram, 7 V − 16 V to 3.3 V @ 1.0 A Converter MAXIMUM RATINGS* Rating Value Unit 45 V −40 to 150 °C 260 peak (Note 2) °C −65 to +150 °C (Human Body Model) (Machine Model) (Charge Device Model) 2.0 200 >1.0 kV V kV SO−16W EPAD Junction−to−Case, RqJC SO−16W EPAD Junction−to−Ambient, RqJA (Note 3) DFN−18 Junction−to−Ambient, RqJA (Note 3) SO−8 Junction−to−Ambient, RqJA (Note 4) 16 35 38 100 °C/W °C/W °C/W °C/W Peak Transient Voltage (31 V Load Dump @ VIN = 14 V) Operating Junction Temperature Range, TJ Lead Temperature Soldering: Reflow: (Note 1) Storage Temperature Range, TS ESD Package Thermal Resistance Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *The maximum package power dissipation must be observed. 1. 60 second maximum above 183°C. 2. −5°C/0°C allowable conditions. 3. 4 layer board, 1 oz copper outer layers, 0.5 oz copper inner layers, 600 sqmm copper area 4. 1 in2, 1 oz copper area used for heatsinking. MAXIMUM RATINGS (Voltages are with respect to GND) Pin Name VMax VMIN ISOURCE ISINK VIN (DC)* 40 V −0.3 V N/A 4.0 A BOOST 40 V −0.3 V N/A 100 mA VSW 40 V −0.6 V/−1.0 V, t < 50 ns 4.0 A 10 mA VC 7.0 V −0.3 V 1.0 mA 1.0 mA SHDNB 7.0 V −0.3 V 1.0 mA 1.0 mA SYNC 7.0 V −0.3 V 1.0 mA 1.0 mA VFB 7.0 V −0.3 V 1.0 mA 1.0 mA *See table above for load dump. http://onsemi.com 2 NCV8842 PACKAGE PIN DESCRIPTION SO−8 SO−16W EPAD DFN−18 PIN SYMBOL 1 15 1 BOOST 2 16 2−4 VIN This pin is the main power input to the IC. 3 1 5−7 VSW This is the connection to the emitter of the on−chip NPN power transistor and serves as the switch output to the inductor. This pin may be subjected to negative voltages during switch off−time. A catch diode is required to clamp the pin voltage in normal operation. This node can stand −1.0 V for less than 50 ns during switch node flyback. 4 2 8 SHDNB The shutdown pin is active low and TTL compatible. The IC goes into sleep mode, drawing less than 1.0 mA when the pin voltage is pulled below 1.0 V. This pin should be pulled up to VCC with a resistor. 5 7 10 6 8 7 FUNCTION The BOOST pin provides additional drive voltage to the on−chip NPN power transistor. The resulting decrease in switch on voltage increases efficiency. SYNC External synchronization single input, with 60k internal pull−down resistor. If not used, leave unconnected or connect to GND. 13 GND Power return connection for the IC. 9 16 VFB The FB pin provides input to the inverting input of the error amplifier. If VFB is lower than 0.29 V, the oscillator frequency is divided by four, and current limit folds back to about 1 ampere. These features protect the IC under severe overcurrent or short circuit conditions. 8 10 17 VC The VC pin provides a connection point to the output of the error amplifier and input to the PWM comparator. Driving of this pin should be avoided because on− chip test circuitry becomes active whenever current exceeding 0.5 mA is forced into the IC. − 3 − 6, 11 − 14 9, 11, 12, 14, 15, 18 NC No Connection − EPAD EPAD − Exposed die attach pad. Internally connected to GND. External connection to GND is optional. PIN CONNECTIONS 1 16 VSW 1 8 SHDNB VIN BOOST VC NC NC VIN VFB NC NC VSW GND NC NC SYNC NC NC SYNC VC GND VFB BOOST SHDNB SO−8 SO−16W EPAD http://onsemi.com 3 BOOST VIN VIN VIN VSW VSW VSW SHDNB NC 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 DFN−18 NC VC VFB NC NC GND NC NC SYNC NCV8842 ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 4.5 V< VIN < 40 V; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Oscillator Operating Frequency − 153 170 187 kHz Frequency Line Regulation − − 0.05 0.15 %/V Maximum Duty Cycle − 85 90 95 % VFB Frequency Foldback Threshold − 0.29 0.32 0.36 V 5.0 9.0 17 mV/ms − 100 200 ns PWM Comparator Slope Compensation Voltage Fix VFB, DVC/DTON Minimum Output Pulse Width VFB to VSW Power Switch Current Limit VFB > 0.36 V 1.6 2.3 3.0 A Foldback Current VFB < 0.29 V 0.9 1.5 2.1 A Saturation Voltage IOUT = 1.5 A, VBOOST = VIN + 2.5 V 0.4 0.7 1.0 V Current Limit Delay (Note 5) − 120 160 ns 1.244 1.270 1.296 V − 40 − dB − 0.02 0.1 mA Error Amplifier Internal Reference Voltage Reference PSRR − (Note 5) FB Input Bias Current − Output Source Current VC = 1.270 V, VFB = 1.0 V 15 25 35 mA Output Sink Current VC = 1.270 V, VFB = 2.0 V 15 25 35 mA Output High Voltage VFB = 1.0 V 1.39 1.46 1.53 V Output Low Voltage VFB = 2.0 V 5.0 20 60 mV Unity Gain Bandwidth (Note 5) − 500 − kHz Open Loop Amplifier Gain (Note 5) − 70 − dB Amplifier Transconductance (Note 5) − 6.4 − mA/V 190 − 355 kHz − 360 485 mA − 0.9 1.5 1.9 V − 1.0 1.3 1.6 V − 4.0 − mA Sync Sync Frequency Range Sync Pin Bias Current − VSYNC = 5.0 V Sync Threshold Voltage Shutdown Shutdown Threshold Voltage SHDNB Input Current Vin = 5.0 V, (Note 5) Thermal Shutdown Overtemperature Trip Point (Note 5) 175 185 195 °C Thermal Shutdown Hysteresis (Note 5) − 42 − °C 5. Guaranteed by design, not 100% tested in production. http://onsemi.com 4 NCV8842 ELECTRICAL CHARACTERISTICS (continued) (−40°C < TJ < 150°C, 4.5 V< VIN < 40 V; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit General Quiescent Current ISW = 0 A − 4.0 7.5 mA Shutdown Quiescent Current VSHDNB = 0 V, −40°C < TJ < 125°C − 1.0 5.0 mA Boost Operating Current VBOOST − VSW = 2.5 V 6.0 15 40 mA/A Minimum Boost Voltage Note 6 − − 2.5 V Startup Voltage − 3.0 3.5 4.0 V Minimum Output Current − − 7.0 12 mA 6. Guaranteed by design, not 100% tested in production. SHDNB SYNC VIN 2.9 V LDO Voltage Regulator 4 mA Shutdown Comparator + Artificial Ramp − Thermal Shutdown Oscillator BOOST + 1.2 V − Internal rail S Q R Output Driver VSW ∑ + Current Limit Comparator − PWM Comparator 1.46 V + SHDNB IREF − − VFB − + + 0.32 V − + 1.27 V + − Frequency and Current Limit Foldback Error Amplifier VC Figure 2. Block Diagram http://onsemi.com 5 IFOLDBACK GND NCV8842 APPLICATIONS INFORMATION THEORY OF OPERATION current of the inductor L1 and the ESR (equivalent series resistor) of the output capacitor C1. The slope compensation signal is a fixed voltage ramp provided by the oscillator. Adding this signal eliminates subharmonic oscillation associated with the operation at duty cycle greater than 50%. The artificial ramp also ensures the proper PWM function when the output ripple voltage is inadequate. The slope compensation signal is properly sized to serve it purposes without sacrificing the transient response speed. Under load and line transient, not only the ramp signal changes, but more significantly the DC component of the feedback voltage varies proportionally to the output voltage. FFB path connects both signals directly to the PWM comparator. This allows instant modulation of the duty cycle to counteract any output voltage deviations. The transient response time is independent of the error amplifier bandwidth. This eliminates the delay associated with error amplifier and greatly improves the transient response time. The error amplifier is used here to ensure excellent DC accuracy. V2 Control The NCV8842 buck regulator provides a high level of integration and high operating frequencies allowing the layout of a switch−mode power supply in a very small board area. This device is based on the proprietary V2 control architecture. V2 control uses the output voltage and its ripple as the ramp signal, providing an ease of use not generally associated with voltage or current mode control. Improved line regulation, load regulation and very fast transient response are also major advantages. S1 VIN L1 VO Duty Cycle C1 D1 R1 Buck Controller Oscillator Slope Comp VFB Error Amplifier FFB The NCV8842 has a transconductance error amplifier, whose non−inverting input is connected to an Internal Reference Voltage generated from the on−chip regulator. The inverting input connects to the VFB pin. The output of the error amplifier is made available at the VC pin. A typical frequency compensation requires only a 0.1 mF capacitor connected between the VC pin and ground, as shown in Figure 1. This capacitor and error amplifier’s output resistance (approximately 8.0 MW) create a low frequency pole to limit the bandwidth. Since V2 control does not require a high bandwidth error amplifier, the frequency compensation is greatly simplified. The VC pin is clamped below Output High Voltage. This allows the regulator to recover quickly from over current or short circuit conditions. ) Latch S R R2 SFB − + VC − + PWM Comparator V2 Control Error Amplifier VREF + − Figure 3. Buck Converter with V2 Control. As shown in Figure 3, there are two voltage feedback paths in V2 control, namely FFB(Fast Feedback) and SFB(Slow Feedback). In FFB path, the feedback voltage connects directly to the PWM comparator. This feedback path carries the ramp signal as well as the output DC voltage. Artificial ramp derived from the oscillator is added to the feedback signal to improve stability. The other feedback path, SFB, connects the feedback voltage to the error amplifier whose output VC feeds to the other input of the PWM comparator. In a constant frequency mode, the oscillator signal sets the output latch and turns on the switch S1. This starts a new switch cycle. The ramp signal, composed of both artificial ramp and output ripple, eventually comes across the VC voltage, and consequently resets the latch to turn off the switch. The switch S1 will turn on again at the beginning of the next switch cycle. In a buck converter, the output ripple is determined by the ripple Oscillator and Sync Feature The on−chip oscillator is trimmed at the factory and requires no external components for frequency control. The high switching frequency allows smaller external components to be used, resulting in a board area and cost savings. The tight frequency tolerance simplifies magnetic components selection. The switching frequency is reduced to no more than 25% of the nominal value when the VFB pin voltage is below Frequency Foldback Threshold. In short circuit or over−load conditions, this reduces the power dissipation of the IC and external components. The oscillator frequency varies with junction temperature, as seen in the following graph. http://onsemi.com 6 NCV8842 Power Switch and Current Limit fOSC, FREQUENCY (%) 102.5 The collector of the built−in NPN power switch is connected to the VIN pin, and the emitter to the VSW pin. When the switch turns on, the VSW voltage is equal to the VIN minus switch Saturation Voltage. In the buck regulator, the VSW voltage swings to one diode drop below ground when the power switch turns off, and the inductor current is commutated to the catch diode. Due to the presence of high pulsed current, the traces connecting the VSW pin, inductor and diode should be kept as short as possible to minimize the noise and radiation. For the same reason, the input capacitor should be placed close to the VIN pin and the anode of the diode. The saturation voltage of the power switch is dependent on the switching current, as shown in Figure 7. 100 97.5 95 92.5 90 −40 −20 0 20 40 60 80 100 120 140 TJ, JUNCTION TEMPERATURE (°C) Figure 4. Oscillator Frequency Versus Junction Temperature 1.0 Sync 10k ±33% (VIN − VSW) / (VIN − VSW) @ 1.5 A An external clock signal can sync the NCV8842 to a higher frequency. The SYNC pin equivalent input circuit is shown in Figure 5. 50k ±33% VZ = 11V to 20V 50k ±33% GND 0.9 0.8 0.7 0.6 0.5 0.4 0.3 Figure 5. The rising edge of the sync pulse turns on the power switch to start a new switching cycle, as shown in Figure 6. There is approximately 0.5 ms delay between the rising edge of the sync pulse and rising edge of the VSW pin voltage. The sync threshold is TTL logic compatible, and duty cycle of the sync pulses can vary from 10% to 90%. The frequency foldback feature is disabled during the sync mode. 0 0.5 1.0 1.5 SWITCHING CURRENT (A) 2.0 Figure 7. Power Switch Saturation Versus Switching Current (Normalized to 1.5 A) The NCV8842 contains pulse−by−pulse current limiting to protect the power switch and external components. When the peak of the switching current reaches the Current Limit, the power switch turns off after the Current Limit Delay. The switch will not turn on until the next switching cycle. The current limit threshold is independent of switching duty cycle. The maximum load current, given by the following formula under continuous conduction mode, is less than the Current Limit due to the ripple current. V (V * VO) IO(MAX) + ILIM * O IN 2(L)(VIN)(fs) where: fS = switching frequency, ILIM = current limit threshold, VO = output voltage, VIN = input voltage, L = inductor value. When the regulator runs under current limit, the subharmonic oscillation may cause low frequency Figure 6. A NCV8842 Buck Regulator is Synchronized to an External 350 kHz Pulse Signal http://onsemi.com 7 NCV8842 oscillation, as shown in Figure 8. Similar to current mode control, this oscillation occurs at the duty cycle greater than 50% and can be alleviated by using a larger inductor value. The current limit threshold is reduced to Foldback Current when the FB pin falls below Foldback Threshold. This feature protects the IC and external components under the power up or over−load conditions. BOOST PIN CURRENT (mA) 30 25 20 15 10 5 0 0 0.5 1.0 SWITCHING CURRENT (A) 1.5 Figure 9. The Boost Pin Current Includes 7.0 mA Pre−Driver Current and Base Current when the Switch is Turned On. The Beta Decline of the Power Switch Further Increases the Base Current at High Switching Current Shutdown The internal power switch will not turn on until the VIN pin rises above the Startup Voltage. This ensures no switching will occur until adequate supply voltage is provided to the IC. Refer to Figure 10 for the SHDNB (shutdown−bar) pin input circuit. Figure 8. The Regulator in Current Limit BOOST Pin The BOOST pin provides base driving current for the power switch. A voltage higher than VIN provides required headroom to turn on the power switch. This in turn reduces IC power dissipation and improves overall system efficiency. The BOOST pin can be connected to an external boost−strapping circuit which typically uses a 0.1 mF capacitor and a 1N914 or 1N4148 diode, as shown in Figure 1. When the power switch is turned on, the voltage on the BOOST pin is equal to 1 mA to 10 mA SHDNB VIN 20k ±33% 1.2V + VZ = 6V to 8V VBOOST + VIN ) VO * VF GND where: VF = diode forward voltage. The anode of the diode can be connected to any DC voltage as well as the regulated output voltage (Figure 1). However, the maximum voltage on the BOOST pin should not exceed 40 V. As shown in Figure 9, the BOOST pin current includes a constant 7.0 mA pre−driver current and base current proportional to switch conducting current. A detailed discussion of this current is conducted in Thermal Consideration section. A 0.1 mF capacitor is usually adequate for maintaining the Boost pin voltage during the on time. Figure 10. The IC enters a sleep mode when the SHDNB pin is pulled below the Shutdown Threshold Voltage. In sleep mode, the power switch is kept open and the supply current reduces to Shutdown Quiescent Current ( 1 mA typically). This pin has an internal pull−down current. When not in use, pull this pin up to VCC with a resistor (See Figure 1). A 100 kW pullup resistor will ensure safe operation from below 9 V and during a 40 V load dump condition. http://onsemi.com 8 NCV8842 Startup minimum duty cycle by extending the switching cycle. This protects the IC from overheating, and also limits the power that can be transferred to the output. The current limit foldback effectively reduces the current stress on the inductor and diode. When the output is shorted, the DC current of the inductor and diode can approach the current limit threshold. Therefore, reducing the current limit by 40% can result in an equal percentage drop of the inductor and diode current. The short circuit waveforms are captured in Figure 12, and the benefit of the foldback frequency and current limit is self−evident. During power up, the regulator tends to quickly charge up the output capacitors to reach voltage regulation. This gives rise to an excessive in−rush current which can be detrimental to the inductor, IC and catch diode. In V2 control , the compensation capacitor provides Soft−Start with no need for extra pin or circuitry. During the power up, the Output Source Current of the error amplifier charges the compensation capacitor which forces VC pin and thus output voltage ramp up gradually. The Soft−Start duration can be calculated by V CCOMP TSS + C ISOURCE where: VC = VC pin steady−state voltage, which is approximately equal to error amplifier’s reference voltage. CCOMP = Compensation capacitor connected to the VC pin ISOURCE = Output Source Current of the error amplifier. Using a 0.1 mF CCOMP, the calculation shows a TSS over 5.0 ms which is adequate to avoid any current stresses. Figure 11 shows the gradual rise of the VC, VO and envelope of the VSW during power up. There is no voltage over−shoot after the output voltage reaches the regulation. If the supply voltage rises slower than the VC pin, output voltage may over−shoot. Figure 12. In Short Circuit, the Foldback Current and Foldback Frequency Limit the Switching Current to Protect the IC, Inductor and Catch Diode Thermal Considerations A calculation of the power dissipation of the IC is always necessary prior to the adoption of the regulator. The current drawn by the IC includes quiescent current, pre−driver current, and power switch base current. The quiescent current drives the low power circuits in the IC, which include comparators, error amplifier and other logic blocks. Therefore, this current is independent of the switching current and generates power equal to WQ + VIN IQ where: IQ = quiescent current. Figure 11. The Power Up Transition of NCV8842 Regulator The pre−driver current is used to turn on/off the power switch and is approximately equal to 12 mA in worst case. During steady state operation, the IC draws this current from the Boost pin when the power switch is on and then receives it from the VIN pin when the switch is off. The pre−driver current always returns to the VSW pin. Since the pre−driver current goes out to the regulator’s output even when the power switch is turned off, a minimum load is required to prevent overvoltage in light load conditions. If the Boost pin voltage is equal to VIN + VO when the switch is on, the power dissipation due to pre−driver current can be calculated by Short Circuit When the VFB pin voltage drops below Foldback Threshold, the regulator reduces the peak current limit by 40% and switching frequency to 1/4 of the nominal frequency. These features are designed to protect the IC and external components during over load or short circuit conditions. In those conditions, peak switching current is clamped to the current limit threshold. The reduced switching frequency significantly increases the ripple current, and thus lowers the DC current. The short circuit can cause the minimum duty cycle to be limited by Minimum Output Pulse Width. The foldback frequency reduces the http://onsemi.com 9 NCV8842 COMPONENT SELECTION V 2 (VIN * VO ) O ) VIN WDRV + 12 mA Input Capacitor The base current of a bipolar transistor is equal to collector current divided by beta of the device. Beta of 60 is used here to estimate the base current. The Boost pin provides the base current when the transistor needs to be on. The power dissipated by the IC due to this current is V 2 WBASE + O VIN In a buck converter, the input capacitor supplies pulsed current with an amplitude equal to the load current. This pulsed current and the ESR of the input capacitors determine the VIN ripple voltage, which is shown in Figure 13. For VIN ripple, low ESR is a critical requirement for the input capacitor selection. The pulsed input current has a significant AC component, which is absorbed by the input capacitors. The RMS current of the input capacitor can be calculated using: IS 60 where: IS = DC switching current. IRMS + IO ǸD(1 * D) When the power switch turns on, the saturation voltage and conduction current contribute to the power loss of a non−ideal switch. The power loss can be quantified as WSAT + VO VIN IS where: D = switching duty cycle which is equal to VO/VIN. IO = load current. VSAT where: VSAT = saturation voltage of the power switch which is shown in Figure 7. The switching loss occurs when the switch experiences both high current and voltage during each switch transition. This regulator has a 30 ns turn−off time and associated power loss is equal to I WS + S 2 VIN 30 ns fS The turn−on time is much shorter and thus turn−on loss is not considered here. The total power dissipated by the IC is sum of all the above WIC + WQ ) WDRV ) WBASE ) WSAT ) WS Figure 13. Input Voltage Ripple in a Buck Converter The IC junction temperature can be calculated from the ambient temperature, IC power dissipation and thermal resistance of the package. The equation is shown as follows, To calculate the RMS current, multiply the load current with the constant given by Figure 14 at each duty cycle. It is a common practice to select the input capacitor with an RMS current rating more than half the maximum load current. If multiple capacitors are paralleled, the RMS current for each capacitor should be the total current divided by the number of capacitors. TJ + WIC RqJA ) TA Minimum Load Requirement As pointed out in the previous section, a minimum load is required for this regulator due to the pre−driver current feeding the output. Placing a resistor equal to VO divided by 12 mA should prevent any voltage overshoot at light load conditions. Alternatively, the feedback resistors can be valued properly to consume 12 mA current. 0.6 0.5 IRMS (XIO) 0.4 0.3 0.2 0.1 0 0 0.2 0.4 0.6 DUTY CYCLE 0.8 1.0 Figure 14. Input Capacitor RMS Current can be Calculated by Multiplying Y Value with Maximum Load Current at any Duty Cycle http://onsemi.com 10 NCV8842 Input capacitor type selection is determined by design constraints and emphasis (such as cost, performance, or size). Aluminum electrolytic capacitors are widely available in a broad selection of values, and are generally economical. Their ESR and ESL (effective series inductance), however, are relatively high. Multiple capacitors are often connected in parallel to reduce ESR, and ceramic capacitors added in parallel to reduce high frequency noise. OS−CON types exhibit lower ESR. Solid tantalum capacitors combine low ESR with small physical size. wave due to ESL. Capacitive reactance is assumed to be small compared to ESR and ESL. The peak to peak ripple current of the inductor is: V (V * VO) IP * P + O IN (VIN)(L)(fS) VRIPPLE(ESR), the output ripple due to the ESR, is equal to the product of IP−P and ESR. The voltage developed across the ESL is proportional to the di/dt of the output capacitor. It is realized that the di/dt of the output capacitor is the same as the di/dt of the inductor current. Therefore, when the switch turns on, the di/dt is equal to (VIN − VO)/L, and it becomes VO/L when the switch turns off. The total ripple voltage induced by ESL can then be derived from Output Capacitor In a buck converter, the requirements on the output capacitor are not as critical as those on the input capacitor. The current to the output capacitor comes from the inductor and thus is triangular. In most applications, this makes the RMS ripple current not an issue in selecting output capacitors. The output ripple voltage is the sum of a triangular wave caused by ripple current flowing through ESR, and a square V * VO V V VRIPPLE(ESL) + ESL( IN) ) ESL( IN ) + ESL( IN) L L L The total output ripple is the sum of the VRIPPLE(ESR) and VRIPPLE(ESR). Figure 15. Output Voltage Ripple Using Two 10 mF Ceramic Capacitors in Parallel Figure 16. Output Voltage Ripple Using One 100 mF POSCAP Capacitor Figure 17. Output Voltage Ripple Using One 100 mF OS−CON Figure 18. Output Voltage Ripple Using One 100 mF Tantalum Capacitor http://onsemi.com 11 NCV8842 Figure 15 to Figure 18 show the output ripple of a 5.0 V to 3.3 V/500 mA regulator using 22 mH inductor and various capacitor types. At the switching frequency, the low ESR and ESL make the ceramic capacitors behave capacitively as shown in Figure 15. Additional paralleled ceramic capacitors will further reduce the ripple voltage, but inevitably increase the cost. “POSCAP”, manufactured by SANYO, is a solid electrolytic capacitor. The anode is sintered tantalum and the cathode is a highly conductive polymerized organic semiconductor. TPC series, featuring low ESR and low profile, is used in the measurement of Figure 16. It is shown that POSCAP presents a good balance of capacitance and ESR, compared with a ceramic capacitor. In this application, the low ESR generates less than 5.0 mV of ripple and the ESL is almost unnoticeable. The ESL of the through−hole OS−CON capacitor give rise to the inductive impedance. It is evident from Figure 17 which shows the step rise of the output ripple on the switch turn−on and large spike on the switch turn−off. The ESL prevents the output capacitor from quickly charging up the parasitic capacitor of the inductor when the switch node is pulled below ground through the catch diode conduction. This results in the spike associated with the falling edge of the switch node. The D package tantalum capacitor used in Figure 18 has the same footprint as the POSCAP, but doubles the height. The ESR of the tantalum capacitor is apparently higher than the POSCAP. The electrolytic and tantalum capacitors provide a low−cost solution with compromised performance. The reliability of the tantalum capacitor is not a serious concern for output filtering because the output capacitor is usually free of surge current and voltage. The worse case diode average current occurs during maximum load current and maximum input voltage. Diode power dissipation can be estimated by (Iavg x Vf) x (100−%duty cycle) x 0.01. Average power, ambient temperature and thermal characteristics must all be considered when selecting a diode. For the diode to survive a short circuit condition, the current rating should exceed the Foldback Current Limit. Inductor Selection When choosing inductors, one might have to consider maximum load current, core and copper losses, component height, output ripple, EMI, saturation and cost. Lower inductor values are chosen to reduce the physical size of the inductor. Higher value cuts down the ripple current, core losses and allows more output current. For most applications, the inductor value falls in the range between 2.2 mH and 22 mH. The saturation current ratings of the inductor shall not exceed the IL(PK), calculated according to V (V * VO) IL(PK) + IO ) O IN 2(fS)(L)(VIN) The DC current through the inductor is equal to the load current. The worse case occurs during maximum load current. Check the vendor’s spec to adjust the inductor value under current loading. Inductors can lose over 50% of inductance when it nears saturation. The core materials have a significant effect on inductor performance. The ferrite core has benefits of small physical size, and very low power dissipation. But be careful not to operate these inductors too far beyond their maximum ratings for peak current, as this will saturate the core. Powered Iron cores are low cost and have a more gradual saturation curve. The cores with an open magnetic path, such as rod or barrel, tend to generate high magnetic field radiation. However, they are usually cheap and small. The cores providing a close magnetic loop, such as pot−core and toroid, generate low electro−magnetic interference (EMI). There are many magnetic component vendors providing standard product lines suitable for the NCV8842. Table 1 lists three vendors, their products and contact information. Diode Selection The diode in the buck converter provides the inductor current path when the power switch turns off. The peak reverse voltage is equal to the maximum input voltage. The peak conducting current is clamped by the current limit of the IC. The average current can be calculated from: I (V * VO) ID(AVG) + O IN VIN Table 1. Vendor Product Family Web Site Coiltronics UNI−Pac1/2: SMT, barrel THIN−PAC: SMT, toroid, low profile CTX: Leaded, toroid www.coiltronics.com Coilcraft DO1608: SMT, barrel DS/DT 1608: SMT, barrel, magnetically shielded DO3316: SMT, barrel DS/DT 3316: SMT, barrel, magnetically shielded DO3308: SMT, barrel, low profile www.coilcraft.com TDK SUF10145, SUF12555, VLF10040 www.tdk.com http://onsemi.com 12 NCV8842 ORDERING INFORMATION Package Shipping† NCV8842DG SOIC−8 (Pb−Free) 98 Units / Rail NCV8842DR2G SOIC−8 (Pb−Free) 2500 Units / Tape & Reel NCV8842PWG SO−16WEP (Pb−Free) 47 Units / Rail NCV8842PWR2G SO−16WEP (Pb−Free) 1000 Units / Tape & Reel NCV8842MNR2G DFN18 (Pb−Free) 2500 Units / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 13 NCV8842 PACKAGE DIMENSIONS SOIC 16−LEAD WIDE BODY EXPOSED PAD PW SUFFIX CASE 751AG−01 ISSUE A −U− A M P 0.25 (0.010) M W M 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751R-01 OBSOLETE, NEW STANDARD 751R-02. 9 B 1 R x 45_ 8 −W− G PIN 1 I.D. 14 PL DETAIL E TOP SIDE C F −T− 0.10 (0.004) T K D 16 PL 0.25 (0.010) M T U SEATING PLANE W S J S DETAIL E H EXPOSED PAD 1 8 L 16 DIM A B C D F G H J K L M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 3.45 3.66 0.25 0.32 0.00 0.10 4.72 4.93 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.136 0.144 0.010 0.012 0.000 0.004 0.186 0.194 0_ 7_ 0.395 0.415 0.010 0.029 SOLDERING FOOTPRINT* 9 0.350 Exposed Pad 0.175 BACK SIDE 0.050 CL 0.200 0.188 CL 0.376 0.074 0.024 0.150 DIMENSIONS: INCHES *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 NCV8842 PACKAGE DIMENSIONS DFN18 6x5, 0.5P CASE 505−01 ISSUE D NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A D B PIN 1 LOCATION E 2X DIM A A1 A3 b D D2 E E2 e K L 0.15 C 2X TOP VIEW 0.15 C (A3) 0.10 C A 18X 0.08 C A1 C SIDE VIEW SEATING PLANE SOLDERING FOOTPRINT* D2 18X 18X L 5.30 e 1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 −−− 0.45 0.65 1 9 0.50 PITCH E2 K 18 10 BOTTOM VIEW 18X 0.75 4.19 18X b 0.10 C A B 0.05 C 18X 0.30 NOTE 3 3.24 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 15 NCV8842 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. V2 is a trademark of Switch Power, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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