DATA SHEET
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Automotive Grade
Non-Synchronous Boost
Controller
8
1
SOIC−8
D SUFFIX
CASE 751
NCV8871
The NCV8871 is an adjustable output non−synchronous boost
controller which drives an external N−channel MOSFET. The device
uses peak current mode control with internal slope compensation. The
IC incorporates an internal regulator that supplies charge to the gate
driver.
Protection features include internally−set soft−start, undervoltage
lockout, cycle−by−cycle current limiting, hiccup−mode short−circuit
protection and thermal shutdown.
Additional features include low quiescent current sleep mode and
externally−synchronizable switching frequency.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Peak Current Mode Control with Internal Slope Compensation
1.2 V ±2% Reference voltage
Fixed Frequency Operation
Wide Input Voltage Range of 3.2 V to 40 Vdc, 45 V Load Dump
Input Undervoltage Lockout (UVLO)
Internal Soft−Start
Low Quiescent Current in Sleep Mode
Cycle−by−Cycle Current Limit Protection
Hiccup−Mode Overcurrent Protection (OCP)
Hiccup−Mode Short−Circuit Protection (SCP)
Thermal Shutdown (TSD)
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This is a Pb−Free Device
MARKING DIAGRAM
8
8871xxG
ALYW
G
1
8871xxG = Specific Device Code
xx = 00, 03, 04, 05
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
EN/SYNC 1
8 VFB
ISNS 2
7 VC
GND 3
6 VIN
GDRV 4
5 VDRV
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCV887100D1R2G
SOIC−8
(Pb−Free)
2500 / Tape &
Reel
NCV887103D1R2G
SOIC−8
(Pb−Free)
2500 / Tape &
Reel
NCV887104D1R2G
SOIC−8
(Pb−Free)
2500 / Tape &
Reel
NCV887105D1R2G
SOIC−8
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
November, 2021 − Rev. 17
1
Publication Order Number:
NCV8871/D
NCV8871
6
TEMP
VDRV
FAULT
LOGIC
EN/SYNC
SYNC
1
OSC
SC
VC
5
CLK
7
PWM
EN/
4
2
CL
+
RC
DRIVE
LOGIC
CSA
3
CDRV
VDRV
Cg
L
D
Vo
Q
GDRV
ISNS
GND
Co
RSNS
RF1
SCP
CC
Vg
VIN
8
Gm
SS
VFB
RF2
Vref
Figure 1. Simplified Block Diagram and Application Schematic
PACKAGE PIN DESCRIPTIONS
Pin No.
Pin
Symbol
1
EN/SYNC
2
ISNS
Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense
resistor to ground to sense the switching current for regulation and current limiting.
3
GND
Ground reference.
4
GDRV
Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from
GDRV to the gate to tailor EMC performance.
5
VDRV
Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VIN. Bypass
with a 1.0 mF ceramic capacitor to ground.
6
VIN
Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addition to a diode from the output voltage to VDRV and/or VIN.
7
VC
Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize
the converter.
8
VFB
Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND
creates a voltage divider for regulation and programming of the output voltage.
Function
Enable and synchronization input. The falling edge synchronizes the internal oscillator. The part is disabled
into sleep mode when this pin is brought low for longer than the enable time−out period.
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NCV8871
ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated)
Rating
Value
Unit
−0.3 to 40
V
Peak Transient Voltage (Load Dump on VIN)
45
V
Dc Supply Voltage (VDRV, GDRV)
12
V
−0.3 to 6
V
−0.3 to 3.6
V
Dc Voltage (EN/SYNC)
−0.3 to 6
V
Dc Voltage Stress (VIN − VDRV)*
−0.7 to 45
V
Operating Junction Temperature
−40 to 150
°C
Storage Temperature Range
−65 to 150
°C
Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C
265 peak
°C
Dc Supply Voltage (VIN)
Peak Transient Voltage (VFB)
Dc Voltage (VC, VFB, ISNS)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*An external diode from the input to the VIN pin is required if bootstrapping VDRV and VIN off of the output voltage.
PACKAGE CAPABILITIES
Characteristic
ESD Capability (All Pins)
Human Body Model
Machine Model
Value
Unit
w2.0
w200
kV
V
1
−
100
°C/W
Moisture Sensitivity Level
Package Thermal Resistance
1. 1
in2,
Junction−to−Ambient, RqJA (Note 1)
1 oz copper area used for heatsinking.
Device Variations
The NCV8871 features several variants to better fit a
multitude of applications. The table below shows the typical
values of parameters for the parts that are currently
available.
TYPICAL VALUES
Part No.
Dmax
fs
tss
Sa
Vcl
Isrc
Isink
VDRV
SCE
NCV887100
88%
170 kHz
7.4 ms
53 mV/ms
400 mV
800 mA
600 mA
10.5 V
Y
NCV887103
93%
340 kHz
3.7 ms
53 mV/ms
200 mV
575 mA
350 mA
8.4 V
Y
NCV887104
93%
340 kHz
3.7 ms
53 mV/ms
200 mV
800 mA
600 mA
8.4 V
N
NCV887105
88%
170 kHz
7.4 ms
53 mV/ms
400 mV
800 mA
600 mA
10.5 V
N
DEFINITIONS
Symbol
Dmax
Characteristic
Symbol
Characteristic
Symbol
Characteristic
Maximum Duty Cycle
fs
Switching Frequency
tss
Soft−Start Time
Sa
Slope Compensating Ramp
Vcl
Current Limit Trip Voltage
Isrc
Gate Drive Sourcing Current
Isink
Gate Drive Sinking Current
VDRV
Drive Voltage
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3
SCE
Short Circuit Enable
NCV8871
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
mA
GENERAL
Quiescent Current, Sleep Mode
Iq,sleep
VIN = 13.2 V, EN = 0, TJ = 25°C
−
2.0
−
Quiescent Current, Sleep Mode
Iq,sleep
VIN = 13.2 V, EN = 0, −40°C < TJ < 125°C
−
2.0
6.0
mA
Quiescent Current, No switching
Iq,off
Into VIN pin, EN = 1, No switching
−
1.5
2.5
mA
Quiescent Current, Switching,
normal operation
Iq,on
Into VIN pin, EN = 1, Switching
−
3.0
6.0
mA
90
115
140
ns
OSCILLATOR
Minimum pulse width
ton,min
Maximum duty cycle
Dmax
NCV887100
NCV887103
NCV887104
NCV887105
86
91
91
86
88
93
93
88
90
95
95
90
%
Switching frequency
fs
NCV887100
NCV887103
NCV887104
NCV887105
153
306
306
153
170
340
340
170
187
374
374
187
kHz
Soft−start time
tss
From start of switching with VFB = 0 until
reference voltage = VREF
NCV887100
NCV887103
NCV887104
NCV887105
6.0
3.0
3.0
6.0
7.4
3.7
3.7
7.4
8.8
4.4
4.4
8.8
From EN → 1 until start of switching with
VFB = 0
−
240
280
NCV887100
NCV887103
NCV887104
NCV887105
46
46
46
46
53
53
53
53
60
60
60
60
mV/ms
VEN/SYNC = 5 V
−
5.0
10
mA
2.0
−
5.0
V
0
−
800
mV
From SYNC falling edge, to oscillator control (EN high) or shutdown (EN low), Percent of typical switching period
−
−
350
%
Percent of fs
−
−
80
%
1.1
−
−
MHz
−
50
100
ns
25
−
75
%
Soft−start delay
Slope compensating ramp
tss,dly
Sa
ms
ms
ENABLE/SYNCHRONIZATION
EN/SYNC pull−down current
IEN/SYNC
EN/SYNC input high voltage
Vs,ih
EN/SYNC input low voltage
Vs,il
EN/SYNC time−out ratio
%ten
SYNC minimum frequency ratio
SYNC maximum frequency
%fsync,min
VIN > VUVLO
fsync,max
Synchronization delay
ts,dly
Synchronization duty cycle
Dsync
From SYNC falling edge to GDRV falling
edge under open loop conditions
CURRENT SENSE AMPLIFIER
Input−to−output gain at dc, ISNS v 1 V
0.9
1.0
1.1
V/V
Bandwidth
BWcsa
Gain of Acsa − 3 dB
2.5
−
−
MHz
ISNS input bias current
Isns,bias
Out of ISNS pin
−
30
50
mA
360
180
180
360
400
200
200
400
440
220
220
440
−
80
125
Low−frequency gain
Acsa
Current limit threshold voltage
Vcl
Voltage on ISNS pin
NCV887100
NCV887103
NCV887104
NCV887105
Current limit,
Response time
tcl
CL tripped until GDRV falling edge,
VISNS = Vcl(typ) + 60 mV
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4
mV
ns
NCV8871
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
125
150
175
%
−
−
125
ns
0.8
1.2
1.63
mS
2.0
−
−
MW
−
0.5
2.0
mA
CURRENT SENSE AMPLIFIER
Overcurrent protection,
Threshold voltage
%Vocp
Overcurrent protection,
Response Time
tocp
Percent of Vcl
From overcurrent event, Until switching
stops, VISNS = VOCP + 40 mV
VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
Transconductance
gm,vea
VEA output resistance
Ro,vea
VFB input bias current
Ivfb,bias
Reference voltage
VFB – Vref = ± 20 mV
Current out of VFB pin
Vref
1.176
1.200
1.224
V
VEA maximum output voltage
Vc,max
2.5
−
−
V
VEA minimum output voltage
Vc,min
−
−
0.3
V
VEA sourcing current
Isrc,vea
VEA output current, Vc = 2.0 V
80
100
−
mA
VEA sinking current
Isnk,vea
VEA output current, Vc = 0.7 V
80
100
−
mA
GATE DRIVER
Sourcing current
Isrc
VDRV ≥ 6 V, VDRV − VGDRV = 2 V
NCV887100
NCV887103
NCV887104
NCV887105
600
400
600
600
800
575
800
800
−
−
−
−
Sinking current
Isink
VGDRV ≥ 2 V
NCV887100
NCV887103
NCV887104
NCV887105
500
250
500
500
600
350
600
600
−
−
−
−
VIN − VDRV, IvDRV = 25 mA
−
0.3
0.6
V
VIN − VDRV = 1 V
35
45
−
mA
−
−
0.7
V
10
8.0
8.0
10
10.5
8.4
8.4
10.5
11
8.8
8.8
11
−
15
−
kW
Driving voltage dropout
Vdrv,do
Driving voltage source current
Idrv
Backdrive diode voltage drop
Vd,bd
VDRV − VIN, Id,bd = 5 mA
Driving voltage
VDRV
IVDRV = 0.1 − 25 mA
NCV887100
NCV887103
NCV887104
NCV887105
Pull−down resistance
Rpd
mA
mA
V
UVLO
Undervoltage lock−out,
Threshold voltage
Vuvlo
VIN falling
3.0
3.1
3.2
V
Undervoltage lock−out,
Hysteresis
Vuvlo,hys
VIN rising
50
125
200
mV
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NCV8871
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
SHORT CIRCUIT PROTECTION
Startup blanking period
%tscp,dly
From start of soft−start, Percent of tss
100
120
150
%
Hiccup−mode period
%thcp,dly
From shutdown to start of soft−start,
Percent of tss
70
85
100
%
VFB as percent of Vref
60
67
75
%
tscp
From VFB < Vscp to stop switching
−
35
100
ns
Thermal shutdown threshold
Tsd
TJ rising
160
170
180
°C
Thermal shutdown hysteresis
Tsd,hys
TJ falling
10
15
20
°C
Thermal shutdown delay
tsd,dly
From TJ > Tsd to stop switching
−
−
100
ns
Short circuit threshold voltage
Short circuit delay
%Vscp
THERMAL SHUTDOWN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCV8871
TYPICAL PERFORMANCE CHARACTERISTICS
5.5
TJ = 25°C
Iq,on, QUIESCENTCURRENT (mA)
Iq,sleep, SLEEP CURRENT (mA)
7
6
5
4
3
2
1
0
0
10
20
30
VIN, INPUT VOLTAGE (V)
5.0
4.5
4.0
3.5
40
TJ = 25°C,
VIN = 13.2 V
0
200
400
600
800
fs, SWITCHING FREQUENCY (kHz)
Figure 2. Sleep Current vs. Input Voltage
Figure 3. Quiescent Current vs. Switching
Frequency
3.30
VIN = 13.2 V
5
Iq,on, QUIESCENTCURRENT (mA)
Iq,sleep, SLEEP CURRENT (mA)
6
4
3
2
1
0
−50
0
50
100
150
3.25
3.15
3.10
3.05
3.00
−40
200
NORMALIZED CURRENT LIMIT (25°C)
125
ton,min MINIMUM ON TIME (ns)
10
60
110
TJ, JUNCTION TEMPERATURE (°C)
160
Figure 5. Quiescent Current vs. Temperature
Figure 4. Sleep Current vs. Temperature
123
121
119
117
10
60
110
TJ, JUNCTION TEMPERATURE (°C)
VIN = 13.2 V
fs = 170 kHz
3.20
TJ, JUNCTION TEMPERATURE (°C)
115
−40
1000
160
1.010
1.005
1.000
0.995
0.990
−40
Figure 6. Minimum On Time vs. Temperature
10
60
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Normalized Current Limit vs.
Temperature
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160
NCV8871
TYPICAL PERFORMANCE CHARACTERISTICS
7
Vref, REFERENCE VOLTAGE (V)
Ienable, PULLDOWN CURRENT (mA)
1.205
1.203
1.201
1.199
1.197
5
4
3
2
1
0
TJ, JUNCTION TEMPERATURE (°C)
2
3
4
Venable, VOLTAGE (V)
Figure 8. Reference Voltage vs. Temperature
Figure 9. Enable Pulldown Current vs. Voltage
10
60
110
160
0
1
8.0
Ienable, PULLDOWN CURRENT (mA)
1.195
−40
TJ = 25°C
6
7.5
7.0
6.5
6.0
5.5
5.0
−40
10
60
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Enable Pulldown Current vs.
Temperature
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160
5
6
NCV8871
THEORY OF OPERATION
VIN
L
Oscillator
PWM Comparator
−
S
GDRV
Q
Gate
Drive
R
CO
RL
+
+
VOUT
+
Voltage Error
ISNS
−
CSA
VFB
−
+
VEA
NCV8871
Compensation
Figure 11. Current Mode Control Schematic
Current Mode Control
If the voltage across the current sense resistor exceeds the
over current threshold voltage the device enters over current
hiccup mode. The device will remain off for the hiccup time
and then go through the soft−start procedure.
The NCV8871 incorporates a current mode control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the on−time of the
power switch. The oscillator is used as a fixed−frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and the error amplifier, which is commonly
found in voltage mode controllers. The second benefit
comes from inherent pulse−by−pulse current limiting by
merely clamping the peak switching current. Finally, since
current mode commands an output current rather than
voltage, the filter offers only a single pole to the feedback
loop. This allows for a simpler compensation.
The NCV8871 also includes a slope compensation
scheme in which a fixed ramp generated by the oscillator is
added to the current ramp. A proper slope rate is provided to
improve circuit stability without sacrificing the advantages
of current mode control.
Short Circuit Protection
If the short circuit enable bit is set (SCE = Y) the device
will attempt to protect the power MOSFET from damage.
When the output voltage falls below the short circuit trip
voltage, after the initial short circuit blanking time, the
device enters short circuit latch off. The device will remain
off for the hiccup time and then go through the soft−start.
EN/SYNC
The Enable/Synchronization pin has three modes. When
a dc logic high (CMOS/TTL compatible) voltage is applied
to this pin the NCV8871 operates at the programmed
frequency. When a dc logic low voltage is applied to this pin
the NCV8871 enters a low quiescent current sleep mode.
When a square wave of at least %fsync,min of the free running
switching frequency is applied to this pin, the switcher
operates at the same frequency as the square wave. If the
signal is slower than this, it will be interpreted as enabling
and disabling the part. The falling edge of the square wave
corresponds to the start of the switching cycle. If device is
disabled, it must be disabled for 7 clock cycles before being
re−enabled.
If the VIN pin voltage falls below VUVLO when
EN/SYNC pin is at logic−high, the IC may not power up
when VIN returns back above the UVLO. To resume a
normal operating state, the EN/SYNC pin must be cycled
with a single logic−low to logic−high transition.
Current Limit
The NCV8871 features two current limit protections,
peak current mode and over current latch off. When the
current sense amplifier detects a voltage above the peak
current limit between ISNS and GND after the current limit
leading edge blanking time, the peak current limit causes the
power switch to turn off for the remainder of the cycle. Set
the current limit with a resistor from ISNS to GND, with R
= VCL / Ilimit.
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NCV8871
UVLO
From this the ideal minimum and maximum duty cycles
can be calculated as follows:
Input Undervoltage Lockout (UVLO) is provided to
ensure that unexpected behavior does not occur when VIN
is too low to support the internal rails and power the
controller. The IC will start up when enabled and VIN
surpasses the UVLO threshold plus the UVLO hysteresis
and will shut down when VIN drops below the UVLO
threshold or the part is disabled.
To avoid any lock state under UVLO conditions, the
EN/SYNC pin should be in logic−low state. For further
details, please refer to EN/SYNC paragraph.
D min + 1 *
D max + 1 *
V IN(max)
V OUT
V IN(min)
V OUT
Both duty cycles will actually be higher due to power loss
in the conversion. The exact duty cycles will depend on
conduction and switching losses. If the maximum input
voltage is higher than the output voltage, the minimum duty
cycle will be negative. This is because a boost converter
cannot have an output lower than the input. In situations
where the input is higher than the output, the output will
follow the input, minus the diode drop of the output diode
and the converter will not attempt to switch.
If the calculated Dmax is higher the Dmax of the NCV8871,
the conversion will not be possible. It is important for a boost
converter to have a restricted Dmax, because while the ideal
conversion ration of a boost converter goes up to infinity as
D approaches 1, a real converter’s conversion ratio starts to
decrease as losses overtake the increased power transfer. If
the converter is in this range it will not be able to regulate
properly.
If the following equation is not satisfied, the device will
skip pulses at high VIN:
Internal Soft−Start
To insure moderate inrush current and reduce output
overshoot, the NCV8871 features a soft start which charges a
capacitor with a fixed current to ramp up the reference voltage.
This fixed current is based on the switching frequency, so
that if the NCV8871 is synchronized to twice the default
switching frequency the soft start will last half as long.
VDRV
An internal regulator provides the drive voltage for the
gate driver. Bypass with a ceramic capacitor to ground to
ensure fast turn on times. The capacitor should be between
0.1 mF and 1 mF, depending on switching speed and charge
requirements of the external MOSFET.
APPLICATION INFORMATION
D min
w t on(min)
fs
Design Methodology
This section details an overview of the component selection
process for the NCV8871 in continuous conduction mode
boost. It is intended to assist with the design process but does
not remove all engineering design work. Many of the
equations make heavy use of the small ripple approximation.
This process entails the following steps:
1. Define Operational Parameters
2. Select Current Sense Resistor
3. Select Output Inductor
4. Select Output Capacitors
5. Select Input Capacitors
6. Select Feedback Resistors
7. Select Compensator Components
8. Select MOSFET(s)
9. Select Diode
10. Determine Feedback Loop Compensation Network
Where: fs: switching frequency [Hz]
ton(min): minimum on time [s]
2. Select Current Sense Resistor
Current sensing for peak current mode control and current
limit relies on the MOSFET current signal, which is
measured with a ground referenced amplifier. The easiest
method of generating this signal is to use a current sense
resistor from the source of the MOSFET to device ground.
The sense resistor should be selected as follows:
RS +
V CL
I CL
Where: RS: sense resistor [W]
VCL: current limit threshold voltage [V]
ICL: desire current limit [A]
1. Define Operational Parameters
3. Select Output Inductor
Before beginning the design, define the operating
parameters of the application. These include:
VIN(min): minimum input voltage [V]
VIN(max): maximum input voltage [V]
VOUT: output voltage [V]
IOUT(max): maximum output current [A]
ICL: desired typical cycle-by-cycle current limit [A]
The output inductor controls the current ripple that occurs
over a switching period. A high current ripple will result in
excessive power loss and ripple current requirements. A low
current ripple will result in a poor control signal and a slow
current slew rate in case of load steps. A good starting point
for peak to peak ripple is around 20−40% of the inductor
current at the maximum load at the worst case VIN, but
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NCV8871
operation should be verified empirically. The worst case VIN
is half of VOUT, or whatever VIN is closest to half of VOUT.
After choosing a peak current ripple value, calculate the
inductor value as follows:
L+
The total feedback resistance (Rupper + Rlower) should be in
the range of 1 kW – 100 kW.
7. Select Compensator Components
Current Mode control method employed by the NCV8871
allows the use of a simple, Type II compensation to optimize
the dynamic response according to system requirements.
V IN(WC) D WC
DI L,max f s
Where: VIN(WC): VIN value as close as possible to
half of VOUT [V]
DWC: duty cycle at VIN(WC)
DIL,max: maximum peak to peak ripple [A]
The maximum average inductor current can be calculated
as follows:
I L,AVG +
8. Select MOSFET(s)
In order to ensure the gate drive voltage does not drop out
the MOSFET(s) chosen must not violate the following
inequality:
Q g(total) v
V OUTI OUT(max)
Where: Qg(total): Total Gate Charge of MOSFET(s) [C]
Idrv: Drive voltage current [A]
fs: Switching Frequency [Hz]
The maximum RMS Current can be calculated as follows:
V IN(min)h
The Peak Inductor current can be calculated as follows:
I L,peak + I L,avg )
DI L,max
2
I Q(max) + I out
Where: IL,peak: Peak inductor current value [A]
The output capacitors smooth the output voltage and
reduce the overshoot and undershoot associated with line
transients. The steady state output ripple associated with the
output capacitors can be calculated as follows:
DI OUT(max)
fC OUT
)
ǒ
I OUT(max)
1*D
)
V IN(min)D
2fL
Ǔ
V Q(max) + V OUT(max)
9. Select Diode
The output diode rectifies the output current. The average
current through diode will be equal to the output current:
R ESR
I D(avg) + I OUT(max)
The capacitors need to survive an RMS ripple current as
follows:
I Cout(RMS) + I OUT
Ǹ
D WC
D
) WC
12
DȀ WC
ǒ
DȀ WC
L
R
OUT
T
SW
Ǔ
Additionally, the diode must block voltage equal to the
higher of the output voltage and the maximum input voltage:
2
V D(max) + V OUT(max)
The maximum power dissipation in the diode can be
calculated as follows:
The use of parallel ceramic bypass capacitors is strongly
encouraged to help with the transient response.
P D + V f (max) I OUT(max)
Where: Pd: Power dissipation in the diode [W]
Vf(max): Maximum forward voltage of the diode [V]
5. Select Input Capacitors
The input capacitor reduces voltage ripple on the input to
the module associated with the ac component of the input
current.
I Cin(RMS) +
10. Determine Feedback Loop Compensation Network
The purpose of a compensation network is to stabilize the
dynamic response of the converter. By optimizing the
compensation network, stable regulation response is
achieved for input line and load transients.
Compensator design involves the placement of poles and
zeros in the closed loop transfer function. Losses from the
boost inductor, MOSFET, current sensing and boost diode
losses also influence the gain and compensation
expressions. The OTA has an ESD protection structure
(RESD ≈ 502 W, data not provided in the datasheet) located
on the die between the OTA output and the IC package
compensation pin (VC). The information from the OTA
PWM feedback control signal (VCTRL) may differ from the
IC-VC signal if R2 is of similar order of magnitude as RESD .
V IN(min) 2 D WC
Lf sV OUT2 Ǹ3
6. Select Feedback Resistors
The feedback resistors form a resistor divider from the
output of the converter to ground, with a tap to the feedback
pin. During regulation, the divided voltage will equal Vref.
The lower feedback resistor can be chosen, and the upper
feedback resistor value is calculated as follows:
R upper + R lower
ǸD
DȀ
The maximum voltage across the MOSFET will be the
maximum output voltage, which is the higher of the
maximum input voltage and the regulated output voltaged:
4. Select Output Capacitors
V OUT(ripple) +
I drv
fs
ǒV out * V refǓ
V ref
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11
NCV8871
• The attenuating effect of large value ceramic capacitors
The compensation and gain expressions which follow take
influence from the OTA output impedance elements into
account.
Type-I compensation is not possible due to the presence
of RESD . The Figures 12 and 13 compensation networks
correspond to a Type-II network in series with RESD .
The resulting control-output transfer function is an accurate
mathematical model of the IC in a boost converter topology.
The model does have limitations and a more accurate SPICE
model should be considered for a more detailed analysis:
L
rL
VIN
•
in parallel with output electrolytic capacitor ESR is not
considered in the equations.
The CCM Boost control-output transfer function
includes operating efficiency as a correction factor to
improve modeling accuracy under low input voltage
and high output current operating conditions where
operating losses becomes significant.
Vd
VOUT
rCf
COUT
Rds(on)
VC
GDRV
R2
RESD
C2
C1
ISNS
VCTRL
OTA
Ri
R0
VFB
GND
R1
Rlow
Figure 12. NCV8871 Boost Converter OTA and Compensation
www.onsemi.com
12
ROUT
NCV8871
Vd
VIN
VOUT
1:N
rCf
Lp
COUT
Rds(on)
VC
ROUT
GDRV
R2
RESD
C2
C1
ISNS
VCTRL
OTA
R0
Ri
VREF
VFB
GND
R1
Rlow
Figure 13. NCV8871 Flyback Converter OTA and Compensation
Necessary equations for describing the modulator gain
(Vctrl-to-Vout gain) Hctrl_output (f) are described next. Boost
continuous conduction mode (CCM) and discontinuous
conduction mode (DCM) transfer function expressions are
summarized in Table 1. Flyback CCM and DCM transfer
function expressions are summarized in Table 2.
The following equations may be used to select compensation
components R2 , C1 , C2 for Figures 12 & 13 power supply.
Required input design parameters for analysis are:
Vd = Output diode Vf (V)
VIN = Power supply input voltage (V)
N = Ns /Np (Flyback transformer turns ratio)
Ri = Current sense resistor (W)
RDS(on) = MOSFET RDS(on) (W)
(Rsw_eq = RDS(on) + Ri for the boost continuous conduction
mode (CCM) expressions)
COUT = Bulk output capacitor value (F)
rCF = Bulk output capacitor ESR (W)
ROUT = Equivalent resistance of output load (W)
Pout = Output Power (W)
L = Boost inductor value or flyback transformer primary
side inductance (H)
rL = Boost inductor ESR (W)
Ts = 1/fs , where fs = clock frequency (Hz)
R1 and Rlow = Feedback resistor divider values used to set the
output voltage (W)
VOUT = Device specific output voltage (defined by R1 and
Rlow values) (V)
R0 = OTA output resistance = 3 MW
Sa = IC slope compensation (e.g. 53 mV/ms for NCV887100)
gm = OTA transconductance = 1.2 mS
D = Controller duty ratio
D’ = 1 − D
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13
NCV8871
Table 1. BOOST CCM AND DCM TRANSFER FUNCTION EXPRESSIONS
CCM
Duty Ratio (D)
ȡ
ȧ
ȧ
ȧ
Ȣ
-V OUT
DCM
ƪ
2R OUTV dV IN* R sw_eq)R OUT
Ǹ ǒ
ǒ
V IN
V OUT
*2
V OUT 2
Ǔ
ȣ
ȧ
ȧ
ȧ
Ȥ
R OUTV IN 2)2R sw_eqV INV OUT*4V dR sw_eqV IN
R OUT
)R sw_eq 2V OUT 2
-4R sw_eqV OUT 2*4r LV dV IN*4r LV OUT 2
ǒ
2R OUT V OUT 2 ) V dV IN
VOUT/VIN DC
Voltage Gain (M)
Ǔƫ
Ǹ2tLM(M * 1)
L
Where: t L +
R OUTT s
Ǔ
ȱ
ȳ
(1 * D)V ȧ
ȧ
1
1
ƪ
ƫ
1*
ȧ
ȧ
V
1
1*D
ȧ1 )
ȧ
r )DR
(1*D) ǒ
Ǔ
R
Ȳ
ȴ
d
out
2
1
2
ǒ Ǹ
1)
1)
2D 2
tL
Ǔ
sw_eq
L
OUT
V IN * I Laveǒr L ) R sw_eqǓ
Inductor On-slope
(Sn ), V/s
Ri
L
Where average inductor current:
Compensation
Ramp (mc )
Right-Half-Plane
Zero (wz2 )
(1 * D)
L
Low Frequency
Modulator Pole
(wp1 )
2
I Lave +
P out
1
r CFC OUT
r CFC OUT
ǒ
r CFR OUT
R OUT *
r CF ) R OUT
Ǔ
*
rL
R OUT
L
M 2L
1
R CFC OUT
2F SW
p
Sampling Double
Pole (wn )
1
1
ǒ
R OUTT s 1
Sa
2M )
)
2
Sn
LM 2
p1
Ǔ
D
S nm cT s
hR OUT
2V OUT
Ri
D
Ǔǒ
2
1
z1
z2
1)j
2pf 2
2pf
) ǒj w Ǔ
n
w nQ p
www.onsemi.com
14
@
M*1
2M * 1
ǒ1 ) j w2pfǓǒ1 * j w2pfǓ
ǒ1 ) j w2pfǓǒ1 * j w2pfǓ
2pf
1 )jw
1
1*M
−
p(m c(1 * D) * 0.5)
Hd
M*1
−
Ts
Fm
2M * 1
@
ǒ Ǔ
−
ǒ
Sn
1
High Frequency
Modulator Pole
(wp2 )
F mH d
Sa
1)
Sn
Ts
2
)
mc
R OUT
LM 3
Sampling Quality
Coefficient (Qp )
Ri
V INh
C OUT
Control-Output
Transfer Function
(Hctrl_output (f))
L
Sa
1)
Cout ESR Zero
(wz1 )
V IN
Ǔ
F mH d
z1
ǒ
2pf
1 )jw
p1
Ǔǒ
z2
2pf
1 ) jw
p2
Ǔ
NCV8871
Table 2. FLYBACK CCM AND DCM TRANSFER FUNCTION EXPRESSIONS
CCM
DCM
Duty ratio (D)
V OUT
V OUT
V OUT ) NV IN
VOUT/VIN DC Conversion
Ratio (M)
Compensation Ramp (mc )
1*D
V IN
V IN
Cout ESR Zero (wz1 )
Right-Half-Plane Zero (wz2 )
Ri
Lp
Sa
1)
1
r CFC OUT
(1 * D) R OUT
R OUT
DL pN 2
N 2L
ǒ
@
p
1
M(M ) 1)
Ǔ
2
R OUTC OUT
ǒ Ǔ
wp2
−
1
ǒ
2F SW
2
1
1)M
S nm cT s
R OUT
V IN
R iN
ǒ1 ) j w2pfǓǒ1 * j w2pfǓ
2pf
1 ) jw
p1
F mH d
Ǔ
Once the desired cross-over frequency (fc ) gain
adjustment and necessary phase boost are determined from
the Hctrl_output (f) gain and phase plots, the Table 3 equations
may be used. It should be noted that minor compensation
Ǹ
1
2t L
ǒ1 ) j w2pfǓǒ1 * j w2pfǓ
z2
z1
ǒ
1
D
1
Ǔ
Sa
DȀ 2
t L 1 ) 2 S n ) 2M ) 1
F mH d
Sn
1
Sa
DȀ 3
t L 1 ) 2 S n ) 1 ) D
Control-output Transfer
Function (Hctrl_output (f))
Ri
r CFC OUT
2
Hd
T sR OUT
Sa
1)
Sn
R OUTC OUT
Fm
N 2L p
N@D
Ǹ2 @ tL
Lp
Modulator Pole (wp1 )
Where: t L +
N@D
Inductor On-slope (Sn ), V/s
Ǹ2t L
NV IN
z1
ǒ
2pf
1 )jw
p1
Ǔǒ
z2
2pf
1 ) jw
p2
Ǔ
component value adjustments may become necessary when
R2 ≤ ~10·Resd as a result of approximations for determining
components R2 , C1 , C2 .
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15
NCV8871
Table 3. OTA COMPENSATION TRANSFER FUNCTION AND COMPENSATION VALUES
Desired OTA Gain at Cross-over Frequency fc (G)
desired_G fc_gain_db
20
10
ǒq
Desired Phase Boost at Cross-over Frequency fc (boost)
Ǔ 180°
* 90° Ǔ
p
ǒ
( )
margin * arg H ctrl_output fc
p
180°
w p1e
Select OTA Compensation Zero to Coincide
with Modulator Pole at fp1 (fz )
2p
Resulting OTA High Frequency Pole Placement (fp )
f zf c ) f c 2 tan(boost)
f c * f z tan(boost)
Compensation Resistor R2
V OUT
f p * f z 1.2g m
f pG
Ǹ
1)
Ǹ
1)
Compensation Capacitor C1
ǒǓ
2
fc
fp
ǒǓ
fz
fp
1
2pf zR 2
Compensation Capacitor C2
1
2pf pG
OTA DC Gain (G0_OTA )
@
R lowg m
R low ) R 1
R low
R low ) R 1
ȳ
R R C
1*
1*4
ȧ
ȧ
2 R R C
ǒR ) R Ǔ C ȴ
Ȳ
ǒ
Ǔ
ȳ
R R C
1 R )R ȱ
1)
1*4
ȧ
ȧ
2 R R C
ǒR ) R Ǔ C ȴ
Ȳ
ǒ
Ǔȱ
ȳ
R ǒR ) R ǓC
1 R )R )R
1
*
1
*
4
ȧ
ȧ
2 R ǒR ) R ǓC
ǒR ) R ) R Ǔ C ȴ
Ȳ
ǒ
Ǔȱ
ȳ
R ǒR ) R ǓC
1 R )R )R
1)
1*4
ȧ
ȧ
2 R ǒR ) R ǓC
ǒR ) R ) R Ǔ C ȴ
Ȳ
ǒ1 ) j w Ǔ ǒ1 ) j w2pf Ǔ
Low Frequency Zero (wz1e )
1
ǒR2 ) ResdǓȱ
@ gm @ R0
2 esd 2
High Frequency Zero (wz2e )
2
0
2
High Frequency Pole (wp2e )
2
0
0
2
OTA Transfer Function (GOTA (f))
2
0
2
esd
esd
2 esd 2
2
2
1
esd
Ǹ
Ǹ
esd
esd
2 esd 2
2
2
1
esd
Ǹ
esd
2 esd 2
Low Frequency Pole (wp1e )
Ǹ
2
2
0
0
2
2
0
esd
2
2
1
esd
0
esd
2
esd
2
2
1
2pf
z2e
z1e
-G 0_OTA
The open-loop-response in closed-loop form to verify the
gain/phase margins may be obtained from the following
expression.
ǒ
2pf
1 ) jw
p1e
Ǔǒ
2pf
1 )jw
p2e
Ǔ
device. Simply connect the voltage you would like to boost
to the inductor and connect the stable voltage to the VIN pin
of the device. In boost configuration, the output of the
converter can be used to power the device. In some cases it
may be desirable to connect 2 sources to VIN pin, which can
be accomplished simply by connecting each of the sources
through a diode to the VIN pin.
T(f) + G OTA(f) H ctrl_output(f)
Low Voltage Operation
If the input voltage drops below the UVLO or MOSFET
threshold voltage, another voltage may be used to power the
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16
NCV8871
SEPIC TOPOLOGY APPLICATION INFORMATION
VIN
L1
Oscillator
S Q
PWM Comparator
GDRV
Gate
Drive
R
+
CCPL
L2
Co
ISNS
CSA
RL
VFB
Voltage Error
VEA
NCV8871
Compensation
Figure 14. SEPIC Current Mode Schematic
SEPIC Design Methodology
From this the ideal minimum and maximum duty cycles
can be calculated as follows:
This section details an overview of the component
selection process for the NCV8871 in continuous
conduction mode SEPIC. It is intended to assist with the
design process but does not remove all engineering design
work. Many of the equations make heavy use of the small
ripple approximation. This process entails the following
steps:
1. Define Operational Parameters
2. Select Current Sense Resistor
3. Select SEPIC Inductors
4. Select Coupling Capacitor
5. Select Output Capacitors
6. Select Input Capacitors
7. Select Feedback Resistors
8. Select Compensator Components
9. Select MOSFET(s)
10. Select Diode
D min +
V OUT
V IN(max) ) V OUT
D max +
V OUT
V IN(min) ) V OUT
Both duty cycles will actually be higher due to power loss
in the conversion. The exact duty cycles will depend on
conduction and switching losses.
If the calculated DWC (worst case) is higher than the Dmax
limit of the NCV8871, the conversion will not be possible.
It is important for a SEPIC converter to have a restricted
Dmax, because while the ideal conversion ratio of a SEPIC
converter goes up to infinity as D approaches 1, a real
converter’s conversion ratio starts to decrease as losses
overtake the increased power transfer. If the converter is in
this range it will not be able to regulate properly.
If the following equation is not satisfied, the device will
skip pulses at high VIN:
1. Define Operational Parameters
Before beginning the design, define the operating
parameters of the application. These include:
VIN(min): minimum input voltage [V]
VIN(max): maximum input voltage [V]
VOUT: output voltage [V]
IOUT(max): maximum output current [A]
ICL: desired typical cycle−by−cycle current limit [A]
D min
w t on(min)
fs
Where: fs: switching frequency [Hz]
ton(min): minimum on time [s]
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17
NCV8871
2. Select Current Sense Resistor
Current mode control helps resolve some of the resonant
frequencies that create issues in voltage mode SEPIC
converter designs, but some resonance issues may occur. A
resonant frequency exists at
Current sensing for peak current mode control and current
limit relies on the MOSFET current signal, which is
measured with a ground referenced amplifier. Note that the
ICL equals the sum of the currents from both inductors. The
easiest method of generating this signal is to use a current
sense resistor from the source of the MOSFET to device
ground. The sense resistor should be selected as follows:
RS +
f resonance +
It may become necessary to place an RC damping network
in parallel with the coupling capacitor if the resonance is
within ~1 decade of the closed−loop crossover frequency.
The capacitance of the damping capacitor should be ~5
times that of the coupling capacitor. The optimal damping
resistance (including the ESR of the damping capacitor) is
calculated as
V CL
I CL
Where: RS: sense resistor [W]
VCL: current limit threshold voltage [V]
ICL: desire current limit [A]
3. Select SEPIC Inductors
R damping +
The output inductor controls the current ripple that occurs
over a switching period. A high current ripple will result in
excessive power loss and ripple current requirements. A low
current ripple will result in a poor control signal and a slow
current slew rate in case of load steps. A good starting point
for peak to peak ripple is around 20−40% of the inductor
current at the maximum load at the worst case VIN, but
operation should be verified empirically. The worst case VIN
is the minimum input voltage. After choosing a peak current
ripple value, calculate the inductor value as follows:
L+
V OUT(ripple) +
I OUT(max)D WC
C OUT f s
)
ǒ
I OUT(max)
1 * D WC
Ǔ
D WCV IN(min)
Ǹ
I Cout(RMS) +
2 f sL 2
R esr
ǒ
I OUT(max) 2 D WC ) I 2a )
Ǔ
I 2r
* I aI r DȀ WC
3
where
I a + I L1_peak ) I L2_peak * I out
V OUT I OUT(max)
I r + DI L1 ) DI L2
V IN(min)h
The use of parallel ceramic bypass capacitors is strongly
encouraged to help with the transient response.
The Peak Inductor current can be calculated as follows:
DI L1
2
6. Select Input Capacitors
The input capacitor reduces voltage ripple on the input to
the module associated with the ac component of the input
current.
DI L2
2
Where (if L1 = L2): DIL1 = DIL2
I Cin(RMS) +
4. Select Coupling Capacitor
Coupling capacitor RMS current is significant. A low
ESR ceramic capacitor is required as a coupling capacitor.
Selecting a capacitor value too low will result in high
capacitor ripple voltage which will distort ripple current and
diminish input line regulation capability. Budgeting 2−5%
coupling capacitor ripple voltage is a reasonable guideline.
DV coupling +
)
The capacitors need to survive an RMS ripple current as
follows:
Where: VIN(WC): VIN value as close as possible to half of
VOUT [V]
DWC: duty cycle at VIN(WC)
DIL,max: maximum peak to peak ripple [A]
The maximum average inductor current can be calculated as
follows:
I L2,peak + I OUT(max) )
L1 ) L2
C coupling
The output capacitors smooth the output voltage and
reduce the overshoot and undershoot associated with line
transients. The steady state output ripple associated with the
output capacitors can be calculated as follows:
DI L,max f s
I L1,peak + I L1,avg )
Ǹ
5. Select Output Capacitors
V IN(WC) D WC
I L,AVG +
1
2p Ǹ(L1 ) L2)C coupling
DI L1
Ǹ12
7. Select Feedback Resistors
The feedback resistors form a resistor divider from the
output of the converter to ground, with a tap to the feedback
pin. During regulation, the divided voltage will equal Vref.
The lower feedback resistor can be chosen, and the upper
feedback resistor value is calculated as follows:
I out D WC
C coupling f s
R upper + R lower
www.onsemi.com
18
ǒV out * V refǓ
V ref
NCV8871
9. Select MOSFET(s)
The total feedback resistance (Rupper + Rlower) should be
in the range of 1 kW – 100 kW.
In order to ensure the gate drive voltage does not drop out
the MOSFET(s) chosen must not violate the following
inequality:
8. Select Compensator Components
Current Mode control method employed by the
NCV8871 allows the use of a simple, Type II compensation
to optimize the dynamic response according to system
requirements.
Q g(total) v
Where: Qg(total): Total Gate Charge of MOSFET(s) [C]
Idrv: Drive voltage current [A]
fs: Switching Frequency [Hz]
The maximum RMS Current can be calculated as follows:
I D(max) +
Ǹ ǒ
D WC
I Q(peak) 2 )
ǒDI L1 ) DI L2Ǔ
3
I drv
fs
2
* I Q(peak)ǒDI L1 ) DI L2Ǔ
where
Ǔ
V Q(max) + V OUT(max) ) V IN(max)
I Q(peak) + I L1_peak ) I L2_peak
The maximum voltage across the MOSFET will be the
maximum output voltage, which is the higher of the
maximum input voltage and the regulated output voltaged:
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19
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
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